差分時(shí)鐘拓分析

差分時(shí)鐘拓?fù)浞治鯬egasusYU一、 仿真條件采用差分時(shí)鐘緩沖驅(qū)動(dòng)器SY100EP14作為驅(qū)動(dòng)器和接收器。將IBIS模型轉(zhuǎn)為Cadence仿真的DML模型，進(jìn)行差分信號(hào)完整性的仿真(LVPEC)。模型采用3.3V供電的模型。仿真75MHz差分時(shí)鐘信號(hào)，環(huán)境為Typicalo二、 仿真過(guò)程a)PMC推薦拓?fù)銹WE1jHEFI<^_FE^LiiiB__―IHDKiPLFKLMl(1.1F>■i^-yPWE1jHEFI<^_FE^LiiiB__―IHDKiPLFKLMl(1.1F>■i^-yDESIGNRECECVER]3DES[GHRECEIVERL4DESIGNRECECVER]3DES[GHRECEIVERL4cbfFfiaEDTOiix.￡:EHjrg.li-ugH疽Mi臥tHiEli[■f] 5lDriu￡￡l￡!CL>tL5:I&IUEB.1DES3G-H.R￡C￡[1￡TiL：320 0OiaSE 7jp FNW Fi]：LTHS1? 2533.網(wǎng)737.4T3IiIECCS.ISIVEEL2OESiGH.EECZEITEX.142■] a.aia^E丁邛 e典玖鴕H tTAlEECCJl.IfUVEDL1DEWKH.EECZCTD..L^.DESICr Ld_dLff21] a.|]1>]?E T戲 FAILFill-432.54-3 網(wǎng)W5.6T-397.b)USI推薦拓?fù)鋜；；SigHplcrerSIG原；＞iffclk_￥ST.teipI.0Prwje-rt;nf/rwhWrBrS.? 13間區(qū)|Eili口“ 的＜1典itttlpCflioPhlELRECE1VLE■nauiE商林＜i,JPEFJLJi'.fta^r-Sdr：-：FlHD1056a.mn我DGWIGNnr.lTElLDESIGNRECEIVER13-DESIGNRECEIVER14j±iffc)EMC推薦拓?fù)洌篋RIVERhrJlXthiqS。.頊，;￡2#*曜|國(guó)為赧S-aiKEIDvtTAT■L-R-HiSlVifeTLDESIGNDKIJE1LLTtfCFFnr.rnjiE30aola.wo5G三、分析及改進(jìn)很顯然，上面的三種波形，都不滿足時(shí)鐘信號(hào)單調(diào)性的要求。EMC的設(shè)計(jì)，由于不正確的偏置，導(dǎo)致輸入電壓擺幅過(guò)大°USI的設(shè)計(jì)，沒(méi)有加電源和地之間的電容，對(duì)電源平面受到的干擾考慮不足。將PMC的設(shè)計(jì)中，串接AC電容的容值改為1uf，見(jiàn)下圖仿真波形，沒(méi)有波形的優(yōu)良改善。單調(diào)性仍然不過(guò)

RFCF'\^=-RFCF'\^=-DRFP卜漁FCF'EIIrLzf上面PMC推薦的拓?fù)洌菗?jù)同事所說(shuō)，PMC有這樣串接AC電容的連接方式。根據(jù)打印出來(lái)的PMC差分時(shí)鐘設(shè)計(jì)部分原理圖，從晶振到時(shí)鐘驅(qū)動(dòng)芯片，沒(méi)有串接AC電容。從晶振的datasheet上看，也沒(méi)有推薦使用AC串接電容。所以，下面采用不串接AC耦合電容的拓?fù)?。RECEIVERuiiiJirEDRIVER*度PrlverRECEIVERuiiiJirEDRIVER*度PrlverC7C1E(LitckTv]FuslriSKodctitledS0i3eltaiE.in5Q"工mho,HAM5l|Over-BliQiilLDVr“]KrwDiel<TIU1DIWIGm.UMTEEL.I□ISICJl.ILECIIVIKim項(xiàng)i：i.>]L07GE宇0T1IL-ros.4€305$.23MIL.07L.5DESIGfl.DEEYEB.2DESIEn.BECEIVIL142d0.QL05GVyuPASSFUL-7(194$:扣刑2312U9.G&L.5:DISTM.UBCTEa1□zsteh.hecetvib.13_tje200.QL05ET-1SS弛*STG1B95SB-JB9S.SEl_LJ CES]G?Tlf_ZESIG]-[ L1_血：很顯然，去除AC耦合電容后，波形得到改善，接收到的時(shí)鐘信號(hào)已滿足單調(diào)性要求。因此，應(yīng)采用PMC推薦設(shè)計(jì)（不串接AC耦合電容）?？梢钥吹剑厦娴牟ㄐ稳匀淮嬖谒?，屬于不良的波形，仍然有可能影響單調(diào)性。因此，需要繼續(xù)進(jìn)行改進(jìn)。之前的偏置上下拉部分，是放在靠近驅(qū)動(dòng)器的一端。根據(jù)經(jīng)驗(yàn)，放在接收器一邊將會(huì)更好的吸收反射。改進(jìn)的拓?fù)洌篛R]i,'ER

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?>*學(xué)>casrO-MddJan?>*學(xué)>casrO-MddJan2L11.L9.202008DES[GNRECEIVERIrLDESIGMRECEIVERTime[ns]很明顯，波形已得到很好的改善。對(duì)于時(shí)鐘信號(hào)邊沿的單調(diào)性要求，已達(dá)到要求。并且電平部分的過(guò)沖也得到控制。四、結(jié)論1）采用下圖的拓?fù)浞绞竭B接差分時(shí)鐘信號(hào)（即PMC的推薦）2） 提供直流偏置的電阻部分，必須放置于靠近接收器的地方。距離接收器不要超過(guò)14mm，越近越好。3） 兩根耦合差分線的直流偏置部分，必須對(duì)稱放置。五、進(jìn)一步驗(yàn)證Fast和Slow是兩種極限仿真條件。如果在這兩種條件下，時(shí)鐘能夠滿足信號(hào)完整性要求，那么實(shí)際的信號(hào)就不會(huì)出問(wèn)題。即便不能滿足Fast和Slow條件，只要typical條件下足夠好，實(shí)際情況下，出問(wèn)題的概論會(huì)很小。

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