數(shù)字邏輯第四章課后答案

數(shù)字邏輯第四章課后答案盛建倫：《數(shù)字邏輯與VHDL邏輯設(shè)計(jì)》習(xí)題解答習(xí)題4解答4-1試用與非門設(shè)計(jì)實(shí)現(xiàn)函數(shù)F(A,B,C,D)=Σm(0,2,5,8,11,13,15)的組合邏輯電路。解：首先用卡諾圖對(duì)函數(shù)進(jìn)行化簡，然后變換成與非-與非表達(dá)式?；喓蟮暮瘮?shù)4-2CDAB00010010010111100110111000111000A&&BC&&&&&F&FBCDABDBCDACDBCDABDBCDACDBCDABDBCDACDD&試用邏輯門設(shè)10。解：本題的函數(shù)不能化簡，但可以變換成異或表達(dá)式，使電路實(shí)現(xiàn)最簡。真值表：邏輯函數(shù)表達(dá)式：ABC000001010011100101110111Y01101001=1ABC邏輯圖=1YYABCABCABCABC(AB)C4-1盛建倫：《數(shù)字邏輯與VHDL邏輯設(shè)計(jì)》習(xí)題解答4-3用與非門設(shè)計(jì)四變量多數(shù)表決電路。當(dāng)輸入變量A、B、C、D有三個(gè)或三個(gè)以上為1時(shí)輸出為1，輸入為其他狀態(tài)時(shí)輸出為0。解：真值表：先用卡諾圖化簡，然后變換成與非-與非表達(dá)式：ABCD00000010001101000101011001111000101010111100110111101111YABDABCBCDACDABDABCBCDACDABDABCBCDACDY00000010010111C&00010AB00011110CD00010000001011100111001010010邏輯圖A&B&&Y邏輯函數(shù)表達(dá)式：D4-4&44解：首先根據(jù)所給問題列出真值表，然后用卡諾圖化簡邏輯函數(shù)，按照化簡后的邏輯函數(shù)畫邏輯圖。4-2盛建倫：《數(shù)字邏輯與VHDL邏輯設(shè)計(jì)》習(xí)題解答真值表：卡諾圖化簡：ABCDY1Y2Y3Y400000000000100010010001100110010010001100101011101100101011101001000110010011101101011111011111011001010110110111110100111111000ABCD00011110000011011100111100100011Y3的卡諾圖化簡后的邏輯函數(shù)：Y1AY2ABABABY3BCBCBCY4CDCDCD4-3ABCD00011110000000010000111111101111Y1的卡諾圖ABCD00011110000000011111110000101111Y2ABCD00011110000101010101110101100101Y4邏輯圖Y1Y2Y3Y4=1=1=1ABCD盛建倫：《數(shù)字邏輯與VHDL邏輯設(shè)計(jì)》習(xí)題解答4-5圖4.48所示是一個(gè)由兩臺(tái)水泵向水池供水的系統(tǒng)。水池中安置了A、B、C三個(gè)水位傳感器。當(dāng)水池水位低于C點(diǎn)時(shí)，兩臺(tái)水泵同時(shí)供水。當(dāng)水池水位低于B點(diǎn)且高于C點(diǎn)時(shí)，由水泵M1單獨(dú)供水。當(dāng)水池水位低于A點(diǎn)且高于B點(diǎn)時(shí)，由水泵M2單獨(dú)供水。當(dāng)水池水位高于A點(diǎn)時(shí)，兩臺(tái)水泵都停止供水。試設(shè)計(jì)一個(gè)水泵控制電路。要求電路盡可能簡單。M1ABCM24.484-510。首先根據(jù)所給問題列出真值表。其中有幾種情況是不可能出現(xiàn)的，用約束項(xiàng)表示。ABC000001010011100101110111如果利用約束項(xiàng)化簡如果不利用約束項(xiàng)化簡M1M200A01BC000111100011A01BC000111100110011011M1M2M1BM1ABM2CABM1M2≥1M2ABCABCA(BC)M1&M2&=&1BACABC(a)用約束項(xiàng)化簡(b)不用約束項(xiàng)化簡4-4盛建倫：《數(shù)字邏輯與VHDL邏輯設(shè)計(jì)》習(xí)題解答習(xí)題4-5的邏輯圖4-63-874HC138畫出邏輯圖。Y1ABCA(BC)Y2ACABY3(AB)(AC)Y4ABCABC解：先將邏輯函數(shù)變換成最小項(xiàng)之和的形式Y(jié)1ABCABACABCABCABCABCY2ABCABCABCABCYABACABCABCABCABC374HC138&&Y4YABCABCABCABC2m7m4m3m2Y3ABCABCABCABCm7m5m3m2Y4ABCABCm7m0ABCY0Y1S3Y2Y374HC138Y4Y5A2Y6A1Y7A0S1S2Y1&Y2&Y3令74HC138的A2=A，A1=B，A0=C，4-73-874HC138Y32≤某<7Y=某－2某<2,Y=1=7,Y=6211Y7S3Y6S2Y5S1Y4A2A1A074HC138&&Y2Y1Y024-510Y3Y2Y1Y0&盛建倫：《數(shù)字邏輯與VHDL邏輯設(shè)計(jì)》習(xí)題解答4-144.503874HC13881構(gòu)成的電路。試分析①當(dāng)數(shù)據(jù)C2C1C0=D2D1D0時(shí)，輸出F=②當(dāng)數(shù)據(jù)C2C1C0≠D2D1D0輸出F=解：C2C1C0=D2D1D0F=0②C2C1C0≠D2D1D0F=1C2C1C0D2D1D04-153狀態(tài)都能控制電燈由亮變滅或者由滅變亮。用數(shù)據(jù)選擇器實(shí)現(xiàn)。1Y7Y6Y5Y474HC138Y3Y2Y1A2A1A0Y0C2C1C0S1S2S3D7D6D581擇器D4D3YFD2D1D0A2A1A0D2D1D04.504-14解：用A、B、C3Z=0ABC=000時(shí)的狀態(tài)Z=0。（比較容易得真值表，初始狀態(tài)也很重要）真值表：邏輯函數(shù)表達(dá)式：ABC000001010011100101110111Z01101001ZABCABCABCABC4-11盛建倫：《數(shù)字邏輯與VHDL邏輯設(shè)計(jì)》習(xí)題解答C341AB址，CAB1A1A0D3D2D1D0即A1=A，A0=B，D0=D3=C，D1=D2=C4-16邏輯圖41YZ/=1=0A、B/減的兩個(gè)數(shù)。做加法運(yùn)算時(shí)，S//SS=A+BS=A－BAB000001010011100101110111SCO0011100000101001邏輯函數(shù)不能化簡，但是可以變換成異或表達(dá)式。S某ABAB某AB某AB(AB)某(AB)S=1CO&ABCOABAB=(某A)B按照變換后的邏輯函數(shù)畫邏輯圖。AB4-173-874HC1381的借位信號(hào)。解：全減器的功能是Si=Ai－Bi－Ci。首先根據(jù)所給問題列出真值表。真值表：邏輯函數(shù)：AiBiCiSiCOSAiBiCAiBCiABiCiABCiiiiiii4-12盛建倫：《數(shù)字邏輯與VHDL邏輯設(shè)計(jì)》習(xí)題解答0000010100111001011101110011110110000011COAiBiCiAiBiCiAiBiCiAiBiCi74HC138SiAiBiCiAiBiCiAiBiCiAiBiCim1m2m4m71247mmmm4-181COAiBiCiAiBiCiAiBiCiAiBiCim1m2m3m7m1m2m3m7AiBiCiY73SY6S2Y5S1Y4A2A1A074HC138&SiY3Y2Y1Y0&CO4CC14585D3D2D1D0>100110。解：從CC14585的一個(gè)端口輸入數(shù)據(jù)D3D2D1D0，另一個(gè)端口輸入1001。CC14585的擴(kuò)展輸入端IA>B和IA=B必須接高電平，IA1001邏輯圖D0D1D2D31A0A1A2CC14585A3IABYABIABYABIABYABB0B1B2B3F4-19試根4.24er）A1、A0、W2W1、W0從N4.514.244-194-13盛建倫：《數(shù)字邏輯與VHDL邏輯設(shè)計(jì)》習(xí)題解答A1A0D000001010011100101110111DW3W2W1W000000001000000100000010000001000W3W2W1W0DeMU某A1A04.51解：表4.24的功能表可以簡化為A1A0W3W2W1W000000D0100D0100D0011D000邏輯函數(shù)W0A1A0D邏輯圖W3&W2&W1&W0&W1A1A0DW2A1A0DW3A1A0DA1A011D4-20試比較圖4.52所示兩個(gè)邏輯電路的功能。F1&101DCBAA0D0D1D2D3D4D5D6D7A181A3A2A1A0AF24-14BCDVHDL4.524-204.5281D6=D7=D，D1=0，D2=1，D5=D4=D3=D0=D，A2=A，A1=B，A0=C，所以，F(xiàn)2ABCD7ABCD6ABCD5ABCD4ABCD3ABC1ABCD0ABCDABCDABCDABCDABCDABCABCDABCDABCDABCDABCDABCDABCDABCDABCDF1m15m13m10m8m6m5m4m0ABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCDABCD比較FI和F24-21用VHDL44進(jìn)制代碼。解：首先畫出代碼轉(zhuǎn)換電路的系統(tǒng)框圖，如根據(jù)所給問題列出真值表。G3G2G1G000000001001100100110011101010100B3B2B1B000000001001000110100010101100111G3B3代碼轉(zhuǎn)換電路… G0B04-15盛建倫：《數(shù)字邏輯與VHDL邏輯設(shè)計(jì)》習(xí)題解答1100110111111110101010111001100010001001101010111100110111101111根據(jù)系統(tǒng)框圖寫VHDL程序的Entity表寫VHDLArchitecture。VHDL程序如下：--GraycodetoBinarycodelibraryieee;ueieee.td_logic_1164.all;entitygray2binaryiport(grayin:intd_logic_vector(3downto0);binaryout:outtd_logic_vector(3downto0));endgray2binary;architecturebehaveofgray2binaryibeginwithgrayinelectbinaryout<=\\\\\\\\\\\\\\\\endbehave;4-16盛建倫：《數(shù)字邏輯與VHDL邏輯設(shè)計(jì)》習(xí)題解答4-22用VHDL470~9A，b，C，d，E，F(xiàn)。47D3~D0號(hào)名，用Ya~Yga、b、c、d、efg7系統(tǒng)框圖……列出代碼轉(zhuǎn)換邏輯的真值表。4.12D3D2D1D0YaYbYcYdYeYfYg0000000100100011010001010110011110001001101010111100110111101111根據(jù)系統(tǒng)框圖設(shè)計(jì)VHDL程序的entity，用行為描述的方法，根據(jù)真值表設(shè)4-17YaYbYcYdYeYfYg代碼轉(zhuǎn)換電路D3D2D1D0…顯示字符0123456789AbCdEF字形1111110011000011011011111001011001110110111011111111000011111111110011111011100111111001110011110110011111000111盛建倫：《數(shù)字邏輯與VHDL邏輯設(shè)計(jì)》習(xí)題解答計(jì)VHDL程序的architecture。libraryieee;ueieee.td_logic_1164.all;entitybcd2eg7iport(bcdin:intd_logic_vector(3downto0);egout:outtd_logic_vector(6downto0));endbcd2eg7;architecturebehavofbcd2eg7ibeginwithbcdinelectegout<=\--diplay\\\\\\\\--diplay\\\--diplay\\--diplay\\--diplay\\--diplay\\--diplay\\--diplay\\--diplay\\endbehave;用VHDL7位的ASCII70~9，字母A，b，C，d，E，F(xiàn)，H，L，o，P，U，等。解：ASCII7Yg0盛建倫：《數(shù)字邏輯與VHDL邏輯設(shè)計(jì)》習(xí)題解答123456789AbCdEFHLoPU00000000011111111111111111111010100001001111111110000000001100000001100000011100000111100000111011010110011000110010010010101010110101000101011011111101011000101111001111001001001110111111111010010101011011010011110011010100010101111111111100011101111101111011011111011110111101104-23用VHDL設(shè)計(jì)一個(gè)16位全加器。解：4-24用VHDL8用VHDL4-19盛建倫：《數(shù)字邏輯與VHDL邏輯設(shè)計(jì)》習(xí)題解答--4-Bitcarry-look-aheadFullAdderlibraryieee;ueieee.td_logic_1164.all;entityFULL_ADDER1iport(A,B:inbit_vector(3downto0);Cin:inbit;S:outbit_vector(3downto0);Cout:outBIT);endFULL_ADDER1;--architectureFULL_ADDERpofFULL_ADDER1iignalA,B,S:bit_vector(3downto0);ignalCin,Cout:bit;ignalC:bit_vector(3downto0);ignalT:bit_vector(3downto0);ignalG:bit_vector(3downto0);beginA<=A;B<=B;Cin<=Cin;T(0)<=A(0orB(0);--P0G(0)<=A(0)andB(0);--G0T(1)<=A(1)orB(1);--P1G(1)<=A(