VHDL數(shù)字鐘設(shè)計(jì)方案報(bào)告

VHDL數(shù)字鐘設(shè)計(jì)方案報(bào)告VHDL數(shù)字鐘設(shè)計(jì)報(bào)告數(shù)字鐘總體設(shè)計(jì)方案：=1\*GB3①正確顯示時(shí)、分、秒；=2\*GB3②可手動(dòng)校時(shí)，能分別進(jìn)行時(shí)、分的校正；=3\*GB3③整點(diǎn)報(bào)時(shí)功能；數(shù)字鐘的設(shè)計(jì)模塊包括：分頻器、去抖動(dòng)電路、校時(shí)電路、“時(shí)、分、秒”計(jì)數(shù)器、校時(shí)閃爍電路、整點(diǎn)報(bào)時(shí)和譯碼顯示電路。每一個(gè)功能模塊作為一個(gè)實(shí)體單獨(dú)進(jìn)行設(shè)計(jì)，最后再用VHDL的例化語句將各個(gè)模塊進(jìn)行整合，生成頂層實(shí)體top。該數(shù)字鐘可以實(shí)現(xiàn)3個(gè)功能：計(jì)時(shí)功能、設(shè)置時(shí)間功能和報(bào)時(shí)功能。二．?dāng)?shù)字鐘模塊細(xì)節(jié)分頻器（fenpin）本系統(tǒng)共需3種頻率時(shí)鐘信號(hào)（1024Hz、512Hz、1Hz）。為減少輸入引腳，本系統(tǒng)采用分頻模塊，只需由外部提供1024Hz基準(zhǔn)時(shí)鐘信號(hào)，其余三種頻率時(shí)鐘信號(hào)由分頻模塊得到。分頻原理：為以1024Hz基準(zhǔn)時(shí)鐘經(jīng)1024分頻得到512Hz,1Hz頻率時(shí)鐘信號(hào)。分頻器管腳代碼：libraryieee;use;use;use;entityfenpinisport(clk1024:instd_logic; clk1,clk512:outstd_logic );endfenpin;architecturecmloffenpinisbeginprocess(clk1024)variablecount1:integerrange0to512;variableq1:std_logic;beginifclk1024'eventandclk1024='1'thenifcount1=512then q1:=notq1; count1:=0; elsecount1:=count1+1;endif;endif;clk1<=q1;endprocess;process(clk1024) variablecount512:integerrange0to1;variableq512:std_logic;begin ifclk1024'eventandclk1024='1'then ifcount512=1then q512:=notq512; count512:=0; elsecount512:=count512+1;endif;endif;clk512<=q512;endprocess;endcml; 2．2校時(shí)電路（jiaoshi）本模塊要實(shí)現(xiàn)的功能是：正常計(jì)時(shí)、校時(shí)、校分在每個(gè)狀態(tài)下都會(huì)產(chǎn)生不同控制信號(hào)實(shí)現(xiàn)相應(yīng)的功能。校時(shí)管腳圖代碼：libraryieee;use;use;entityjiaoshiisport(rst,rvs,select_rvs,mtime,mclkin,hclkin:instd_logic;hclkout,mclkout:outstd_logic);endjiaoshi;architecturecmlofjiaoshiissignalh_m:std_logic;beginp1:process(rst,rvs,hclkin,mclkin,h_m,mtime)beginifrst='0'thennull;elsifrvs='1'thenhclkout<=hclkin;mclkout<=mCLKin;elsifh_m='0'thenhclkout<=hclkin;mclkout<=mtime;elsehclkout<=mtime;mclkout<=mclkin;endif;endprocess;p2:process(select_rvs) begin ifselect_rvs'eventandselect_rvs='1'then h_m<=noth_m; endif;endprocess;endcml;管腳圖仿真圖時(shí)計(jì)數(shù)器（hour）分計(jì)數(shù)器(mine)秒計(jì)數(shù)器(second)時(shí)計(jì)數(shù)器管腳圖時(shí)代碼：libraryieee;use;use;entityhourisport(rst,hclk:instd_logic;hour0,hour1:bufferstd_logic_vector(3downto0));endhour;architecturecmlofhourisbeginprocess(rst,hclk,hour0,hour1)beginifrst='0'then hour0<="0000"; hour1<="0000";elsifhclk'eventandhclk='1'thenifhour0="0011"andhour1="0010"thenhour0<="0000";hour1<="0000";elsifhour0="1001"thenhour0<="0000";hour1<=hour1+1;elsehour0<=hour0+1;endif;endif;endprocess;endcml;分計(jì)數(shù)器管腳圖分代碼：libraryieee;use;use;entitymineisport(rst,mclk:instd_logic;mco:outstd_logic;min0,min1:bufferstd_logic_vector(3downto0));endmine;architecturecmlofmineissignalmin0_t,min1_t:std_logic_vector(3downto0);beginprocess(rst,mclk,min0,min1)beginifrst='0'then min0<="0000"; min1<="0000";elsifmclk'eventandmclk='1'thenifmin0="0101"andmin1="1001"thenmin0<="0000";min1<="0000";mco<='1';elsifmin0="0010"andmin0="1001"thenmin1<="0011";min0<="0000";downto0));endsecond;architecturecmlofsecondissignalsec0_t,sec1_t:std_logic_vector(3downto0);beginprocess(rst,sclk,sec0,sec1)beginifrst='0'then sec0<="0000"; sec1<="0000";elsifsclk'eventandsclk='1'thenifsec0="0101"andsec1="1001"thensec0<="0000";sec1<="0000";sco<='1';elsifsec0="0010"andsec0="1001"thensec1<="0011";sec0<="0000";sco<='0'; elsifsec0="1001"thensec1<=sec1+1;sec0<="0000";elsesec0<=sec0+1;endif;endif;endprocess;endcml;校時(shí)閃爍電路（flashnjiaoshi）如果正在進(jìn)行校時(shí)，flashjiaoshi將實(shí)現(xiàn)使當(dāng)前正在校時(shí)項(xiàng)（小時(shí)或分鐘）以1Hz的頻率閃爍，以便于操知道正在被校正。校時(shí)閃爍電路管腳圖代碼：libraryieee;use;use;entityflashjiaoshiisport(rst,sclk,rvs,select_rvs:instd_logic;hour0in,hour1in,min0in,min1in:instd_logic_vector(3downto0);hour0out,hour1out,min0out,min1out:outstd_logic_vector(3downto0));endflashjiaoshi;architecturecmlofflashjiaoshiissignalh_m:std_logic;beginp1:process(rst,sclk,rvs,hour0in,hour1in,min0in,min1in,h_m)beginifrst='0'thennull;elsifrvs='1'thenhour0out<=hour0in; hour1out<=hour1in; min0out<=min0in; min1out<=min1in;elsifh_m='0'thenhour0out<=hour0in;hour1out<=hour1in;ifsclk='1'thenmin0out<=min0in;min1out<=min1in;elsemin0out<="1111";min1out<="1111"; endif; else min0out<=min0in; min1out<=min1in; IFsCLK='1'then hour0out<=hour0in; hour1out<=hour1in; else hour0out<="1111"; hour1out<="1111"; endif; endif;endprocessp1;p2:process(select_rvs)begin ifselect_rvs'eventandselect_rvs='1'thenh_m<=noth_m;endif;endprocessp2;endcml;整點(diǎn)報(bào)時(shí)電路整點(diǎn)報(bào)時(shí)管腳圖代碼：libraryieee;use;use;entitybaoshiis port(clk1024,clk512:instd_logic;min0,min1,sec0,sec1:instd_logic_vector(3downto0);speak:outstd_logic);endbaoshi;architecturecmlofbaoshiisbeginspeak<=clk512when(min1="0101"andmin0="1001"andsec1="0101")and(sec0="0011"orsec0="0101"orsec0="0111")else clk1024 when(min1="0101"andmin0="1001"andsec1="0101"andsec0="1001")else '0'; endcml;譯碼顯示電路該顯示用的是動(dòng)態(tài)掃描電路譯碼顯示管腳圖波形圖代碼：libraryieee;use;use;entityxianshiisport(clk512:instd_logic;h1,h0,m1,m0,s1,s0:instd_logic_vector(3downto0);seg7:outstd_logic_vector(6downto0);select_sig:outstd_logic_vector(5downto0));endxianshi;architecturecmlofxianshiissignaldata:std_logic_vector(3downto0);signalorder:std_logic_vector(2downto0);beginprocess(clk512)beginifclk512'eventandclk512='1'thencaseorderiswhen"000"=>data<=h1;select_sig<="011111"; when"001"=>data<=h0;select_sig<="101111"; when"010"=>data<=m1;select_sig<="110111"; when"011"=>data<=m0;select_sig<="111011"; when"100"=>data<=s1;select_sig<="111101"; when"101"=>data<=s0;select_sig<="111110"; whenothers=>data<="1000";select_sig<="111111";endcase; iforder="101"thenorder<="000"; elseorder<=order+1; endif;endif;endprocess;process(data) begin casedatais when"0000"=>seg7<="0000001"; when"0001"=>seg7<="1001111"; when"0010"=>seg7<="0010010"; when"0011"=>seg7<="0000110"; when"0100"=>seg7<="1001100"; when"0101"=>seg7<="0100100"; when"0110"=>seg7<="0100000"; when"0111"=>seg7<="0001111"; when"1000"=>seg7<="0000000"; when"1001"=>seg7<="0000100"; whenothers=>seg7<="1111111"; endcase;endprocess;endcml ; 數(shù)字鐘整體設(shè)計(jì)（top）本數(shù)字鐘的設(shè)計(jì)包括分頻器、去抖動(dòng)電路、校時(shí)電路、“時(shí)、分、秒”計(jì)數(shù)器、校時(shí)閃爍電路和譯碼顯示電路。以上已經(jīng)有了各個(gè)功能模塊的實(shí)現(xiàn)方法，現(xiàn)在將各個(gè)模塊綜合在一起，構(gòu)成一個(gè)完整的數(shù)字鐘。代碼：libraryieee;use;use;entitytopisport(clk1024,key,reset:instd_logic;keyin:instd_logic_vector(1downto0);select_sigout:outstd_logic_vector(5downto0);seg7out:outstd_logic_vector(6downto0);speak:outstd_logic);endtop;architecturecmloftopiscomponentfenpinisport(clk1024:instd_logic; clk1,clk512:outstd_logic );endcomponentfenpin;componentjiaoshiisport(rst,rvs,select_rvs,mtime,mclkin,hclkin:instd_logic;hclkout,mclkout:outstd_logic);endcomponentjiaoshi;componenthourisport(rst,hclk:instd_logic;hour0,hour1:bufferstd_logic_vector(3downto0));endcomponenthour;componentminuteisport(rst,mclk:instd_logic;mco:outstd_logic;min0,min1:bufferstd_logic_vector(3downto0));endcomponentminute;componentsecondisport(rst,sclk:instd_logic;sco:outstd_logic;sec0,sec1:bufferstd_logic_vector(3downto0));endcomponentsecond;componentflashjiaoshiisport(rst,sclk,rvs,select_rvs:instd_logic;hour0in,hour1in,min0in,min1in:instd_logic_vector(3downto0);hour0out,hour1out,min0out,min1out:outstd_logic_vector(3downto0));endcomponentflashjiaoshi;componentxianshiisport(clk512:instd_logic;h1,h0,m1,m0,s1,s0:instd_logic_vector(3downto0);seg7:outstd_logic_vector(6downto0);select_sig:outstd_logic_vector(5downto0));endcomponentxianshi;componentbaoshiis port(clk1024,clk512:instd_logic;min0,min1,sec0,sec1:instd_logic_vector(3downto0);speak:outstd_logic);endcomponentbaoshi;signalscanCLKSig:std_logic;signalsecCLKSig:std_logic;signalhCLKSig0,hCLKSig1:std_logic;signalmCLKSig0,mCLKSig1:std_logic;signalsec1Sig,sec0Sig:std_logic_vector(3downto0);signalmin1Sig0,min0Sig0:std_logic_vector(3downto0);signalmin1Sig1,min0Sig1:std_logic_vector(3downto0);signalhour1Sig0,hour0Sig0:std_logic_vector(3downto0);signalhour1Sig1,hour0Sig1:std_logic_vector(3downto0);beginU1:fenpinPORTMAP(clk1024=>clk1024,clk512=>scanCLKSig,clk1=>secCLKSig);U2:jiaoshiPORTMAP(rst=>reset,rvs=>key,select_rvs=>keyin(0),mtime=>keyin(1),hclkin=>hCLKSig0,mclkin=>mCLKSig0,hclkout=>hCLKSig1,mclkout=>mCLKSig1);U3:hourPORTMAP(rst=>reset,hCLK=>hCLKSig1,hour1=>hour1Sig0,hour0=>hour0Sig0);