第三章數(shù)字邏輯課件

Chapter3DigitalCircuits

(數(shù)字電路)GiveaknowledgeoftheElectricalaspectsofDigitalCircuits(介紹數(shù)字電路中的電氣知識)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)1DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)ReviewofChapter3PositiveLogicandNegativeLogic(正邏輯和負邏輯)Threebasiclogicfunctions:AND,OR,andNOT

(三種基本邏輯：與、或、非)VOUTVINVccR獲得高、低電平的基本原理2ReviewofChapter3(第三章內(nèi)容回顧)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)ThreekindsofDescriptionMethod

(三種描述方法)：

TruthTable(真值表)

LogicExpression(邏輯表達式)

LogicCircuit(邏輯符號)NANDandNOR(與非和或非)3ReviewofChapter3(第三章內(nèi)容回顧)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)LogicFamilies:TTLFamilyandCMOSFamily(邏輯系列：TTL系列和CMOS系列)CMOSLogicLevel(CMOS邏輯電平)Drain(漏極)Source(源極)Gate(柵極)Vgs+Source(源極)Drain(漏極)Gate(柵極)

+VgsP-Channel

(P溝道)N-Channel

(N溝道)4VDD=+5.0VVOUTVINTpTnVCCAZCMOSInverter(CMOS反相器)DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)ReviewofChapter35VCCAZCMOSInverter(CMOS反相器)VDD=+5.0VZABCMOSNANDGate(CMOS與非門)ReviewofChapter3DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)6VCCAZCMOSInverter(CMOS反相器)VDD=+5.0VZABCMOSNORGate

(CMOS或非門)ReviewofChapter3DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)7VCCAZCMOSInverter

(CMOS反相器)VDD=+5.0VAZNon-invertingGate

(非反相門)ReviewofChapter3DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)8TheAdditive“on”ResistanceofseriestransistorslimitstheFan–InofCMOSgates.

(導通電阻的可加性限制了CMOS門的扇入數(shù))VDD=+5.0VZABVDD=+5.0VZABReviewofChapter3DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)9DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)3.4ElectronicBehaviorofCMOSCircuits(CMOS電路的電氣特性)LogicVoltageLevels(邏輯電壓電平)DCNoiseMargins

(直流噪聲容限)Fun-Out(扇出)物理上的而不是邏輯上的103.4ElectronicBehaviorofCMOSCircuits(CMOS電路的電氣特性)Speed,PowerConsumption

(速度、功耗)Noise,ElectrostaticDischarge

(噪聲、靜電放電)Open-DrainOutputs,ThreeStateOutputs(漏極開路輸出、三態(tài)輸出)DataSheet（數(shù)據(jù)表）Specifications(規(guī)格說明)（Table3-3P99）DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)113.5CMOSSteady-StateElectricalBehavior(CMOS穩(wěn)態(tài)電氣特性)LogicLevelsandNoiseMargins

(邏輯電平和噪聲容限)VDD=+5.0VVOUTVINTpTnVOUTVIN5.01.53.55.0電壓傳輸特性DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)12LogicLevelsSpecifications(邏輯電平規(guī)格)HIGH(高態(tài))ABNOMAL(不正常狀態(tài))LOW(低態(tài))VOLmaxVILmaxVIHminVOHminVCC－0.1V地＋0.1V0.7VCC0.3VCCDigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)3.5CMOSSteady-StateElectricalBehavior(CMOS穩(wěn)態(tài)電氣特性)13DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)DCNoiseMargin（直流噪聲容限）HIGH(高態(tài))ABNOMAL(不正常狀態(tài))LOW(低態(tài))VOLmaxVILmaxVIHminVOHmin30%VCC－0.1V3.5CMOSSteady-StateElectricalBehavior(CMOS穩(wěn)態(tài)電氣特性)Howmuchnoiseittakestocorruptaworse-caseoutputvoltageintoavaluethatmaynotberecognizedproperlybyaninput.(多大的噪聲會使最壞輸出電壓被破壞得不可識別)14LogiclevelandnoisemarginTheinputlimit:toavoidthenoisebeamplified!15DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)3.5.2CircuitBehaviorwithResistiveLoads(帶電阻性負載的電路特性)Requirenontrivialamountsofcurrenttooperate(要求有一定的驅(qū)動電流才能工作)VCCAZVCCRThevRpRnVThev

+VOUTVIN16DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)VCC=+5.0VRp>1MRnResistiveLoads(電阻性負載)VOLmaxIOLmaxWhentheOutputintheLOWstate(輸出為低態(tài)時)VOUT<=VOLmaxTheOutputsinkCurrent(輸出端吸收電流)TheMaximumCurrenttheOutputcansink[能吸收的最大電流IOLmax（灌電流）]3.5.2CircuitBehaviorwithResistiveLoads(帶電阻性負載的電路特性)17DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)VCC=+5.0VRpRn>1MResistiveLoads(電阻性負載)VOHminIOHmaxWhentheOutputintheHIGHstate(輸出為高態(tài)時)VOUT>=VOHminTheOutputSourceCurrent(輸出端提供電流)TheMaximumCurrenttheOutputcanSource[能提供的最大電流IOHmax（拉電流）]3.5.2CircuitBehaviorwithResistiveLoads(帶電阻性負載的電路特性)18DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)VCC=+5.0VRThevVThev

+WhentheOutputintheHIGHstate,EstimatetheSourcecurrent(輸出為高態(tài)時，估計提供電流)：3.5.2CircuitBehaviorwithResistiveLoads(帶電阻性負載的電路特性)19VCC=+5.0VRThevVThev

+WhentheOutputintheLOWstate,EstimatetheSinkcurrent(輸出為低態(tài)時，估計吸收電流)：DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)3.5.2CircuitBehaviorwithResistiveLoads(帶電阻性負載的電路特性)20VCC=+5.0V4002.5kVIN1.5VVOUT4.31VVCC=+5.0V4k200VIN3.5VVOUT0.24VOutputvoltageawayfromthepower-supplyrail(Furtherwitharesistiveload[輸出電壓變壞（有電阻性負載時更差）]What’sworse:Outputcurrent,PowerConsumption(更糟糕的是：輸出端電流，功耗)3.5.3CircuitBehaviorwithNon-idealInputs(非理想輸入時的電路特性)21DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)3.5.4Fan-out（扇出）TheNumberofInputsthattheGatecandrivewithoutexceedingitsworst-caseloadingspecifications.(在不超出其最壞情況負載規(guī)格的條件下，一個邏輯門能驅(qū)動的輸入端個數(shù)。)Fan-outmustbeexaminedforbothpossibleoutputstates,HIGNandLOW

(扇出需考慮輸出高電平和低電平兩種狀態(tài))OverallFan-out=Min(HIGH-stateandLOW-state[總扇出＝min（高態(tài)扇出，低態(tài)扇出）]DCFan-outandACFan-out

(直流扇出和交流扇出)22DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)74HCTDrives74LSLOWFan-Out(低態(tài)扇出):Fan-out(扇出)

HIGHFan-Out(高態(tài)扇出)：高態(tài)剩余驅(qū)動能力：CMOS:74HCTIOH=–4mAIOL=4mAIIH=1AIIL=–1ATTL:74LSIOH=–400AIOL=8mAIIH=20AIIL=–0.4mA總扇出23DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)3.5.5EffectsofLoading(負載效應)

LoadinganOutputBeyonditsratedFan-out[當輸出負載大于它的扇出能力時]OutputVoltagebecomeWorse

[輸出電壓變差（不符合邏輯電平的規(guī)格）]PropagationDelay,RiseandFalltimemayIncrease

(傳輸延遲和轉(zhuǎn)換時間變長)TemperatureofthedevicemayIncrease,ReducingReliability,CausingdeviceFailure(溫度可能升高，可靠性降低，器件失效)24DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)3.5.6UnusedInputs

(不用的CMOS輸入端)NeverbeleftUnconnected(orFloating)

(不用的CMOS輸入端絕不能懸空)XZ1k+5VXZXZIncreasethecapacitiveloadonthedrivingsignalandmayslowthingsdown.(增加了驅(qū)動信號的電容負載，使操作變慢)25DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)CurrentSpikesandDecouplingCapacitors(電流尖峰和去耦電容器)電流傳輸特性iDvI12VDDVDD=+5.0VVOUTVINTpTn26DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)3.6CMOSDynamicElectricalBehavior(CMOS動態(tài)電氣特性)BoththeSpeedandPowerConsumptionofaCMOSdevicedependtoalargeextentonACorDynamicCharacteristicsofthedeviceanditsload(CMOS器件的速度和功耗在很大程度上取決于器件及其負載的動態(tài)特性。)273.6CMOSDynamicElectricalBehavior(CMOS動態(tài)電氣特性)Speeddependsontwocharacteristics(速度取決于兩個特性)：TransitionTime（轉(zhuǎn)換時間）PropagationDelay（傳播延遲）TheamountofTimethattheOutputofalogiccircuittakestoChangefromonestatetoanother.(邏輯電路的輸出從一種狀態(tài)變?yōu)榱硪环N狀態(tài)所需的時間)TheamountofTimethatittakesforaChangeintheInputsignaltoproduceaChangeintheOutputsignal.(從輸入信號變化到產(chǎn)生輸出信號變化所需的時間)Figure3-36Figure3-42DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)28DigitalLogicDesignandApplication(數(shù)字邏輯設(shè)計及應用)3.6.1TransitionTime(轉(zhuǎn)換時間)

Risetime(tr)andFalltime(tf

)(上升時間tr

和下降時間tf

)The“On”transistorResistance

(晶體管的“導通”電阻)StrayCapacitance（寄生電容）VCC=+5.0VRLRpRnVL+CL電容兩端電壓不能突變“Time-ConstantequalsTransition-Time”(在實際電路中,可用時間常數(shù)近似轉(zhuǎn)換時間)293.6.2PropagationDelay(傳播延遲)VINVOUTSignalPath:theelectricalpathfromaparticularinputsignaltoaparticularoutputsignal