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Advance

FLASHMEMORY

K9LAG08U1MK9G8G08U0M

PAGE

10

K9XXG08UXM

INFORMATIONINTHIS

ISPROVIDEDINRELATIONTOSAMSUNGPRODUCTS,

ANDISSUBJECTTOCHANGEWITHOUTNOTICE.

NOTHINGINTHIS

SHALLBECONSTRUEDASGRANTINGANYLICENSE,

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*SamsungElectronicsreservestherighttochangeproductsorspecificationwithoutnotice.

Title

1Gx8Bit/2Gx8BitNANDFlashMemory

RevisionHistory

RevisionNo

History

DraftDate

Remark

0.0

0.1

0.2

0.3

0.4

0.5

Initialissue

Cycletimeischangedfrom35nsto30ns

Technicalnoteischanged.

ACPara.tRHWdeleted

thepowerrecoverytimeofminmumischangedfrom10sto100s(p38)

Leadedpartiseliminated.

tR50us->60us(p.3,12,31)

tRHW,tCSDparameterisdefined.

Technicalnoteisadded.(p.16)

Enduranceischanged(10K->5K)

Max.tPROGischanged(2ms->3ms)

Feb.1st2005

Apr.1st2005

Sept.1.2005

Mar.20th.2006

Apr.20th2006

Apr.25th2006

AdvanceAdvance

Advance

Advance

AdvanceAdvance

TheattacheddatasheetsarepreparedandapprovedbySAMSUNGElectronics.SAMSUNGElectronicsCO.,.reservetherighttochangethespecifications.SAMSUNGElectronicswillevaluateandreplytoyourrequestsandquestionsaboutdevice.Ifyouhaveanyquestions,pleasecontacttheSAMSUNGbranchofficenearyouroffice.

1Gx8Bit/2Gx8BitNANDFlashMemory

PRODUCTLIST

PartNumber

VccRange

Organization

PKGType

K9G8G08U0M-P

2.7V~3.6V

X8

TSOP1

K9G8G08U0M-I

52ULGA

K9LAG08U1M-I

FEATURES

VoltageSupply:2.7V~3.6V

Organization

MemoryCellArray:(1G+32M)bitx8bit

DataRegister :(2K+64)bitx8bit

AutomaticProgramandErase

PageProgram:(2K+64)Byte

BlockErase :(256K+8K)Byte

PageReadOperation

PageSize:(2K+64)Byte

RandomRead:60s(Max.)

SerialAccess:30ns(Min.)

MemoryCell:2bit/MemoryCell

FastWriteCycleTime

Programtime:800s(Typ.)

BlockEraseTime:1.5ms(Typ.)

Command/Address/DataMultiplexedI/OPort

HardwareDataProtection

-Program/EraseLockoutDuringPowerTransitions

ReliableCMOSFloating-GateTechnology

Endurance:5KProgram/EraseCycles(with4bit/512byteECC)

DataRetention:10Years

CommandRegisterOperation

UniqueIDforCopyrightProtection

Package:

K9G8G08U0M-PCB0/PIB0:Pb-PACKAGE

48-PinTSOPI(12x20/0.5mmpitch)

K9G8G08U0M-ICB0/IIB0

52-PinULGA(12x17/1.00mmpitch)

K9LAG08U1M-ICB0/IIB0

52-PinULGA(12x17/1.00mmpitch)

GENERALDESCRIPTION

Offeredin1Gx8bit,theK9G8G08U0Misa8G-bitNANDFlashMemorywithspare256M-bit.ItsNANDcellprovidesthemostcost-effectivesolutionforthesolidstatemassstoragemarket.Aprogramoperationcanbeperformedintypical800sonthe2,112-bytepageandaneraseoperationcanbeperformedintypical1.5msona(256K+8K)byteblock.Datainthedataregistercanbereadoutat30nscycletimeperbyte.TheI/Opinsserveastheportsforaddressanddatainput/outputaswellascommandinput.Theon-chipwritecontrollerautomatesallprogramanderasefunctionsincludingpulserepetition,whererequired,andinternalverificationandmarginingofdata.Eventhewrite-intensivesystemscantakeadvantageoftheK9G8G08U0Mtendedreliabilityof5Kprogram/erasecyclesbyprovidingECC(ErrorCorrectingCode)withrealtimemap-outalgorithm.TheK9G8G08U0Misanoptimumsolu-tionforlargenonvolatilestorageapplicationssuchassolidstatefilestorageandotherportableapplicationsrequiringnon-volatility.

PINCONFIGURATION(TSOP1)

K9G8G08U0M-PCB0/PIB0

N.C

N.C

N.C

N.C

N.C

N.C

R/BRECEN.C

N.C

VccVssN.C

N.CCLEALEWEWPN.C

N.C

N.C

N.C

N.C

N.C

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

48-pinTSOP1

StandardType

12mmx20mm

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

N.C

N.C

N.CI/O7I/O6I/O5I/O4N.C

N.C

N.C

VccVssN.C

N.C

N.CI/O3I/O2I/O1I/O0N.C

N.C

N.C

N.C

0.16+0.07

-0.03

050

0.0197

0.008+0.003

-0.001

0.25TYP

0.010

0.125+0.075

0.035

0.005+0.003

-0.001

12.40MAX

0.488

12.00

0.472

(0.25)

0.010

PACKAGEDIMENSIONS

0.004MAX

0.10

Unit:mm/Inch

20.000.20

0.7870.008

#1

#48

#24

#25

1.000.05

0.0390.002

0.05MIN

0.002

18.400.10

0.7240.004

0.047

1.20MAX

0~8

0.45~0.750.018~0.030

(0.50)

0.020

48-TSOP1-1220AF

+0.07

0.20-0.03

48-PINLEAD/LEADSTICTHINSMALLOUT-LINEPACKAGETYPE(I)

17.000.10

1.00

0.50

1.00

2.50

12.00

1.30

1.00

2.50

0.65Max

2.00

17.000.10

PINCONFIGURATION(ULGA)

K9G8G08U0M-ICB0/IIB0

NC NC NC

NC NC NC

NC /RE NC NC NC NC NC

Vcc

NC Vss IO7 IO5 Vcc

/CE NC R/B NC IO6 IO4

NC

CLE

NC

/WE

IO0

IO2 Vss

NC

Vss NC /WP IO1 IO3 Vss

NC

ALE

NC

NC

NC

NC NC

NC NC NC

NC NC NC

ABCDEFGHJKLMN

7

6

5

4

3

2

1

52-ULGA(measuredinmillimeters)

12.000.10

1.0010.001.00

A

2.00

12.000.10

76543 2 1

B

(DatumA)

1.00

1.00

#A1

ABC

D

(DatumB)

E

F

GH

JKLM

N

12-1.000.05

0.1MCAB

41-0.700.05

17.000.10

0.10C

SideView

BottomView

TopView

PACKAGEDIMENSIONS

0.1MC

AB

17.000.10

1.00

0.50

1.00

2.50

12.00

1.30

1.00

2.50

0.65Max

2.00

17.000.10

K9LAG08U1M-ICB0/IIB0

ABCDEFGHJKLMN

NC

NC NC

NC

NC

NC

NC

/RE1 R/B2 IO7-2IO6-2 IO5-2

NC

Vcc

/RE2 Vss

IO7-1IO5-1 Vcc

/CE1 /CE2 R/B1 /WP2 IO6-1 IO4-1 IO4-2

CLE1

CLE2/WE1

IO0-1IO2-1 Vss

IO3-2

Vss ALE2 /WP1 IO1-1IO3-1 Vss

NC

ALE1

NC NC

/WE2

NC

IO0-2

IO1-2 IO2-2 NC

NC

NC

NC

7

6

5

4

3

2

1

52-ULGA(measuredinmillimeters)

12.000.10

1.0010.001.00

A

2.00

12.000.10

76543 2 1

B

(DatumA)

1.00

1.00

#A1

A

BC

(DatumB)

DEF

GH

JKLM

N

12-1.000.05

0.1MCAB

41-0.700.05

0.1MCAB

17.000.10

0.10C

SideView

BottomView

TopView

PACKAGEDIMENSIONS

PINDESCRIPTION

PinName

PinFunction

I/O0~I/O7

DATAINPUTS/OUTPUTS

TheI/Opinsareusedtoinputcommand,addressanddata,andtooutputdataduringreadoperations.TheI/Opinsfloattohigh-zwhenthechipisdeselectedorwhentheoutputsaredisabled.

CLE

COMMANDLATCHENABLE

TheCLEinputcontrolstheactivatingpathforcommandssenttothecommandregister.Whenactivehigh,commandsarelatchedintothecommandregisterthroughtheI/OportsontherisingedgeoftheWEsignal.

ALE

ADDRESSLATCHENABLE

TheALEinputcontrolstheactivatingpathforaddresstotheinternaladdressregisters.AddressesarelatchedontherisingedgeofWEwithALEhigh.

CE

CHIPENABLE

TheCEinputisthedeviceselectioncontrol.WhenthedeviceisintheBusystate,CEhighisignored,andthedevicedoesnotreturntostandbymodeinprogramoreraseoperation.RegardingCEcontrolduringreadoperation,referto’Pageread’sectionofDeviceoperation.

RE

READENABLE

TheREinputistheserialdata-outcontrol,andwhenactivedrivesthedataontotheI/Obus.DataisvalidtREAafterthefallingedgeofREwhichalsoincrementstheinternalcolumnaddresscounterbyone.

WE

WRITEENABLE

TheWEinputcontrolswritestotheI/Oport.Commands,addressanddataarelatchedontherisingedgeoftheWEpulse.

WP

WRITEPROTECT

TheWPpinprovidesinadvertentwrite/eraseprotectionduringpowertransitions.TheinternalhighvoltagegeneratorisresetwhentheWPpinisactivelow.

R/B

READY/BUSYOUTPUT

TheR/Boutputindicatesthestatusofthedeviceoperation.Whenlow,itindicatesthataprogram,eraseorrandomreadoperationisinprocessandreturnstohighstateuponcompletion.Itisanopendrainoutputanddoesnotfloattohigh-zconditionwhenthechipisdeselectedorwhenoutputsaredisabled.

V OWER

CCisthepowersupplyfordevice.

Vss

GROUND

N.C

NOCONNECTION

Leadisnotinternallyconnected.

NOTE:ConnectallVCCandVSSpinsofeachdevicetocommonpowersupplyoutputs.

DonotleaveVCCorVSSdisconnected.

Figure1-1.K9G8G08U0MFunctionalBlockDiagram

A12-A30

A0-A11

Command

I/OBuffers&Latches

VccVss

CEREWE

GlobalBuffers

I/

CLEALEWP

ControlLogic&HighVoltageGenerator

CommandRegister

Y-BuffersLatches

&Decoders

X-BuffersLatches

&Decoders

OutputDriver

8,192M+256MBit

NANDFlashARRAY

(2,048+64)Bytex524,288

DataRegister&S/A

Y-Gating

VccVss

I/00

07

Figure2-1.K9G8G08U0MArrayOrganization

(

512KPages(=4,096Blocks)

8bit

2KBytes

64Bytes

PageRegister

2KBytes

I/O0~I/O7

64Bytes

1Block=128Pages256K+8k)Byte

1Page=(2K+64)Bytes

1Block=(2K+64)Bx128Pages

=(256K+8K)Bytes

1Device=(2K+64)Bx128Pagesx4,096Blocks

=8,448Mbits

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

1stCycle

A0

A1

A2

A3

A4

A5

A6

A7

2ndCycle

A8

A9

A10

A11

*L

*L

*L

*L

3rdCycle

A12

A13

A14

A15

A16

A17

A18

A19

4thCycle

A20

A21

A22

A23

A24

A25

A26

A27

5thCycle

A28

A29

A30

*L

*L

*L

*L

*L

NOTE:ColumnAddress:StartingAddressoftheRegister.

Lmustbesetto"Low".

Thedeviceignoresanyadditionalinputofaddresscycleshanrequired.

ColumnAddressColumnAddressRowAddressRowAddressRowAddress

ProductIntroduction

TheK9G8G08U0Misa8,448Mbit(8,858,370,048bit)memoryorganizedas524,288rows(pages)by2,112x8columns.Spare64col-umnsarelocatedfromcolumnaddressof2,048~2,111.A2,112-bytedataregisterisconnectedtomemorycellarraysfor mo-datingdatatransferbetweentheI/Obuffersandmemorycellsduringpagereadandpageprogramoperations.Thememoryarrayismadeupof32cellsthatareseriallyconnectedtoformaNANDstructure.Eachofthe32cellsresidesinadifferentpage.AblockconsistsoftwoNANDstructuredstrings.ANANDstructureconsistsof32cells.Acellhas2-bitdata.Total1,081,344NANDcellsresideinablock.Theprogramandreadoperationsareexecutedonapagebasis,whiletheeraseoperationiecutedonablockbasis.Thememoryarrayconsistsof4,096separayerasable256K-byteblocks.Itindicatesthatthebitbybiseoperationispro-hibitedontheK9G8G08U0M.

TheK9G8G08U0Mhasaddressesmultiplexedinto8I/Os.Thisschemedramaticallyreducespincountsandallowssystemupgradestofuturedensitiesbymaintainingconsistencyinsystemboarddesign.Command,addressanddataareallwrittenthroughI/O'sbybringingWEtolowwhileCEislow.ThosearelatchedontherisingedgeofWE.CommandLatchEnable(CLE)andAddressLatchEnable(ALE)areusedtomultiplexcommandandaddressrespectively,viatheI/Opins.Somecommandsrequireonebuscycle.Forexample,ResetCommand,StatusReadCommand,etcrequirejustonecyclebus.Someothercommands,likepagereadandblockeraseandpageprogram,requiretwocycles:onecycleforsetupandtheothercycleforexecution.The1G-bytephysicalspacerequires30addresses,therebyrequiringfivecyclesforaddressing:2cyclesofcolumnaddress,3cyclesofrowaddress,inthatorder.PageReadandPageProgramneedthesamefiveaddresscyclesfollowingtherequiredcommandinput.InBlockEraseoper-ation,however,onlythreerowaddresscyclesareused.Deviceoperationsareselectedbywritingspecificcommandsintothecom-mandregister.Table1definesthespecificcommandsoftheK9G8G08U0M.

Table1.CommandSets

Function

1stCycle

2ndCycle

AcceptableCommandduringBusy

Read

00h

30h

ReadID

90h

-

Reset

FFh

-

O

PageProgram

80h

10h

Two-

nePageProgram(2)

80h 11h

81h 10h

BlockErase

60h

D0h

Two-neBlockErase

60h 60h

D0h

RandomDataInput(1)

85h

-

RandomDataOutput(1)

05h

E0h

ReadStatus

70h

O

NOTE:1.RandomDataInput/Outputcanbeexecutedinapage.

Anycommandbetween11hand81hisprohibitedexcept70handFFh.

Caution:AnyundefinedcommandinputsareprohibitedexceptforabovecommandsetofTable1.

ABSOLUTE UMRATINGS

Parameter

Symbol

Rating

Unit

VoltageonanypinrelativetoVSS

Vcc

-0.6to+4.6

V

Vin

-0.6to+4.6

Vi/o

-0.6toVcc+0.3(<4.6V)

TemperatureUnderBias

K9XXG08UXM-XCB0

Tbias

-10to+125

C

K9XXG08UXM-XIB0

-40to+125

StorageTemperature

K9XXG08UXM-XCB0

Tstg

-65to+150

C

K9XXG08UXM-XIB0

ShortCircuitCurrent

Ios

5

mA

NOTE:

MinimumDCvoltageis-0.6Voninput/outputpins.Duringtransitions,thislevelmayundershootto-2.0Vforperiods<30ns.

umDCvoltageoninput/outputpinsisVCC+0.3Vwhich,duringtransitions,mayovershoottoVCC+2.0Vforperiods<20ns.

PermanentdevicedamagemayoccurifABSOLUTEUMRATINGSareexceeded.Functionaloperationshouldberestrictedtotheconditionsasdetailedintheoperationalsectionsofthisdatasheet.Exposuretoabsolute umratingconditionsforextendedperiodsmayaffectreliability.

MENDEDOPERATINGCONDITIONS

(VoltagereferencetoGND,K9XXG08UXM-XCB0:TA=0to70C,K9XXG08UXM-XIB0:TA=-40to85C)

Parameter

Symbol

K9XXG08UXM

Unit

Min

Typ.

Max

SupplyVoltage

Vcc

2.7

3.3

3.6

V

SupplyVoltage

Vss

0

0

0

V

DCANDOPERATINGCHARACTERISTICS( mendedoperatingconditionsotherwisenoted.)

Parameter

Symbol

TestConditions

Min

Typ

Max

Unit

OperatingCurrent

PageReadwithSerialAccess

Icc1

tRC=30ns,CE=VIL,IOUT=0mA

-

15

30

mA

Program

Icc2

-

-

15

30

Erase

Icc3

-

-

15

30

Stand-byCurrent(TTL)

Isb1

CE=VIH,WP=0V/VCC

-

-

1

Stand-byCurrent(CMOS)

Isb2

CE=VCC-0.2,WP=0V/VCC

-

10

50

A

InputLeakageCurrent

Ili

VIN=0toVcc(max)

-

-

10

OutputLeakageCurrent

Ilo

VOUT=0toVcc(max)

-

-

10

InputHighVoltage

VIH(1)

-

0.8xVcc

-

VCC+0.3

V

InputLowVoltage,Allinputs

VL(1)

-

-0.3

-

0.2xVcc

OutputHighVoltageLevel

Voh

IOH=-400A

2.4

-

-

OutputLowVoltageLevel

Vol

IOL=2.1mA

-

-

0.4

OutputLowCurrent(R/B)

IOL(R/B)

VOL=0.4V

8

10

-

mA

NOTE:

VILcanundershootto-0.4VandVIHcanovershoottoVCC+0.4Vfordurationsof20nsorless.

TypicalvaluearemeasuredatVcc=3.3V,TA=25C.Not100%tested.

ThetypicalvalueoftheK9LAG08U1M’sISB2is20Aandthe umvalueis100A.

VALIDBLOCK

Parameter

Symbol

Min

Typ.

Max

Unit

K9G8G08U0M

Nvb

3,996

-

4,096

Blocks

K9LAG08U1M

Nvb

7,992

8,192

Blocks

NOTE:

Thedevicemayincludeinitialinvalidblockswhenfirstshipped.Additionalinvalidblocksmaydevelopwhilebeingused.Thenumberofvalidblocksispresentedwithbothcasesofinvalidblocksconsidered.Invalidblocksaredefinedasblocksthatcontainoneormorebadbits.Donoseorpro-gramfactory-markedbadblocks.Refertotheattachedtechnicalnotesforappropriatemanagementofinitialinvalidblocks.

The1stblock,whichiscedon00hblockaddress,isguaranteedtobeavalidblockatthetimeofshipment.

Thenumberofvalidblockisonthebasisofsingleneoperations,andthismaybedecreasedwithtwoneoperations.

*:EachK9G8G08U0MchipintheK9LAG08U1Mhas un100invalidblocks.

ACTESTCONDITION

(K9XXG08UXM-XCB0:TA=0to70C,K9XXG08UXM-XIB0:TA=-40to85C)

Parameter

K9XXG08UXM

InputPulseLevels

0VtoVcc

InputRiseandFallTimes

5ns

InputandOutputTimingLevels

Vcc/2

OutputLoad

1TTLGATEandCL=50pF

CAPACITANCE(TA=25C,VCC=3.3V,f=1.0MHz)

Item

Symbol

TestCondition

Min

Max

Unit

Input/OutputCapacitance

Ci/o

VIL=0V

-

10

pF

InputCapacitance

Cin

VN=0V

-

10

pF

NOTE:Capacitanceisperiodicallysampledandnot100%tested.

MODESELECTION

CLE

ALE

CE

WE

RE

WP

Mode

H

L

L

H

X

ReadMode

CommandInput

L

H

L

H

X

AddressInput(5clock)

H

L

L

H

H

WriteMode

CommandInput

L

H

L

H

H

AddressInput(5clock)

L

L

L

H

H

DataInput

L

L

L

H

X

DataOutput

X

X

X

X

H

X

DuringRead(Busy)

X

X

X

X

X

H

DuringProgram(Busy)

X

X

X

X

X

H

DuringErase(Busy)

X

X(1)

X

X

X

L

WriteProtect

X

X

H

X

X

0V/Vcc(2)

Stand-by

NOTE:1.XcanbeVILorVIH.

2.WPshouldbebiasedtoCMOShighorCMOSlowforstandby.

Program/EraseCharacteristics

Parameter

Symbol

Min

Typ

Max

Unit

ProgramTime

tPROG

-

0.8

3

ms

DummyBusyTimeforMultineProgram

tDBSY

0.5

1

s

NumberofPartialProgramCyclesintheSamePage

Nop

-

-

1

cycle

BlockEraseTime

tBERS

-

1.5

10

ms

NOTE:Typicalprogramtimeisdefinedasthetimewithinwhi orethan50%ofthewholepagesareprogrammedat3.3VVccand25Ctemperature.

ACTimingCharacteristicsforCommand/Address/DataInput

Parameter

Symbol

Min

Max

Unit

CLESetupTime

tCLS(1)

15

-

ns

CLEHoldTime

tCLH

5

-

ns

CESetupTime

tCS(1)

20

-

ns

CEHoldTime

tCH

5

-

ns

WEPulseWidth

tWP

15

-

ns

ALESetupTime

tALS(1)

15

-

ns

ALEHoldTime

tALH

5

-

ns

DataSetupTime

tDS(1)

15

-

ns

DataHoldTime

tDH

5

-

ns

WriteCycleTime

tWC

30

-

ns

WEHighHoldTime

tWH

10

-

ns

AddresstoDataLoadingTime

tADL(2)

70(2)

ns

NOTES:1.ThetransiionofhecorrespondingcontrolpinsmustoccuronlyoncewhileWEisheldlow.

2.tADListhetimefromtheWErisingedgeoffinaladdresscycletotheWErisingedgeoffirstdycle.

ACCharacteristicsforOperation

Parameter

Symbol

Min

Max

Unit

DataTransferfromCelltoRegister

tR

-

60

s

ALEtoREDelay

tAR

10

-

ns

CLEtoREDelay

tCLR

10

-

ns

ReadytoRELow

tRR

20

-

ns

REPulseWidth

tRP

15

-

ns

WEHightoBusy

tWB

-

100

ns

ReadCycleTime

tRC

30

-

ns

REAccessTime

tREA

-

20

ns

CEAccessTime

tCEA

-

25

ns

REHightoOutputHi-Z

tRHZ

-

100

ns

CEHightoOutputHi-Z

tCHZ

-

30

ns

CEHightoALEorCLEDon’tCare

tCSD

10

-

ns

REHightoOutputHold

tRHOH

15

-

ns

RELowtoOutputHold

tRLOH

5

-

ns

CEHightoOutputHold

tCOH

15

-

ns

REHighHoldTime

tREH

10

-

ns

OutputHi-ZtoRELow

tR

0

-

ns

REHightoWELow

tRHW

100

-

ns

WEHightoRELow

tWHR

60

-

ns

DeviceResettingTime(Read/Program/Erase)

tRST

-

5/10/500(1)

s

NOTE:1.Ifresetcommand(FFh)iswrittenatReadystate,thedevicegoesintoBusyfor um5s.

NANDFlashTechnicalNotes

InitialInvalidBlock(s)

InitialinvalidblocksaredefinedasblocksthatcontainoneormoreinitialinvalidbitswhosereliabilityisnotguaranteedbySamsung.Theinformationregardingtheinitialinvalidblock(s)iscalledtheinitialinvalidblockinformation.Deviceswithinitialinvalidblock(s)havethesamequalitylevelasdeviceswithallvalidblocksandhavethesameACandDCcharacteristics.Aninitialinvalidblock(s)doesnotaffecttheperformanceofvalidblock(s)becauseitisisolatedfromthebitlineandthecommonsourcelinebyaselecttran-sistor.Thesystemdesignmustbeabletomaskouttheinitialinvalidblock(s)viaaddressmap.The1stblock,whichiscedon00hblockaddress,isguaranteedtobeavalidblockatthetimeofshipment.

IdentifyingInitialInvalidBlock(s)

Alldevicelocationsareerased(FFh)exceptlocationswheretheinitialinvalidblock(s)informationiswrittenpriortoship.Theinitialinvalidblock(s)statusisdefinedbythe1stbyteinthesparearea.Samsungmakessurethatthelastpageofeveryinitialinvalidblockhasnon-FFhdataatthecolumnaddressof2,048.Theinitialinvalidblockinformationisalsoerasableinmostcases,anditisimpossibletorecovertheinformationonceithasbeenerased.Therefore,thesystemmustbeabletorecognizetheinitialinvalidblock(s)basedontheinitialinvalidblockinformationandcreatetheinitialinvalidblocktableviathefollowingsuggestedflowchart(Figure3).Anyintentionalerasureoftheinitialinvalidblockinformationisprohibited.

IncrementBlockAddress

Check"FFh"atthecolumnaddress2048ofthelastpageintheblock

Create(orupdate)Initial

InvalidBlock(s)Table

*

No

Check"FFh"?

Yes

No LastBlock?

Yes

End

Start

SetBlockAddress=0

Figure3.Flowcharttocreateinitialinvalidblocktable.

NANDFlashTechnicalNotes()

Errorinwriteorreadoperation

Withinitslifetime,additionalinvalidblocksmaydevelopwithNANDFlashmemory.Refertothequalificationreportfortheactualdata.Blockrecementshouldbedoneuponeraseorprogramerror.

FailureMode

DetectionandCountermeasuresequence

Write

EraseFailure

StatusReadafterErase-->BlockRecement

ProgramFailure

StatusReadafterProgram-->BlockRecement

Read

UptoFourBitFailure

VerifyECC->ECCCorrection

ECC :ErrorCorrectingCode-->RSCodeetc.

Example)4bitcorrection/512-byte

Start

ProgramFlowChart

Write80h

WriteAddress

WriteData

Write10h

I/O6=1?

orR/B=1?

No

*

ProgramError

Yes

No

I/O0=0?

Yes

ProgramCompleted

ReadStatusRegister

*

:Ifprogramoperationresultsinanerror,mapouttheblockincludingthepageinerrorandcopythetargetdatatoanotherblock.

NANDFlashTechnicalNotes()

EraseFlowChart

I/O6=1?

orR/B=1?

No

*

EraseError

Yes

No

I/O0=0?

Yes

EraseCompleted

ReadStatusRegister

WriteD0h

WriteBlockAddress

Start

Write60h

Start

ReadFlowChart

Write00h

WriteAddress

Write30h

ReadData

ECCGeneration

*

No

ReclaimtheError

VerifyECC

Yes

PageReadCompleted

:Iferaseoperationresultsinanerror,mapout

thefailingblockandreceitwithanotherblock.

BlockRecement

BlockA

1st

(n-1)thnth

(page)

1st

(n-1)thnth

(page)

BlockB

1

anerroroccurs.

Buffermemoryofthecontroller.

2

Step1

WhenanerrorhappensinthenthpageoftheBlock’A’duringeraseorprogramoperation.

Step2

Copythedatainthe1st~(n-1)thpagetothesamelocationofanotherblock.(Block’B’)

Step3

Then,copythenthpagedataoftheBlock’A’inthebuffermemorytothenthpageoftheBlock’B’.

Step4

DonoseorprogramtoBlock’A’bycreatingan’invalidblock’tableorotherappropriatescheme.

NANDFlashTechnicalNotes()

Addressingforprogramoperation

Withinablock,thepagesmustbeprogrammedconsecutivelyfromtheLSB(leastsignificantbit)pageoftheblocktoMSB(mostsig-nificantbit)pagesoftheblock.Randompageaddressprogrammingisprohibited.Inthiscase,thedefinitionofLSBpageistheLSBamongthepagestobeprogrammed.Therefore,LSBdoesn'tneedtobepage0.

(128)

:

(32)

:

(3)

(2)

(1)

Page127

Page31

Page2

Page1

Page0

Dataregister

FromtheLSBpagetoMSBpageDATAIN:Data(1) Data(128)

Page127

(128)

:

(1)

:

(3)

(32)

(2)

Dataregister

Page31

Page2

Page1

Page0

Ex.)Randompageprogram(Prohibition)DATAIN:Data(1) Data(128)

SystemInterfaceUsingCEdon’t-care.

Foraneasiersysteminterface,CEmaybeinactiveduringthedata-loadingorserialaccessasshownbelow.Theinternal2,112bytedataregistersareutilizedasseparatebuffersforthisoperationandthesystemdesigngetsmoreflexible.Inaddition,forvoiceoraudioapplicationswhichuseslowcycletimeontheorderof-seconds,de-activatingCEduringthedata-loadingandserialaccesswouldprovidesignificantsavingsinpowerconsumption.

Figure4.ProgramOperationwithCEdon’t-care.

CEdon’t-care

CE

WEALE

I/Ox

80h

Address(5Cycles)

DataInput

DataInput

10h

tCS

tCH

tCEA

CE

CE

tREA

tWP

RE

WE

I/O0~7

out

Figure5.ReadOperationwithCEdon’t-care.

CLE

CEdon’t-care

CE

RE

CLE

tR

ALE

R/B

WE

00h

Address(5Cycle)

30h

DataOutput(serialaccess)

I/Ox

NOTE

Device

I/O

DATA

ADDRESS

I/Ox

DataIn/Out

Col.Add1

Col.Add2

RowAdd1

RowAdd2

RowAdd3

K9G8G08U0M

I/O0~I/O7

~2,112byte

A0~A7

A8~A11

A12~A19

A20~A27

A28~A30

CommandLatchCycle

tCLS

tCLH

tCS

tCH

tWP

tALS

tALH

tDS

tDH

Command

CLE

CE

WE

ALE

I/Ox

AddressLatchCycle

tCS

tWC

tWC

tWC

tWC

tWP

tWP

tWP

tWP

tALS

tWHtALH

tWH

tALS

tALH

tALS

tWHtALH

tALS

tWHtALH

tALS

tALH

tDS

tDH

tDS

tDH

tDStDH

tDS

tDH

tDS

tDH

Col.Add1

Col.Add2

RowAdd1

RowAdd2

RowAdd3

CLE

CE

WE

ALE

I/Ox

InputDataLatchCycle

tCLH

tCH

tALS

tWC

tWP

tWP

tDS

tWHtDH

tDS

tDH

tDS

tDH

DIN0

DIN1

DINfinal

tWP

CLE

CE

ALE

WE

I/Ox

*SerialAccessCycleafterRead(CLE=L,WE=H,ALE=L)

CE

RE

I/Ox

R/B

tRC

tREH

tREA

tREA

tREA

tCHZ

tCOH

tRHZ

Dout

Dout

tRHZtRHOH

Dout

tRR

NOTES:Transitionismeasuredat200mVfromsteadystatevoltagewithload.

Thisparameterissampledandnot100%tested.tRLOHisvalidwhenfrequencyishigherthan20MHz.

tRHOHstartstobevalidwhenfrequencyislowerthan20MHz.

tRC

tRP

tREH

tCHZtCOH

tREA

tCEA

tREAtRLOH

tRHZ

tRHOH

Dout Dout

tRR

SerialAccessCycleafterRead(EDOType,CLE=L,WE=H,ALE=L)

CE

RE

I/Ox

R/B

NOTES:Transitionismeasuredat200mVfromsteadystatevoltagewithload.

Thisparameterissampledandnot100%tested.tRLOHisvalidwhenfrequencyishigherthan20MHz.

tRHOHstartstobevalidwhenfrequencyislowerthan20MHz.

StatusReadCycle

tCLR

tCLS

tCLH

tCS

tCH

tWP

tCEA

tWHR

tCHZ

tCOH

tDS

tDH

tIR

tREA

70h

tRHZtRHOH

StatusOutput

CLE

CE

WE

RE

I/Ox

ReadOperation

tWC

tWB

tCSD

tAR

tR

tRC

tRHZ

tRR

00h Col.Add1Col.Add2RowAdd1RowAdd2RowAdd3 30h

DoutN DoutN+1

DoutM

ColumnAddress RowAddress

Busy

tCLR

CLE

CE

WE

ALE

RE

I/Ox

R/B

ReadOperation(InterceptedbyCE)

tCLR

tCSD

tCHZ

tWB

tCOH

tAR

tR

tRC

tRR

00h Col.Add1Col.Add2RowAdd1RowAdd2RowAdd3 30h

DoutN DoutN+1 DoutN+2

ColumnAddress RowAddress

Busy

CLE

CE

WE

ALE

RE

I/Ox

R/B

Advance

FLASHMEMORY

K9LAG08U1MK9G8G08U0M

RandomDataOutputInaPage

tCLR

tWHR

tAR

tRHW

tR

tRC

tREA

tRR

00h Col.Add1Col.Add2RowAdd1RowAdd2RowAdd3 30h

DoutN DoutN+1

05h

DoutMDoutM+1

ColumnAddress RowAddress

ColAdd1ColAdd2 E0h

ColumnAddress

Busy

CLE

CE

WE

22

ALE

RE

I/Ox

R/B

K9LAG08U1MK9G8G08U0M

Advance

FLASHMEMORY

PageProgramOperation

CLE

CE

WE

ALE

RE

I/Ox

R/B

tWC

tWC

tWC

tADL

tWB tPROG

tWHR

80h

Co.lAdd1Col.Add2RowAdd1RowAdd2RowAdd3

DinN

DinM

10h

SerialData

In

1uptomByte Program

putCommand

ColumnAddress

RowAddress

SerialInput

Command

70h I/O0

ReadStatusCommand

I/O0=0SuccessfulProgramI/O0=1ErrorinProgram

23

CLE

PageProgramOperationwithRandomDataInput

Advance

FLASHMEMORY

K9LAG08U1MK9G8G08U0M

tWC

tWC

tWC

tADL

tADL

tWB tPROG

tWHR

80h

Col.Add1Col.Add2RowAdd1RowAdd2RowAdd3 Din

N

DinM

85h

Col.Add1Col.Add2 DinJ

DinK

10h

SerialData

I

nputCommand

ColumnAddress

RowAddress

SerialInput RandomDataColumnAddress

InputCommand

SerialInput

Program

d

Comman

70h I/O0

ReadStatusCommand

CE

WE

24

ALE

RE

I/Ox

R/B

K9LAG08U1MK9G8G08U0M

Advance

FLASHMEMORY

BlockEraseOperation

tWC

tWB

tBERS

60h RowAdd1RowAdd2RowAdd3D0h

70h

I/O0

RowAddress

Busy

tWHR

CLE

CE

WE

ALE

RE

I/Ox

R/B

AutoBlockEraseSetupCommand

EraseCommand

ReadStatusCommand

I/O0=0SuccessfulEraseI/O0=1ErrorinErase

25

TnweoP-ageProgramOperation

tWC

tDBSY

tWB

tWBtPROG

tWHR

80h

A0~A7A8~A11A12~A19A20~A27A28~A30

Din

Din

N

M

11h

81h

A0~A7A8~A11A12~A19A20~A27A28~A30