VHDL與數(shù)字集成電路設(shè)計VHDL7-1_第1頁
VHDL與數(shù)字集成電路設(shè)計VHDL7-1_第2頁
VHDL與數(shù)字集成電路設(shè)計VHDL7-1_第3頁
VHDL與數(shù)字集成電路設(shè)計VHDL7-1_第4頁
VHDL與數(shù)字集成電路設(shè)計VHDL7-1_第5頁
已閱讀5頁，還剩34頁未讀， 繼續(xù)免費(fèi)閱讀

下載本文檔

版權(quán)說明：本文檔由用戶提供并上傳，收益歸屬內(nèi)容提供方，若內(nèi)容存在侵權(quán)，請進(jìn)行舉報或認(rèn)領(lǐng)

文檔簡介

第七章：時間考慮2SynchronousTiming3LatchParametersDClkQDQClktc-qtholdPWmtsutd-qDelayscanbedifferentforrisingandfallingdatatransitionsT4RegisterParametersDClkQDQClktc-qtholdTtsuDelayscanbedifferentforrisingandfallingdatatransitions5ClockUncertaintiesSourcesofclockuncertainty6ClockNonidealitiesClockskewSpatialvariationintemporallyequivalentclockedges;deterministic+random,tSKClockjitterTemporalvariationsinconsecutiveedgesoftheclocksignal;modulation+randomnoiseCycle-to-cycle(short-term)tJSLongtermtJLVariationofthepulsewidthImportantforlevelsensitiveclocking7ClockSkewandJitterBothskewandjitteraffecttheeffectivecycletimeOnlyskewaffectstheracemarginClkClktSKtJS8PositiveandNegativeSkew9PositiveSkewLaunchingedgearrivesbeforethereceivingedge10NegativeSkewReceivingedgearrivesbeforethelaunchingedge11TimingConstraintsMinimumcycletime:T-=tc-q+tsu+tlogicWorstcaseiswhenreceivingedgearrivesearly(positive)12TimingConstraintsHoldtimeconstraint:t(c-q,cd)+t(logic,cd)>thold+Worstcaseiswhenreceivingedgearriveslate

Racebetweendataandclock13ImpactofJitter14LongestLogicPathin

Edge-TriggeredSystemsClkTTSUTClk-QTLMLatestpoint

oflaunchingEarliestarrival

ofnextcycleTJI+d15ClockConstraintsin

Edge-TriggeredSystemsIflaunchingedgeislateandreceivingedgeisearly,thedatawillnotbetoolateif:MinimumcycletimeisdeterminedbythemaximumdelaysthroughthelogicTc-q+TLM+TSU<T–TJI,1–TJI,2-dTc-q+TLM+TSU+d+2TJI<TSkewcanbeeitherpositiveornegative16ShortestPathClkTClk-QTLmEarliestpoint

oflaunchingDatamustnotarrive

beforethistimeClkTHNominal

clockedge17ClockConstraints

inEdge-TriggeredSystemsMinimumlogicdelayIflaunchingedgeisearlyandreceivingedgeislate:Tc-q+TLM–TJI,1<TH+TJI,2+dTc-q+TLM<TH+2TJI+d18ClockDistributionClockisdistributedinatree-likefashionH-tree19MorerealisticH-tree[Restle98]20TheGridSystemNorc-matchingLargepower2121164Clocking2phasesinglewireclock,distributedglobally2distributeddriverchannelsReducedRCdelay/skewImprovedthermaldistribution3.75nFclockload58cmfinaldriverwidthLocalinvertersforlatchingConditionalclocksincachestoreducepowerMorecomplexracecheckingDevicevariationtrise=0.35nstskew=150pstcycle=3.3nsClockwaveformLocationofclockdriverondiepre-driverfinaldrivers2223ClockSkewinAlphaProcessor242Phase,withmultipleconditionalbufferedclocks2.8nFclockload40cmfinaldriverwidthLocalclockscanbegated“off”tosavepowerReducedload/skewReducedthermalissuesMultipleclockscomplicateracecheckingtrise=0.35nstskew=50pstcycle=1.67nsEV6(Alpha21264)Clocking600MHz–0.35micronCMOSGlobalclockwaveform25SynchronousPipelinedDatapath26Self-TimedPipelinedDatapath27Hand-ShakingProtocolTwoPhaseHandshake28EventLogic–TheMuller-CElement292-PhaseHandshakeProtocol30Example:Self-timedFIFO31PLL-BasedSynchronization32PLLBlockDiagram33PhaseDetectorOutputbeforefilteringTransfer

characteristic34Phase-FrequencyDetector35PFDRes

溫馨提示

  • 1. 本站所有資源如無特殊說明，都需要本地電腦安裝OFFICE2007和PDF閱讀器。圖紙軟件為CAD,CAXA,PROE,UG,SolidWorks等.壓縮文件請下載最新的WinRAR軟件解壓。
  • 2. 本站的文檔不包含任何第三方提供的附件圖紙等，如果需要附件，請聯(lián)系上傳者。文件的所有權(quán)益歸上傳用戶所有。
  • 3. 本站RAR壓縮包中若帶圖紙，網(wǎng)頁內(nèi)容里面會有圖紙預(yù)覽，若沒有圖紙預(yù)覽就沒有圖紙。
  • 4. 未經(jīng)權(quán)益所有人同意不得將文件中的內(nèi)容挪作商業(yè)或盈利用途。
  • 5. 人人文庫網(wǎng)僅提供信息存儲空間，僅對用戶上傳內(nèi)容的表現(xiàn)方式做保護(hù)處理，對用戶上傳分享的文檔內(nèi)容本身不做任何修改或編輯，并不能對任何下載內(nèi)容負(fù)責(zé)。
  • 6. 下載文件中如有侵權(quán)或不適當(dāng)內(nèi)容，請與我們聯(lián)系，我們立即糾正。
  • 7. 本站不保證下載資源的準(zhǔn)確性、安全性和完整性, 同時也不承擔(dān)用戶因使用這些下載資源對自己和他人造成任何形式的傷害或損失。

評論

0/150

提交評論