ARM培訓(xùn)講義提綱

ARM 位：西安電子科技大 寫(xiě)：何方 編寫(xiě)日期：2005年7月1 ARM3大熱點(diǎn)是：第三、四代移動(dòng)通信技術(shù)、數(shù)字電視嵌入式操作系統(tǒng)與常見(jiàn)的單片機(jī)、DSPDSP處理器：速度、IO設(shè)計(jì)指標(biāo)、處理器的軟件支持、處理器調(diào)試方式、處理器提供商的ARM芯片作為該系統(tǒng)的核心芯片。ARMAdvancedRISCMachines的縮寫(xiě)，ARM1990ARM以低成本、市場(chǎng)。ARMIP供應(yīng)商，只做設(shè)計(jì)。ARM處理器系列有：ARM7系列、ARM9系列、ARM9E系列、ARM10系列、SecurCoreSC100、StrongARM、XScaleARM7系列、ARM9系列：1）ARM7系列：0.9MIPS/MHz3級(jí)流水、馮.ARM7TDMI和ARM720T；T16THUMB指令，D支持在片調(diào)試，M增強(qiáng)型乘法器，產(chǎn)生全64位結(jié)果，I:ICE2）ARM9系列：1.1MIPS/MHz5ARM920T、基于ARMLOGIC等。注意：ARM9ARM7ARM920TARM920TARM920TCP15協(xié)處理器內(nèi)存管理單元ARM芯片的匯編語(yǔ)言。ARMARMV4V5V4，THUMBARM狀態(tài)指令長(zhǎng)度：32位、16操作模式：7種寄存器：316個(gè)狀態(tài)寄存器ARMARMARMARMARM4－1所示

4－1：ARM1ARM執(zhí)行ARM4－24－3ARM指令集：4－2：4－2：ARM

4－3：ARMARMCPSR條件碼和指令條件域的狀態(tài)被有條件地執(zhí)行。該域（31:28）C、N、ZV標(biāo)志的狀態(tài)滿足該域的16個(gè)可能條件，每種由復(fù)加在指令記憶符后的一個(gè)雙字符后綴表示。例如，Branch（B為匯編語(yǔ)言）BEQ表示“BranchifEqual”Z標(biāo)志被置位時(shí)執(zhí)行ALCPSR4－4給出了條件碼概況：4－4：ARMARM4－4。RnPC來(lái)執(zhí)行一個(gè)分支。這個(gè)令時(shí)，Rn[0]ARMTHUMB指令對(duì)指令流進(jìn)行解碼。指令格4－1所示：4－1：BX★★BX- ；{cond}為雙字母條件記憶符（即條件碼），見(jiàn)表4－4，而Rn★使用R15R15作操作數(shù)，該情況未定義。 R0,Into_THUMB+1 R5, ; ;匯編作為ARM★★2分支與帶鏈接分支（B、4－44－24－2：B、BL字節(jié)的分支。該指令偏置必須考慮預(yù)取操作，它會(huì)引起程序計(jì)數(shù)器PC超前當(dāng)前指令2（8個(gè)字節(jié)）★存器以被Rn存作堆棧指針，使用LDMRn!,{..PC}?！铩顱{L}{cond}<expression> 常用請(qǐng)求帶鏈接分支的指令形式。如果缺省，R14舊的PC值存入R14 如表4－4中所示的雙字母助記符（條件碼），如果缺省，默認(rèn)為<expression>目標(biāo)單元，匯編程序計(jì)算偏移量。 Bthere CMP ;R1＝0 ; ;ADDS R1＝R1＋1,設(shè)置CPSRBLCC ;C＝0,★★3數(shù)據(jù)處理指令僅在條件為真時(shí)被執(zhí)行，參見(jiàn)表4－4。該指令編碼如下圖4－34－3（Rn（ImmOP2OP2OP2（OP1+OP2）★CPSR數(shù)據(jù)處理運(yùn)算可分為邏輯運(yùn)算和算術(shù)運(yùn)算，邏輯運(yùn)算（ND、EOR、TST、Q、ORR、OV、BIC、N）對(duì)操作數(shù)的所有相應(yīng)位或產(chǎn)生結(jié)果的操作數(shù)執(zhí)行邏輯運(yùn)算。如果S位被置位（并且Rd不是R15，見(jiàn)下表），則CPSR中的V標(biāo)志不受影響，C標(biāo)志將被置位來(lái)執(zhí)行barrelshifer（或當(dāng)移位操作為L(zhǎng)SL#0時(shí)保護(hù)），Z被置為結(jié)果bit31的邏輯值。4－5R15ALUbit31被置位，Z標(biāo)志當(dāng)且僅當(dāng)結(jié)果全零時(shí)被置位，Nbit31（如果認(rèn)為操作數(shù)為兩個(gè)獨(dú)立的有符號(hào)數(shù)時(shí)指示結(jié)果為負(fù)）★4-4ARM★50~31（LSL）Rm的內(nèi)容并將每一位移動(dòng)指定量到更有意義的位置。結(jié)果的最不重要位以零shifterCPSRS位。例如，LSL#54－5所示。

4－5置。LSR#54－6所示。4－6所以匯編程序?qū)SR#0（以及ASR#0和ROR#0）轉(zhuǎn)換成LSL#0，并允許指定LSR#32。算術(shù)右移（ASR）Rmbit312個(gè)獨(dú)立符號(hào)狀態(tài)中的符號(hào)，例如，ASR#54－74－7Rmbit312Rmbit31Rmbit3110邏輯右移中常用零來(lái)填充高位。例如，ROR#54－8所示。4－8期望給ROR#0的移位域形式用于對(duì)barrelshifter這個(gè)循環(huán)右移是它使用附加的CPSR的C標(biāo)志來(lái)提供一個(gè)要被移位的33位的數(shù)量到Rm內(nèi)容4－9★如果該字節(jié)為零，Rm未改變的內(nèi)容將被當(dāng)作第二操作數(shù)，并且舊的CPSR的C標(biāo)志值LSL32結(jié)果為零，進(jìn)位輸出等于Rm的0LSL大于32LSR32結(jié)果為零，進(jìn)位輸出等于Rm的31LSR大于32ROR32結(jié)果等于Rm，進(jìn)位等于Rm的31RORn結(jié)果和進(jìn)位與RORn-32相同，這里n大于32；因此不斷從n中減去32，直到nbit71★★寫(xiě)入當(dāng)Rd為R15且S標(biāo)志置位時(shí)，操作結(jié)果被放入R15，對(duì)應(yīng)于當(dāng)前模式的SPSR被移入★用R15如果R15（PC）為前8個(gè)字節(jié)。如果用寄存器指定移位量，則PC為前12在ARM920T中TEQP的功能是：如果處理器工作在特許模式就將SPSR_<mode>移入CPSR指令周期：數(shù)據(jù)處理指令增加的周期數(shù)如下表4-4-6注：S、NI分別定義為順序（S-周期、非順序（N-周期）和內(nèi)部（I-周期。 <opcode>{cond}{S} CMP,CMN,TEQ,TST無(wú)結(jié)果指令<opcode>{cond} <opcode>{cond}{S} Rm{,<shift>}或 雙字母條件助記符，見(jiàn)表 如果S表示(指CMP,CMN,TEQ,TST)，置位條件碼Rd,Rn和 寄存器號(hào)表達(dá) 如果使用，匯編程序?qū)?huì)產(chǎn)生一個(gè)移位的立即8 <Shiftname><register><shiftname>#expression,RRX帶 ASL,LSL,LSR,ASR,ROR.(ASL與LSL一樣 ;如果Z標(biāo)志置位，使 R4,R5,R7,LSR;通過(guò)R2底部字節(jié)數(shù)邏輯右移R7，從R5;將答案放入;;從中斷返回，并從SPSR方式保存□□4PSR轉(zhuǎn)移（MRS、□

4－10：MRS、MSRARM920T□.PSR□.PSR狀態(tài)時(shí)，程序不應(yīng)當(dāng)依賴保留位的特定值，因?yàn)閷?lái)的處理器可能會(huì)將它們10。 ;復(fù)制BICR0,R0,#0x1F ;回寫(xiě)修改后的PSR中的條件方式碼時(shí)，可直接將值寫(xiě)入標(biāo)志位而不必影響控N、Z、CV標(biāo)志置位： ;PSR8□PSR1SS定義為順序（S-周期。–MRS{cond}–MSR{cond}<psr>,Rm–MSR{cond}□.MSR–只將立即數(shù)轉(zhuǎn)移到PSRMSR{cond}□ RdandRm CPSR,CPSR_all,SPSR或SPSR_all.(CPSR和CPSR_all與SPSR和意義相同 CPSR_flg或 ;CPSR[31:28]<-Rm[31:28] ;CPSR[31:28]<-Rm[31:28] CPSR_flg,#0xA0000000;CPSR[31:28]<-0xA(setN,C;clearZ,V) ;Rd[31:0]<-CPSR[31:0] ;CPSR[31:0]<- ;CPSR[31:28]<-MSRCPSR_flg,#0x50000000 ;CPSR[31:28]<-0x5(setZ,V;clearN,C)MSRSPSR_all,Rm ;SPSR_<mode>[31:0]<-Rm[31:0]MSR ;SPSR_<mode>[31:28]<-

MSR ;SPSR_<mode>[31:28]<-0xC(setN,Z;MRS ;Rd[31:0]<-□□5乘和帶累加的乘（MUL、4－11：MUL、MLA323232位結(jié)果是一樣的。這些32位，既可用于有符號(hào)乘法，也可用于無(wú)符號(hào)乘法。操作數(shù) 操作數(shù) 結(jié)0xFFFFFFF6 □RdRm一樣。R15必須不能被當(dāng)作操作數(shù)或目標(biāo)寄Rd、RnRs可用作同一個(gè)寄存器?！魿PSR標(biāo)志：□MUL指令占用1S+mI周期，MLA指令占用1S+(m+1)I周期，這里S和I分別代表連續(xù)周期）和內(nèi)部（I周期） 如果乘數(shù)操作數(shù)[32:8]位為全0或全如果乘數(shù)操作數(shù)[32:16]位為全0或全如果乘數(shù)操作數(shù)[32:24]位為全0或全□MUL{cond}{S}Rd,Rm,RsMLA{cond}{S}Rd,Rm,Rs,Rn 雙字母條件助記符，見(jiàn)表 Rd,Rm,RsandRn ; ;ConditionallyR1:=R2*R3+R4,Settingcondition□□6長(zhǎng)乘和帶累加的長(zhǎng)乘（MULL、該指令僅當(dāng)條件為真時(shí)執(zhí)行，參見(jiàn)表4－4。指令編碼見(jiàn)下圖4－124－12：MULL、MLAL（UMULL和SMULL）32RdHi,RdLo:=Rm*Rs的結(jié)果。6432RdLo32RdHi。帶累加乘法形式（UMLALSMLAL）3264位數(shù)得RdHi,RdLo:=Rm*Rs+RdHi,RdLo的結(jié)果。6432RdLo讀取，64位32RdHi讀取，6432RdLo32RdHi?！酢魿PSR□對(duì)有符號(hào)指令SMULL、□..對(duì)無(wú)符號(hào)指令UMULL、□..SI分別代表連續(xù)（S周期）和內(nèi)部（I周期）。表4－7.這里 雙字母條件助記符，見(jiàn)表 RdLo,RdHi,Rm, 除R15 ;R4,R1:=R2*R3 ;R5,R1:=R2*R3+R5□□7該指令僅當(dāng)條件為真時(shí)執(zhí)行參見(jiàn)表4－4。指令編碼見(jiàn)下圖4－134-13□在指令中，基址寄存器的偏移量既可以是12bit的無(wú)符號(hào)立即數(shù)，也可以是一個(gè)第二寄關(guān)于尋址方式是增加還是減少模式，指令的W位（即D21）給出了可選項(xiàng)。當(dāng)W=1=0時(shí)，基址寄存器值不變。在前索引位是多余的，并且總被設(shè)置為0。因此前索引數(shù)據(jù)傳輸總是回寫(xiě)到已經(jīng)修改的基址寄存器。在后索引數(shù)據(jù)傳輸中W位使得在非特權(quán)模式下□□該指令級(jí)別可用于在ARM920T寄存器和存儲(chǔ)器之間轉(zhuǎn)移一個(gè)字節(jié)（B=1）（B=0）□Little-EndianLDRB7~0這樣的802-2。0~70~2存取的半字將0~1516bit31bit31。4-14.Little-Endian□Big-Endian802-1。bit31bit31。□R15不能將R15用作寄存器偏置（Rm） 所以不能使用后尋址的LDR或STR指令，這里Rm是與Rn□□分別定義為順序（S-周期、非順序（N-周期）和內(nèi)部（I-周期。STR2N執(zhí)行周□<LDR|STR>{cond}{B}{T}Rd,這里 雙字母助記符，見(jiàn)表 如果出現(xiàn)B RnandRm <Address>可以是表示產(chǎn)生一個(gè)地址:匯編程序?qū)?huì)產(chǎn)生一條指令，該指令以PC預(yù)索引尋址 [Rn,<#expression>]{!}<expression>[Rn,{+/-}Rm{,<shift>}]{!}變址寄存器+/-偏置，由<shift>后索引尋址 <expression>[Rn],{+/- 如果出現(xiàn)!寫(xiě)回基本寄存器(見(jiàn)W位 □□8半字和有符號(hào)數(shù)據(jù)轉(zhuǎn)移4－44-15、4－164-15.4-16.□8bit（可能被移位）U=1時(shí)基址寄存器RnU0時(shí)基址寄存器Rn偏移量的修改可以在基址寄存器被用于傳輸?shù)刂分埃ㄇ八饕齈=1）或之后（后索引P=0）關(guān)于尋址方式是增加還是減少模式，指令的W位（即D21）給出了可選項(xiàng)。當(dāng)W=1=0時(shí)，基址寄存器值不變。在前索引當(dāng)選擇后索引尋址時(shí)，回寫(xiě)位不應(yīng)該被置為高（即W=1）□當(dāng)設(shè)置S=0和H=1□時(shí)，L位不應(yīng)該為0(表示存儲(chǔ))。LDRSB指令裝載所選的字節(jié)到目的寄存器中的7～0位，同時(shí)在高24LDRSH指令裝載所選的字節(jié)到目的寄存器中的15～0位，同時(shí)在高16位進(jìn)行符號(hào)擴(kuò)□端點(diǎn)形式和字節(jié)/8位，其余的位作符號(hào)擴(kuò)展。（A[1]=1A[0]=1ARM920T將導(dǎo)入一個(gè)無(wú)法預(yù)測(cè)的值。這個(gè)被選半字被放入目標(biāo)寄存器的16位；對(duì)于其余的位，LDRSH作符號(hào)擴(kuò)展；LDRH0。半字存儲(chǔ)（STRH）21631~0。外部存8位，其余的位作符號(hào)擴(kuò)展。（A[1]=1A[0]=1ARM920T將導(dǎo)入一個(gè)無(wú)法預(yù)測(cè)的值。這個(gè)被選半字被放入目標(biāo)寄存器的16位；對(duì)于其余的位，LDRSH作符號(hào)擴(kuò)展；LDRH0。□使用當(dāng)R15被用作基址寄存器(Rn)，則不應(yīng)該指定回寫(xiě)位。當(dāng)將R15用作基址寄存器時(shí)，必須記住它包含了在當(dāng)前指令地址上的一個(gè)8bytes地址。R15不能被用作移位寄存器當(dāng)R15被用作一個(gè)半字存儲(chǔ)指令(STRH)的源寄存器(Rd)時(shí)，存儲(chǔ)地址必須是指令地□□LDR（H、SH、SB）1S+1N+1I周期，LDR（H、SH、SB）PC2S+2N+1I周期，這里，S、NI分別定義為順序（S-周期、非順序（N-周期和內(nèi)部周期。STRH2N□ 條件碼，參見(jiàn)表 裝載有符號(hào)字節(jié)(僅對(duì)于LDR有效 裝載有符號(hào)半字(僅對(duì)于LDR有效 <Address>可以是 預(yù)索引尋址 [Rn,<#expression>]{!}<expression>[Rn,{+/-}Rm{,<shift>}]{!}變址寄存器+/-偏置，由<shift>后索引尋址 <expression>[Rn],{+/- RnRm用作寄存器操作數(shù)。如果Rn是R15，則匯編后將在當(dāng)前ARM920T 如果出現(xiàn)!寫(xiě)回基本寄存器(見(jiàn)W位 ;將存在R2-R3地址中的半字裝入R1，并回寫(xiě)R2 ;將R3中的半字存儲(chǔ)到R14+14中，不回寫(xiě) R8，[R2],#- ;將R2地址中的有符號(hào)數(shù)據(jù)字節(jié)存入R8中，并回寫(xiě)R2-到R2 ;有條件，將R0存儲(chǔ)地址中的內(nèi)容半字裝入R11 ;產(chǎn)生PC相對(duì)于地址FRED的相對(duì)偏移量 R5,[PC,#(FRED-HERE-8)];存儲(chǔ)R5中的半字到地址FRED中□□9塊數(shù)據(jù)轉(zhuǎn)移（LDM、4－44-17塊傳輸指令用于裝載(LDM)或存儲(chǔ)(STM)當(dāng)前的可以使用的存儲(chǔ)器。它們支持所有可寄存器列表在指令里面占有16位，每一個(gè)位對(duì)應(yīng)一個(gè)寄存器。如bit0＝1，表示對(duì)R0進(jìn)4-17.□從最低存儲(chǔ)器地址導(dǎo)入。假設(shè)考慮傳輸R1、R5、R7，基址寄存器Rn=0x1000，同時(shí)回寫(xiě)修改基址寄存器(W=1)。圖4－22給出了傳輸?shù)慕Y(jié)果。□4-18.4-19.4-20.4-21.□使用S對(duì)于LDM和STMR15LDMSTMR15INCLUSIONOFTHEBASEINTHEREGISTERDATAAbortduringSTM在STMAbortsduringLDM在LDMn為轉(zhuǎn)移的字節(jié)數(shù)。這里 括在{}(即{R0,R2- 如果出現(xiàn)請(qǐng)求，回寫(xiě)(W=1)，其余 4－8參考堆棧要求的形式，F(xiàn)D,ED,FA,EA定義了前/后索引和上/下偏移。F和E“滿”或“空”A和DIA,IB,DA,DB用于堆棧以外的其他LDM/STMLDMFD ;將3STMIAR0,{R0- ;LDMFD R15□.(SP),CPSRLDMFDSP!,{R15}^ ;R15□.(SP),CPSR<-SPSR_mode，僅用于特權(quán)模式STMFDR13,{R0-R14}^ ;將用戶模式寄存器放入堆棧中，僅用于特權(quán)模式STMEDSP!,{R0- ;將R0到R3存儲(chǔ)到空間，同時(shí)R14 ;修改LDMEDSP!,{R0- ;SINGLEDATASWAP3-23.Theinstructionisonlyexecutediftheconditionistrue.ThevariousconditionsaredefinedinTable3-2.TheinstructionencodingisshowninFigure3-23.Thedataswapinstructionisusedtoswapabyteorwordquantitybetweenaregisterandexternalmemory.Thisinstructionisimplementedasamemoryreadfollowedbyamemorywritewhichare“l(fā)ocked”together(theprocessorcannotbeinterrupteduntilbothoperationshavecompleted,andthememorymanageriswarnedtotreatthemasinseparable).Thisclassofinstructionisparticularlyusefulforimplementingsoftwaresemaphores.Theswapaddressisdeterminedbythecontentsofthebaseregister(Rn).Theprocessorfirstreadsthecontentsoftheswapaddress.Thenitwritesthecontentsofthesourceregister(Rm)totheswapaddress,andstorestheoldmemorycontentsinthedestinationregister(Rd).Thesameregistermaybespecifiedasboththesourceanddestination.TheLOCKoutputgoesHIGHforthedurationofthereadandwriteoperationstosignaltotheexternalmemorymanagerthattheyarelockedtogether,andshouldbeallowedtocompletewithoutinterruption.Thisisimportantinmulti-processorsystemswheretheswapinstructionistheonlyindivisibleinstructionwhichmaybeusedtoimplementsemaphores;controlofthememorymustnotberemovedfromaprocessorwhileitisperformingalockedoperation.3-23-23BYTESANDThisinstructionclassmaybeusedtoswapabyte(B=1)oraword(B=0)betweenanARM920Tregisterandmemory.TheSWPinstructionisimplementedasaLDRfollowedbyaSTRandtheactionoftheseisasdescribedinthesectiononsingledatatransfers.Inparticular,thedescriptionofBigandLittleEndianconfigurationappliestotheSWPinstruction.USEOF使用DonotuseR15asanoperand(Rd,RnorRs)inaSWPDATAIftheaddressusedfortheswapisunacceptabletoamemorymanagementsystem,thememorymanagercanflagtheproblembydrivingABORTHIGH.Thiscanhappenoneitherthereadorthewritecycle(orboth),andineithercase,theDataAborttrapwillbetaken.Itisuptothesystemsoftwaretoresolvethecauseoftheproblem,thentheinstructioncanberestartedandtheoriginalprogramcontinued.INSTRUCTIONCYCLESwapinstructionstake1S+2N+1Iincrementalcyclestoexecute,whereS,NandIaredefinedassequential(S-cycle),non-sequential,andinternal(I-cycle),respectively.周期）和內(nèi)部（I-周期ASSEMBLER<SWP>{cond}{B} Two-characterconditionmnemonic.SeeTable3- IfBispresentthenbytetransfer,otherwisewordtransfer Expressionsevaluatingtovalidregisternumbers ;LoadR0withthewordaddressedbyR2,;storeR1at ;LoadR2withthebyteaddressedbyR4,;storebits0to7ofR3atSWPEQ ;Conditionallyswapthecontentsof;wordaddressedbyR1with<SWP>{cond}{B} 雙字母條件助記符，見(jiàn)表3- 如果出現(xiàn)B

0~7SWPEQ ;有條件地與R0交換以R1SOFTWAREINTERRUPTTheinstructionisonlyexecutediftheconditionistrue.ThevariousconditionsaredefinedinTable3-2.TheinstructionencodingisshowninFigure3-24,below.3-23-243-24.ThesoftwareinterruptinstructionisusedtoenterSupervisormodeinacontrolledmanner.Theinstructioncausesthesoftwareinterrupttraptobetaken,whicheffectsthemodechange.ThePCisthenforcedtoafixedvalue(0x08)andtheCPSRissavedinSPSR_svc.IftheSWIvectoraddressissuitablyprotected(byexternalmemorymanagementhardware)frommodificationbytheuser,afullyprotectedoperatingsystemmaybeconstructed.（由外部存儲(chǔ)器管理硬件），RETURNFROMTHEThePCissavedinR14_svcuponenteringthesoftwareinterrupttrap,withthePCadjustedtopointtothewordaftertheSWIinstruction.MOVSPC,R14_svcwillreturntothecallingprogramandrestoretheCPSR.在進(jìn)入軟件中斷陷阱時(shí)，PC被存入R14_svc，然后PC指向SWI指令后的字。MOVSNotethatthelinkmechanismisnotre-entrant,soifthesupervisorcodewishestousesoftwareinterruptswithinitselfitmustfirstsaveacopyofthereturnaddressandSPSR.COMMENTThebottom24bitsoftheinstructionareignoredbytheprocessor,andmaybeusedtocommunicateinformationtothesupervisorcode.Forinstance,thesupervisormaylookatthisfieldanduseittoindexintoanarrayofentrypointsforroutineswhichperformthevarioussupervisorfunctions.INSTRUCTIONCYCLESoftwareinterruptinstructionstake2S+1Nincrementalcyclestoexecute,whereSandNaredefinedassequential(S-cycle)andnon-sequential(N-cycle).周期ASSEMBLERSWI{cond} Twocharacterconditionmnemonic,Table3-<expression>Evaluatedandplacedinthecommentfield(whichisignoredby

;Getnextcharacterfromreadstream. ;Outputa"k"tothewritestream.SWINE0 ;Conditionallycallsupervisorwith0incommentfield.SWI{cond} 雙字母條件助記符，見(jiàn)表3-<expression>估計(jì)和放入注釋區(qū)(ARM920T不理睬 ; ;在寫(xiě)流程中輸出SWINE ;有條件調(diào)用注釋區(qū)0SupervisorThepreviousexamplesassumethatsuitablesupervisorcodeexists,for0x08B;SWIentry;AddressesofsupervisorDCDDCDDCD EQUEQUEQU ;SWIhasroutinerequiredinbits8-23anddata(ifany)in;bits0-7.AssumesR13_svcpointstoasuitableSTMFDR13,{R0-R2,R14};Saveworkregistersandreturnaddress. ;GetSWIinstruction.BICR0,R0,#0xFF000000 ;Cleartop8bits. ;Getroutineoffset. ;Getstartaddressofentrytable. ;Branchtoappropriateroutine. ;EnterwithcharacterinR0bits0-7.LDMFDR13,{R0- ;Restoreworkspaceand;restoringprocessormodeandCOPROCESSORDATAOPERATIONSTheinstructionisonlyexecutediftheconditionistrue.ThevariousconditionsaredefinedinTable3-2.TheinstructionencodingisshowninFigure3-25.Thisclassofinstructionisusedtotellacoprocessortoperformsomeinternaloperation.NoresultiscommunicatedbacktoARM920T,anditwillnotwaitfortheoperationtocomplete.Thecoprocessorcouldcontainaqueueofsuchinstructionsawaitingexecution,andtheirexecutioncanoverlapotheractivity,allowingthecoprocessorandARM920Ttoperformindependenttasksin3-23-25COPROCESSORTheS3C2410X,unlikesomeotherARM-basedprocessors,doesnothaveanexternalcoprocessorinterface.Itdoesnothaveaon-chipcoprocessoralso.SothenallcoprocessorinstructionswillcausetheundefinedinstructiontraptobetakenontheS3C2410X.Thesecoprocessorinstructionscanbeemulatedbytheundefinedtraphandler.EventhoughexternalcoprocessorcannotbeconnectedtotheS3C2410X,thecoprocessorinstructionsarestilldescribedhereinfullforcompleteness.(Rememberthatanyexternalcoprocessordescribedinthissectionisasoftwareemulation.)3-25.Onlybit4andbits24to31ThecoprocessorfieldsaresignificanttoARM920T.Theremainingbitsareusedbycoprocessors.Theabovefieldnamesareusedbyconvention,andparticularcoprocessorsmayredefinetheuseofallfieldsexceptCP#asappropriate.TheCP#fieldisusedtocontainanidentifyingnumber(intherange0to15)foreachcoprocessor,andacoprocessorwillignoreanyinstructionwhichdoesnotcontainitsnumberintheCP#field.TheconventionalinterpretationoftheinstructionisthatthecoprocessorshouldperformanoperationspecifiedintheCPOpcfield(andpossiblyintheCPfield)onthecontentsofCRnandCRm,andplacetheresultinCRd.INSTRUCTIONCYCLECoprocessordataoperationstake1S+bIincrementalcyclestoexecute,wherebisthenumberofcyclesspentinthecoprocessorbusy-waitloop.SandIaredefinedassequential(S-cycle)andinternal(I-協(xié)處理器操作占用1S+bI周期，這里，bASSEMBLERCDP{cond} Twocharacterconditionmnemonic.SeeTable3-2. Theuniquenumberoftherequiredcoprocessor EvaluatedtoaconstantandplacedintheCPOpccd,cnandcmEvaluatetothevalidcoprocessorregisternumbersCRd,CRnandCRm WherepresentisevaluatedtoaconstantandplacedintheCPCDP{cond} 雙字母條件助記符，見(jiàn)表3- cd,cnandcm分別表示有效協(xié)處理器寄存器號(hào)CRd、CRn和 ;Requestcoproc1todooperation;onCR2andCR3,andputtheresultinCDPEQp2,5,c1,c2,c3,2 ;IfZflagissetrequestcoproc2todooperation5(type2);onCR2andCR3,andputtheresultinCOPROCESSORDATATRANSFERS(LDC,協(xié)處理器數(shù)據(jù)轉(zhuǎn)移（LDC、Theinstructionisonlyexecutediftheconditionistrue.ThevariousconditionsaredefinedinTable3-2.TheinstructionencodingisshowninFigure3-26.Thisclassofinstructionisusedtoload(LDC)orstore(STC)asubsetofacoprocessors'sregistersdirectlytomemory.ARM920Tisresponsibleforsupplyingthememoryaddress,andthecoprocessorsuppliesoracceptsthedataandcontrolsthenumberofwordstransferred.3-23-263-26.THECOPROCESSORTheCP#fieldisusedtoidentifythecoprocessorwhichisrequiredtosupplyoracceptthedata,andacoprocessorwillonlyrespondifitsnumbermatchesthecontentsofthisfield.TheCRdfieldandtheNbitcontaininformationforthecoprocessorwhichmaybeinterpretedindifferentwaysbydifferentcoprocessors,butbyconventionCRdistheregistertobetransferred(orthefirstregisterwheremorethanoneistobetransferred),andtheNbitisusedtochooseoneoftwotransferlengthoptions.ForinstanceN=0couldselectthetransferofasingleregister,andN=1couldselectthetransferofalltheregistersforcontextswitching.ADDRESSINGARM920Tisresponsibleforprovidingtheaddressusedbythememorysystemforthetransfer,andtheaddressingmodesavailableareasubsetofthoseusedinsingledatatransferinstructions.Note,however,thattheimmediateoffsetsare8bitswideandspecifywordoffsetsforcoprocessordatatransfers,whereastheyare12bitswideandspecifybyteoffsetsforsingledatatransfers.The8bitunsignedimmediateoffsetisshiftedleft2bitsandeitheraddedto(U=1)orsubtractedfrom(U=0)thebaseregister(Rn);thiscalculationmaybeperformedeitherbefore(P=1)orafter(P=0)thebaseisusedasthetransferaddress.Themodifiedbasevaluemaybeoverwrittenbackintothebaseregister(ifW=1),ortheoldvalueofthebasemaybepreserved(W=0).Notethatpost-indexedaddressingmodesrequireexplicitsettingoftheWbit,unlikeLDRandSTRwhichalwayswrite-backwhenpost-indexed.Thevalueofthebaseregister,modifiedbytheoffsetinapre-indexedinstruction,isusedastheaddressforthetransferofthefirstword.Thesecondword(ifmorethanoneistransferred)willgotoorcomefromanaddressoneword(4bytes)higherthanthefirsttransfer,andtheaddresswillbeincrementedbyonewordforeachsubsequenttransfer.ADDRESSThebaseaddressshouldnormallybeawordalignedquantity.Thebottom2bitsoftheaddresswillappearonA[1:0]andmightbeinterpretedbythememorysystem.Useof使用IfRnisR15,thevalueusedwillbetheaddressoftheinstructionplus8bytes.Basewrite-backtoR15mustnotbespecified.DATAIftheaddressislegalbutthememorymanagergeneratesanabort,thedatatrapwillbetaken.Thewrite-backofthemodifiedbasewilltakeplace,butallotherprocessorstatewillbepreserved.Thecoprocessorispartlyresponsibleforensuringthatthedatatransfercanberestartedafterthecauseoftheaborthasbeenresolved,andmustensurethatanysubsequentactionsitundertakescanberepeatedwhentheinstructionisretried.INSTRUCTIONCYCLECoprocessordatatransferinstructionstake(n-1)S+2N+bIincrementalcyclestoexecute,where:nThenumberofwordstransferred.bThenumberofcyclesspentinthecoprocessorbusy-waitS,NandIaredefinedassequential(S-cycle),non-sequential(N-cycle),andinternal(I-cycle),協(xié)處理器數(shù)據(jù)轉(zhuǎn)移指令占用(n-1)S+2N+bI周期，這里 ASSEMBLER<LDC|STC>{cond}{L} Loadfrommemoryto Storefromcoprocessorto Whenpresentperformlongtransfer(N=1),otherwiseperformshorttransfer Twocharacterconditionmnemonic.SeeTable3-2.. Theuniquenumberoftherequiredcoprocessor AnexpressionevaluatingtoavalidcoprocessorregisternumberthatisplacedintheCRdfield<Address>canAnexpressionwhichgeneratesanTheassemblerwillattempttogenerateaninstructionusingthePCasabaseandacorrectedimmediateoffsettoaddressthelocationgivenbyevaluatingtheexpression.ThiswillbeaPCrelative,pre-indexedaddress.Iftheaddressisoutofrange,anerrorwillbegeneratedApre-indexedaddressing offsetof[Rn,<#expression>]{!}offsetof<expression>Apost-indexedaddressing offsetof<expression> writebackthebaseregister(settheWbit)if!is isanexpressionevaluatingtoavalidARM920Tregisternumber.IfRnisR15,theassemblerwillsubtract8fromtheoffsetvaluetoallowforARM920T ;Loadc2ofcoproc1from;table,usingaPCrelativeaddress. ;Conditionallystorec3ofcoproc;intoanaddress24bytesupfrom;writethisaddressbacktoR5,and;longtransferoption(probablytostoremultipleAlthoughtheaddressoffsetisexpressedinbytes,theinstructionoffsetfieldisinwords.Theassemblerwilladjusttheoffsetappropriately.COPROCESSORREGISTERTRANSFERS(MRC,協(xié)處理器寄存器轉(zhuǎn)移（MRC、Theinstructionisonlyexecutediftheconditionistrue.ThevariousconditionsaredefinedTable3-2..TheinstructionencodingisshowninFigure3-ThisclassofinstructionisusedtocommunicateinformationdirectlybetweenARM920Tandacoprocessor.AnexampleofacoprocessortoARM920Tregistertransfer(MRC)instructionwouldbeaFIXofafloatingpointvalueheldinacoprocessor,wherethefloatingpointnumberisconvertedintoa32bitintegerwithinthecoprocessor,andtheresultisthentransferredtoARM920Tregister.AFLOATofa32bitvalueinARM920TregisterintoafloatingpointvaluewithinthecoprocessorillustratestheuseofARM920Tregistertocoprocessortransfer(MCR).AnimportantuseofthisinstructionistocommunicatecontrolinformationdirectlyfromthecoprocessorintotheARM920TCPSRflags.Asanexample,theresultofacomparisonoftwofloatingpointvalueswithinacoprocessorcanbemovedtotheCPSRtocontrolthesubsequentflowofexecution.3-23-273-27.THECOPROCESSORTheCP#fieldisused,asforallcoprocessorinstructions,tospecifywhichcoprocessorisbeingcalledupon.TheCPOpc,CRn,CPandCRmfieldsareusedonlybythecoprocessor,andthepresentedhereisderivedfromconventiononly.Otherinterpretationsareallowedwherethecoprocessorfunctionalityisincompatiblewiththisone.TheconventionalinterpretationisthattheCPOpcandCPfieldsspecifytheoperationthecoprocessorisrequiredtoperform,CRnisthecoprocessorregisterwhichisthesourceordestinationofthetransferredinformation,andCRmisasecondcoprocessorregisterwhichmaybeinvolvedinsomewaywhichdependsontheparticularoperationspecified.對(duì)所有協(xié)處理器指令，CP#CPOpc、CRn、CPCRm區(qū)僅用于協(xié)處理器，并且這里的解釋僅僅來(lái)源于慣例。TRANSFERSTOR15轉(zhuǎn)移到WhenacoprocessorregistertransfertoARM920ThasR15asthedestination,bits31,30,29and28ofthetransferredwordarecopiedintotheN,Z,CandVflagsrespectively.Theotherbitsofthetransferredwordareignored,andthePCandotherCPSRbitsareunaffectedbythetransfer.TRANSFERSFROM從R15AcoprocessorregistertransferfromARM920TwithR15asthesourceregisterwillstorethe一個(gè)從ARM920T的帶有R15作為源寄存器的協(xié)處理器寄存器轉(zhuǎn)移將存儲(chǔ)PC+12INSTRUCTIONCYCLEMRCinstructionstake1S+(b+1)I+1Cincrementalcyclestoexecute,whereS,IandCaredefinedassequential(S-cycle),internal(I-cycle),andcoprocessorregistertransfer(C-cycle),respectively.MCRinstructionstake1S+bI+1Cincrementalcyclestoexecute,wherebisthenumberofcyclesspentinthecoprocessorbusy-waitloop.MRC指令占用1S+(b+1)I+1C周期，LDRPC占用2S+2N+1I周期，這里，S、I和C分別定ASSEMBLER<MCR|MRC>{cond}p#,<expression1>,Rd,cn,cm{,<expression2>} MovefromcoprocessortoARM920Tregister(L=1) MovefromARM920Tregistertocoprocessor Twocharacterconditionmnemonic.SeeTable3-2 Theuniquenumberoftherequiredcoprocessor EvaluatedtoaconstantandplacedintheCPOpc AnexpressionevaluatingtoavalidARM920Tregistercnandcm ExpressionsevaluatingtothevalidcoprocessorregisternumbersCRnandCRmrespectively WherepresentisevaluatedtoaconstantandplacedintheCP ;Requestcoproc2toperformoperation;onc5andc6,andtransferthe;32-bitword)resultbackto ;Requestcoproc6toperformoperation;onR4andplacetheresultinc6.MRCEQ ;Conditionallyrequestcoproc3;performoperation9(type2)onc5;c6,andtransfertheresultbacktoUNDEFINEDTheinstructionisonlyexecutediftheconditionistrue.ThevariousconditionsaredefinedinTable3-2.TheinstructionformatisshowninFigure3-28.3-23-283-28.Iftheconditionistrue,theundefinedinstructiontrapwillbeNotethattheundefinedinstructionmechanisminvolvesofferingthisinstructiontoanycoprocessorswhichmaybepresent,andallcoprocessorsmustrefusetoacceptitbydrivingCPAandCPBHIGH.INSTRUCTIONCYCLEThisinstructiontakes2S+1I+1Ncycles,whereS,NandIaredefinedassequential(S-cycle),non-sequential(N-cycle),andinternal(I-cycle).ASSEMBLERTheassemblerhasnomnemonicsforgeneratingthisinstruction.Ifitisadoptedinthefutureforsomespecifieduse,suitablemnemonicswillbeaddedtotheassembler.Untilsuchtime,thisinstructionmustnotbeused.INSTRUCTIONSETThefollowingexamplesshowwaysinwhichthebasicARM920Tinstructionscancombinetogiveefficientcode.Noneofthesemethodssavesagreatdealofexecutiontime(althoughtheymaysavesome),mostlytheyjustsavecode.USINGTHECONDITIONALUsingConditionalsforLogical ;IfRn=pORRm=qTHENGOTOLabel. Thiscanbereplaced CMPNERm,#q ;Ifconditionnotsatisfiedtryothertest. Absolute;Test;and2'scomplementifMultiplicationby4,5or6(Run Rc,Ra,LSL#2;Multiplyby4, ;Testvalue,ADDCSRc,Rc,Ra ;Completemultiplyby5,ADDHIRc,Rc,Ra ;Completemultiplyby6.CombiningDiscreteandRange ;Discretetest,CMPNERc,#""-1 ;RangetestMOVLSRc,# ;IFRc<=""OR;THENRc:=DivisionandAnumberofdivideroutinesforspecificapplicationsareprovidedinsourceformaspartoftheANSIClibraryprovidedwiththeARMCrossDevelopmentToolkit,availablefromyoursupplier.Ashortgeneralpurposedivideroutinefollows.;EnterwithnumbersinRaand ;Bittocontrolthe ;MoveRbuntilgreaterthanCMPCCRb,RaMOVCCRb,Rb,ASL#1MOVCCRcnt,Rcnt,ASL#1 ;TestforpossibleSUBCS ;SubtractifADDCSRc,Rc,Rcnt ;Putrelevantbitintoresult ;ShiftcontrolbitMOVNE ;Halveunless ;DivideresultinRc,remainderinOverflowDetectionintheARM920TOverflowinunsignedmultiplywitha32-bitUMULL ;3to6 ;+1cycleandaregister Overflowinsignedmultiplywitha32-bitSMULL ;3to6 Rt,RdASR#31 ;+1cycleandaregister Overflowinunsigned