《信息科學類專業(yè)英語》課件第22章

Lesson22Moore’slaw:theFutureofSimicroelectronics

(第二十二課摩爾定律:硅微電子學的未來)

Vocabulary(詞匯)ImportantSentences(重點句)QuestionsandAnswers(問答)Problems(問題)

SoonafterBardeen,Brattain,andShockleyinventedasolid-statedevicein1947toreplaceelectronvacuumtubes,themicroelectronicsindustryandarevolutionstarted.Sinceitsbirth,theindustryhasexperiencedfourdecadesofunprecedentedexplosivegrowthdrivenbytwofactors:NoyceandKilbyinventingtheplanarintegratedcircuitandtheadvantageouscharacteristicsthatresultfromscaling(shrinking)solid-statedevices.Scalingsolid-statedeviceshasthepeculiarpropertyofimprovingcost,performance,andpower,whichhashistoricallygivenanycompanywiththelatesttechnologyalargecompetitiveadvantageinthemarket.Asaresult,themicroelectronicsindustryhasdriventransistorfeaturesizescalingfrom10μmto30nmduringthepast40years.Duringmostofthistime,scalingsimplyconsistedofreducingthefeaturesize.However,duringcertainperiods,thereweremajorchangesaswiththeindustrymovefromSibipolartop-channelMetal-OxideSemiconductor(MOS),thenton-channelMOS,andfinallytoComplementaryMOS(CMOS)planartransistorsinthe1980s,whichhasremainedthedominatetechnologyforthepasttwodecades.ThebigchallengegoingforwardisthattheendofplanarCMOStransistorscalingisnearasthetransistorsizeapproachestensofnanometers.Howtheindustryevolvesafterthislimitisreachedisunclear.

Toaddressthesechallenges,presentdayresearchisfocusedonidentifyingnewmaterialsanddevicesthatcanaugmentand/orpotentiallyreplacetheaging50-year-oldSitransistor.Twoapproachesunderinvestigationare:(1)nonclassicalCMOS,whichconsistsofnewchannelmaterialsand/ormultigatefullydepleteddevicestructures;and(2)alternativestoCMOS,suchasspintronics,singleelectrondevices,andmolecularcomputingWhilesomeofthesenon-Siresearchareasareimportantandwillbesuccessfulinnewapplicationsandmarkets,itseemsunlikelyanyofthenon-SioptionscanreplacetheSitransistorforthe$300billionmicroelectronicsindustryintheforeseeablefuture(perhapsaslongas30years).

ThisreviewaimstoexplainthefutureofSimicroelectronics,keyissuesattheendoftheSiroadmap,andthetimeframeforpossiblenon-Sitechnologyreplacements.WefirstdiscussthestateofMoore’slawandconventionalplanarSitransistorscalinglimits.Next,wecovertheissuesattheendoftheSiroadmapbasedoncurrenttechnologytrends.Weend,perhapsfoolhardily,withanassessmentofnonclassicalCMOSandalternativestoCMOS.Thekeytakeawaymessagesarethatsimplescalinghasended,thereisenormouslifeleftinplanarSiCMOStechnology,andnothingisonthehorizontoreplaceitformainstreamlogicapplications.[1]

1StatusofMoore’slaw

Moore’slawistheempiricalobservationthatcomponentdensityandperformanceofintegratedcircuitsdoubleseveryyear,whichwasthenrevisedtodoublingeverytwoyears.GuidedbythescalingrulessetbyDennardin1974,smartoptimization,timelyintroductionofnewprocessingtechniques,devicestructures,andmaterials(inmanyareasofthedeviceexceptthechannel),Moore’slawhascontinuedunabatedfor40years.Drivenbytremendousadvancesinlithography,the65nmlogictechnologynodefeaturing30nmtransistorsiscurrentlyinhighvolumeproduction.Furthermore,45nmand32nmtechnologieswithprocesstargetsdefinedtomaintainMoore’slawarecurrentlyunderdevelopmentatseveralcompanies.Withsuchsmallfeaturesizesinhighvolumeproductionandunderdevelopment,SiCMOStechnologiesarenowleadingthefieldofnanotechnologyandwillcontinuetodoso.Nanotechnologyisdefined,accordingtotheNationalScienceandEngineeringTechnologyCouncil(NSET),as:

Researchandtechnologydevelopmentattheatomic,molecular,ormacromolecularlevels,inthelengthscaleofapproximately1-100nmrange,toprovideafundamentalunderstandingofphenomenaandmaterialsatthenanoscaleandtocreateandusestructures,devices,andsystemsthathavenovelpropertiesandfunctionsbecauseoftheirsmalland/orintermediatesize.Thenovelanddifferentiatingpropertiesandfunctionsaredevelopedatacriticallengthscaleofmattertypicallyunder100nm.

SiMOSFETsenteredthenanometereraaround2000,asseeninFig.1,thatshowstechnologynodeandtransistorfeaturesizeversusyearforthesemiconductorindustry.Forthe0.13μmtechnologynode,theindustryincorporated70nmgatelengthtransistorsonaverage.Whatisinterestingtonoteisthattraditionaltop-downmicroelectronicshavenotonlybecomenanoelectronicsbutthedevicedimensionsarenowcomparabletothosebeingexploredinthenewfieldofbottom-upnanotechnologyandmolecularelectronics!Fig.1Logictechnologynodeandtransistorgatelengthversuscalendar

year.NotemainstreamSitechnologyisnanotechnology

Thekeydriverbehindthesetrendsiseconomics,aspointedoutbyMoorein1965.AccordingtoMoore,integratedcircuitsandscalingare“thecheapwaytodoelectronics”.EvenwithlargeincreasesinlithographytoolcosttofabricatenanoscaleCMOStransistors(forexample,thecostoflithographysteppersincreasedfrom$10000to$35million,asshowninFig.2),whichhasleadtomodernfactoriescosting$2-3billion,thecostpertransistorhasdecreasedbysevenordersofmagnitudeduringthelast40years(Fig.2)andislikelytocontinuetodecreaseforanotherdecade.However,CMOStransistorscalingmustinevitablyslowdownandfinallyhalt,atleastinthetraditionalsense,asthelithographyscaleapproachesatomicdimensions.Fig.2Transistorcostandlithographictoolcostversusyears.

Notetransistorcosthasdecreasedsevenordersofmagnitudeevenwhiletoolcosthasincreased.2CMOSLimits

WhenstartingadiscussionofCMOSlimits,itisfirstimportanttopointoutthatwhenthelimitsarehit,thiswillnotbetheendofintegratedcircuitsorMoore’slaw.Allitmeansisthattherateofimprovementwillchangeonceagain(ashappenedin1975).ImprovementswillinsteadcomefromareasotherthanscalingandSiCMOStechnologywillcontinueformanydecadesbeforeacrediblealternativearises.Forexample,evenifdevicedensityslows,costpertransistorwillcontinuetobereducedthroughimprovedtoolproductivity,cycletimereduction,defectelimination,andpossibly,thoughunlikely,anotherwafersizeconversionbytheindustry,thusfurtherextendingMoore’slaw.Nextitisimportanttoclassifythelimitsaspracticalortheoreticalandintothecategoriesoflithography,transistor,andwiring.Inthiswork,wewillfocusontransistorlimitssincethisappearstobethemostseriousissue.Atpresent,lithographywillnotbethelimiter.Asatestamentastohowfarengineerscanpushmainstreamtechnology,conventionalopticallithographyenhancedwithhighnumericalaperture,reticalenhancementtechniques,anddoubleexposurecanpatternthe22nmnode,puttingintoquestiontheroleofnonopticallithographytechniquessuchasExtremeUltraViolet(EUV)lithographyWiringlimits,thoughserious,canbeaddressedbyarchitectureandaddingmoremetallayers.3PlanarCMOSTransistorLimits

Transistorscalinglimitsarisefrompracticallimitsrelatedtoleakagecurrentatsmallgatelengths.Theproblematsmallgatelengthsisthatthedrainvoltagereducesthebarrierheightatthesource,therebycausingalowsource-to-channelbarrierheightevenwiththegatevoltageoff,whichleadstoundesirable,largeoff-stateleakage.Thisphenomenonisreferredtoasdrain-inducedbarrierloweringand/ordegradedShortChannelEffect(SCE).ForevidencethatCMOSplanartransistorsareapproachingtheirminimumpracticalsize,oneonlyneedlookattheoff-stateleakagetrendsfortheindustry.CMOSwasinitiallypromisedasatechnologythatdissipatednegligiblepowerinthestandbystate.Inpresentdayhigh-performancelogictechnologiesdesignedformicroprocessors,theleakagepowerofCMOStransistorsisapproximately20-30W(outofatotalpowerbudgetof100W).Thismagnitudeofleakageisalreadyatthepracticallimitsinceitincreasespackagingcost(becauseofcooling)and,evenmoreimportantly,energycost(bothintermsofutilitybillsandtheinfrastructuretogetenergyintocorporateservercomputerrooms).Topreventfurtherincreasesinleakage,therateofgatelengthscalinghasalreadyslowedintherecent90nmand65nmtechnologynodes.ThereisnohardlimitontheminimumsizeofaplanarCMOSdevice,butpracticalconsiderationsonleakagelimitthephysicalgatelengthto20nm.

Withtheindustryalreadyclosetothelimitsofplanartransistors,progresscanstillbeachievedusingmethodsotherthanscaling.OnepossibleoptionisyetagaintomovetoalternatedevicestructureswhilestillusingaSichannelsuchasmultigatefullydepleteddevices(sometimescallednonclassicalCMOS).Withoutquestion,thesenonclassicaldevicesimproveSCE(reduceleakage)becauseofimprovedelectrostaticsfromthemultigatesandultrathinbodies.Fig.3showsasummaryoffullydepleteddevicesinvestigatedbytheindustryduringthepasttwodecades.AllofthesedevicesarebasedonathinlayerofSi-On-Insulator(SOI).However,thispathhasnotbeenchosenbytheindustryatpresentandkeepsgettingpushedouttofuturetechnologynodesbecauseofthreedifficultandunsolvedissues:(1)athinbodyleadstohigherexternalresistance,whichwillbeshowntobeasignificantissueinstate-of-the-artnanoscaleMOSFETSwheretheexternalresistanceisbecomingcomparableinmagnitudetothechannelresistance;(2)significantuniformity,processcomplexity,andcostissuesassociatedwithfabricatingmultigatedevices;and(3)difficultyinengineeringthebandstructureinfullydepleteddevicesusingstrain(tocreatealowconductivitymass),whichhasalreadybecomemainstreaminplanarCMOStoincreasecarriermobility(transistorspeed).

Insteadofmovingtoanewdevicestructure,thepathchosenbytheindustryistoimprovetransistorperformancewithoutanyfurthershrinkingofthetransistorgatelengthbyintroducinglatticestrainintotheSichannel.ThisapproachsignificantlyaltersthebandstructureandaddressesSitransportdeficienciescomparedwithotherhigh-mobility,III-Vsemiconductors.

Forexample,byalteringthepositionofSiatomsintheface-centeredcubicunitcell,theholeconductivityeffectivemasscanbereducedbyafactorof1/4,whichimprovesmobilityandresultsina100-200%increaseintransistorcurrentanddramaticperformancegains.Asaresult,strainedSiisbeingimplementedinnearlyall90nm,65nm,and45nmtechnologynodes.Theresultshavebeensosuccessfulthatitwillbedifficultforalternativehigh-mobilitychanneltechnologiestocompetewithstrainedSi.TheadoptionofstrainedSiwhilekeepingthegatelengthconstantstillsupportsthehistoricaltransistordensityincreaseandcostreduction(atleastinitially)sincethegatedimensionisonlyafractionofthetransistorpitch(i.e.transistordensityisincreasedbyreducingthespacebetweentransistorsandnotthegatelength).Maintainingaconstantgatelength(whilescalingthespaceandpitch)isviableforafewtechnologynodes,butwilleventuallyleadtoscalingbeinglimitedbyparasiticresistanceandcapacitancebecauseofthespacebetweentransistorsbecomingtoosmall.Fig.3EmergingalternativefullydepletedCMOSstructuresforcontinuescaling;(a)one-;(b,c)two-,and(d)three-gatefutlydepleteddevices.(Part(d)courtesyofR.Chau.intel.)4RealLimiterstoScaling:ParasiticResistanceandCapacitance

WiththeendofplanarSitransistorscalinginsight,itisnowpossibletogiveaninsightintothereallimitsontheSiroadmap,whicharetheparasiticresistanceandcapacitancegenerallyassumednegligiblebyscalingtheories.Thiswasagoodassumptionforthepast40yearsbutwillnolongerbethecaseduringthenextdecade.Fig.4showsthevariousparasiticresistancesandcapacitancespresentinaplanarMOSFET.Thesuddenriseinparasiticsattheendoftheroadmapcanbequalitativelyunderstoodasresultingfromthespacebetweenneighboringdevicesdecreasingtotensofnanometerssincethesource/drainandcontactsizeneedtobeaggressivelyscaledtosupporttheincreaseddensityintheabsenceofgatelengthscaling.Fig.4depictsthetypicaldesignrulesofplanarSitransistorsforthe32nmtechnologynode.Itcanbeseenthatthesource/draincontactandthegateareonlytensofnanometersapart,whichisundesirableintermsofparasiticresistance.Suchsmallcontactsizeleadstohighercontactresistanceandcontact-to-gatecapacitance.Fig.4PlanarCMOSschematicshowingthevariousparasiticresistancesandcapacltances(drawntoscaleforthe32nmprocesstechnologynode,,transistorpitch=100nm)

Historically,theparasiticsdidnotmattersincetheyweremuchsmallerthanthechannelresistanceandcapacitance.However,theintrinsicchannelcapacitanceandresistancehasdecreaseddramaticallyduringthepastfourdecades.Tothefirstorder,channelresistanceandcapacitancearebothproportionaltothegatedimension,whichhasdecreased1000timessincethestartofMoore’slaw.Becauseofsuchdramaticreductionsinchannelresistance,theparasiticresistanceandcapacitancearenowbecomingcomparableandareoncoursetobecomingevenlargerthantheintrinsicdeviceresistanceandcapacitance(Figs.5and6).Figs.5and6wereobtainedusingindustrydesignrulesforthe90nmand65nmtechnologynodes,0.7timesscalingforfuturenodes,andequationsfoundin

references.Slotortrenchcontactsareassumedforthe45nmtechnologynodeandbeyondtohelpminimizecontactresistance.

Theparasiticscalingtrendshighlightaninterestingareawherefuturetransistorresearchneedstobefocusedandimportantmetricsforfuturedevices.Muchofpresentdaytransistorresearchisfocusedonnewchannelmaterialsanddevicesforveryhighmobility.Thescalingtrendssuggestthereallimiterisparasiticsandthatthisiswherethefocusneedstobe.Oncethechannelresistancebecomessmallerthantheexternalresistance,reducingthechannelresistancefurther,eventozero,haslittleperformancebenefit(thesameistrueforcapacitance).Furthermore,andperhapsmoreimportantly,ithighlightsthatnewdevicestructuresneedtobejudgedonparasiticresistanceandcapacitancemorethanonchanneltransportproperties.Todate,parasiticsaremuchworseformostnewdeviceoptionsandrarelyisthistakenintoaccount.Take,forexample,therecentlogiccircuitsdemonstratedincarbonnanotubetransistors.AlthoughthechannelmobilityisseveralordersofmagnitudehigherthanSi,thefabricatedinverters33-35are106-1010timesslowerthanstate-ofthe-artCMOSbecauseofparasitics!Also,infullydepletedmultigatedevicesfabricatedonSifins,theparasiticresistanceisworsethanintheplanarCMOStransistor23,24.Forbothfullydepletedandcarbonnanotubetransistors,thehighparasiticresistanceislikelytobeafundamentalproblembecauseofthesmallsource/drainvolume(thesource/draincontactsconnecttoaSibulk‘box’thatisjust5-10nmthickinthecaseoffullydepleteddevices;incarbonnanotubedevicesthisisevenless,withthethicknessontheorderofoneatomiclayer).Fig.5EstimatedtotalplanarCMOSparasiticandchannelresistanceversustechnologynode.Noteparesiticresistenceisoncoursetobecomelangerthantheintrinsicchannelresistance.Fig.6TotalplanarCMOSparasiticandintrinsicchannelcapacitanceversustechnologynode.Noteparasiticcapacitanceisoncoursetobecomelargerthanintrinsicchannelcapacitance.5ProspectstoReplaceSielectronics

WithSiCMOSscalinglimitsinsight,theobviousquestionsare“WhatnanotechnologyisonthehorizontoreplaceplanarSiCMOStransistorsandinwhattimeframecouldthishappen?”Thoughthesearedifficultandperhapsfoolhardyquestionstotryandanswer,itisimportanttoattempttodososincethisaffectsa$300billionworldwideindustryandthecareersofmostengineers.

Addressingthetimeframequestionfirst,howquicklytheindustrycanadoptaradicallydifferentdevicetypedependsonhowmanyresearchanddevelopmentlevelsitimpacts.Levelsaredefinedbydevelopmenteffortsandorganizationsthatarecurrentlypresentinthemicroelectronicsindustrysuchasmaterials,devicedesign,circuitdesign,computerarchitecture,andsoftware.Asaruleofthumb,pastchangesthataffectonelevelgenerallytakeapproximatelyfiveormoreyearswiththeexceptionofsoftware,whichtakesevenlonger.ExamplesofrecentchangesthatmostlyaffectedonelevelandtookfiveyearsormorearebipolartoplanarCMOStransistors,strainedSi,high-kgatedielectrics,low-kbackenddielectrics,andcomputerarchitecturechangessuchashyperthreadingandthemovefromsinglethreadperformancetodualcoremicroprocessors.Manyofthenon-Sidevicetypesaffectmultipleresearchanddevelopmentlevelswithmostradicalnewdevicesaffectingalllevels.Changesthataffectmultiplelevelscaneasilytakefiveyearsperlevelandareverydifficult.Forexample,anewdevicebasedonsingle-electrontransportorspintronicswilllikelyrequireanewproductarchitectureandsoftwaretotakeadvantageoftheiruniquedeviceattributes(highdensityandlowpower)andlimitations(smalltransistordrivecurrentandinabilitytodrivethesixtotenlayersofCuinterconnectsusedtowirethe100sofmillionstobillionoftransistorsinmodernchips).Thus,aradicallynewdevicetypecouldeasilytakeover15-20yearstocoordinatethechangesamongallthelevelsoncetheindustryhasdecidedtopursuethisapproach.Sincetheindustryisstillmorethanadecadeawayfrommakingadecisiononwhichnewdevicetypetopursue,itputsthetimeframeforaradicalnewnanotechnologydeviceformainstreamlogicapplicationsmorethan30yearsaway.Whentheindustrytalksaboutradicallynewdevicetypesthatwill“revolutionizecomputing”,thistypeoftimeperspectiveisoftenmissed.Fig.7attemptstoputinperspectivethetimeframerequiredtoimplementsomeofthenewradicaldevicetypesintoproduction.

Thesecondpartofthequestioniswhatnon-SitechnologycanpotentiallyreplacetheSiplanardevice.Thisisperhapsanevenmoredifficultquestiontoanswerbutequallyimportantsinceresourcesforasociety(bothpeopleandcapital)needtobefocusedonthebestareasforreturn.Evenwiththesecaveats,someconclusionscanbedrawn.

First,iftheindustryisgoingtospendseveraldecadesatadevelopmentcostlikelytobegreaterthan$100billiontogetatechnologytoalevelcompetitivewiththealready>$1trillioninvestedinSitechnologyduringthepast40years,thenewtechnologyisgoingtohavetoofferatleastanorderofmagnitudeimprovementovertheplanarSiCMOStransistors.Fornoncharge-baseddevicesrelyingonradicallydifferentcomputingmodels,atthistimeitisdifficulttopredictthepotentialperformanceadvantages.However,fornon-Sicharge-baseddevices(Ge,III-V,orcarbonnanotubechannels),whichareviewedasthefirstpossiblereplacementstotheplanarSitransistor,itisnowbecomingpossibletoestimatethepotentialimprovementoverSi.Toassessthepotentialperformance,thefirstordermetricoftenusedisthemagnitudeofthechannelmobilityinthenewdevicetypescomparedwiththesurfacechannelSielectronandholemobility.Thoughcommonlyusedthisbenchmarkis,unfortunately,toosimplisticandinmanycasesleadstowrongconclusions.First,highmobilitycanresultfromeitherlowconductivitymassorscattering.Onlyreducedconductivitymass(asopposedtoreducedscattering)isimportantforballistic-limitedtransport,whichdominatesattheendoftheSiroadmap.Second,andequallyimportant,isthedensity-of-statesforholesandelectronsinthechannelmaterialsincethisaffectstheamountofinversionchargeandthedevicedrivecurrent(bothamountandvelocityofchargedeterminesthecurrent).Mostoftheveryhighmobilitymaterials(forexamplecarbonnanotubes)haveverylowdensity-of-states(severalordersofmagnitudelowerthanSi)makingitdifficulttoachievehighdrivecurrents.Infact,eveninthestrainedSitechnologycurrentlyinproduction,strainisusedtocreatebothalowconductivitymassinthechanneldirectionandahighdensity-of-statesbycreatingaverylargeconductivitymassintheplaneofthetransistorperpendiculartothechanneldirection.Includingtheseconsiderations,isnotclearifanyofthenewchannelmaterialsoffersignificantimprovementoverSi.Furthermore,basedonthepreviousdiscussionofparasiticresistance,fewnewchannelmaterialscancompetesinceagreatdealofdevelopmenthasgoneintoreducingexternalresistanceforSiCMOSdevicesbyusingmillisecondannealstocreateabovesolidsolubilitydopingandincorporatingnickelsilicide(NiSi)andSiGeinthesourceanddrain.6Conclusion

Basedoncurrenttechnologytrends,thescalinglimitstoplanarCMOSareclear.ThoughsimplescalingofplanarCMOShasended,thetechnologywillcontinueapproximatelyonMoore’shistoricalperformancetrendforanotherfewtechnologynodesmakingplanarCMOStheleaderincommercialnanotechnology.ThereallimitstoplanarSiCMOS(andmostnewdevicetypes)areparasiticresistanceandcapacitance.Thus,alternatedevicetypesshouldbebenchmarkedonparasiticsandnotjustchanneltransportproperties.Furthermore,radicallynewdevicetypeswillrequirechangesalongmanyresearchanddevelopmentlevelsfrommaterialstosoftware.Thetimeframetoimplementaradicallynewdeviceisestimatedtobe30years.ThusSiCMOSwillbethedominantformofnanotechnologyfortheforeseeablefuture.Finally,wemustrememberMoore’slawisnotaphysicallawbutalawabouteconomics.Consumerproductsandemergingmarketshavebecomethedominateendmarketsforsemiconductorsandwillcontinuetobesoforthenextdecade(versusthemilitaryinthe1960s-70s).Akeyattributeinthesemarketsisprice.Sitechnologyisoncourseinthenextdecadetoofferabilliontransistorchipsfor$1,whichwillbeaverydifficulttechnologytodisplace.[2]

1.?vacaumn.真空;〈口〉真空吸塵器;空間;空虛;空白vt.用真空吸塵器清掃(某物)。

2.?unprecedentedadj.前所未有的；空前的；沒有先例的。

3.?planaradj.平面的,平坦的。

4.?nanometern.納米。

5.?evolvevt.&vi.演變;進化vi.(動植物等)進化；進化形成。Vocabulary

6.?augmentedadj.增音的,擴張的。

7.?depletevt.使大大的減少;使空虛vi.耗盡；使枯竭。

8.?spintronicsn.自旋電子學。

9.?empiricallyadv.以經(jīng)驗為主地。

10.?reticlen.十字線,刻線。

11.?parasiticadj.寄生的,寄生蟲的;由寄生蟲引起的adv.寄生地;由寄生蟲引起地。

12.?ruleofthumb憑感覺的方法;單憑經(jīng)驗的方法。

13.?takeawayn.外賣餐館,外賣食品。

14.?caveatn.<律>中止訴訟程序的申請；警告,附加說明，告誡。

15.?ballisticadj.發(fā)射的,彈道(學)的,衡量沖擊強度的;大怒,暴跳如雷。

[1]Thekeytakeawaymessagesarethatsimplescalinghasended,thereisenormouslifeleftinplanarSiCMOStechnology,andnothingisonthehorizontoreplaceitformainstreamlogicapplications.

關鍵的信息是，簡單的比例縮放已經(jīng)結束了，但是平面硅CMOS工藝還有巨大的生命力。我們還不能肯定是否有能代替它作為主流邏輯應用的其他工藝。onthehorizon，在地平線上，幾乎肯定會很快發(fā)生的。ImportantSentences

[2]Consumerproductsandemergingmarketshavebecomethedominateforsemiconductorsandwillcontinuetobesoforthenextdecade(versusthemilitaryinthe1960s-70s).Akeyattributeinthesemarketsisprice.Sitechnologyisinthenextdecadetoofferabilliontransistorchipsfor$1,?whichwillbeaverydifficulttechnologytodisplace.

消費產(chǎn)品及其未來的市場已經(jīng)成為半導體的主要終端市