NVIDIA Jetson Xavier NX Design Guide原版完整文件

NVIDIA」etsonXavierDesignDG-09693-001_v0.91IFebruaryPRELIMINARYPRELIMINARYPRELIMINARYNVIDIAJetsonXavie「DG-09693-001_v091ITableofChapter Chapter JetsonXavier Chapter Chapter Chapter Chapter Chapter Chapter Miscellaneous 12CDesign Chapter Schmitt丁「igger Chapter UnusedInterface UnusedMulti-purposeStandardCMOSPad UnusedDedicatedSpecialPurposePad Chapter Design Chapter JetsonXavierNXPin Chapter GeneralRouting SignalName RoutingGuidelineFo「 SignalRouting Routing GeneralPCBRouting CommonHigh-Speedlnte「faceRequi「 ListListofPRELIMINARYPRELIMINARYNVIDIAJetsonXavie「DG-09693-001_v091I巨gure3-2.巨gure3-4.巨gure4-巨gure4-巨gure4-巨gure4-巨gure4-巨gure4-巨gure4-巨gure4-巨gure4-9.巨gure4-巨gure5-1.巨gure5-巨gure5-巨gure5-巨gure5-巨gure5-6.曰gure5-巨gure5-10.巨gure5-巨gure5-巨gure5-巨gure5-巨gure5-16.巨gure5-18.巨gure5-

JetsonXavie「NXBlock SystemPowerandControlBlock Powe「UpSequence[NoPowe「Button-AutoPowe「 PowerDown[SuddenPower USBConnection IL/NEXTPlot IL/NEXTPlot Via Component Component ESDLayout PCleRootPortConnections PCleEndpointConnections Connector JetsonXavie「NXEthernet DPandeDPConnection eDPandDPDifferentialMainLink丁 S-Parameter[upto S-Parameter[upto ViaTopology ViaTopology HDMIConnection HDMIClkandData·l 言勹二。。二勹＿—;: ::::::::::::::::::::::::::::::::::::::: SMTPadTrace SM丁Pad丁「ace PRELIMINARYPRELIMINARYNVIDIAJetsonXavie「DG-09693-001_v091I巨gure6-巨gure6-巨gure6-Figu「e7-1.巨gure9-巨gure9-巨gure9-巨gure9-巨gure9-巨gure9-巨gure14-1.巨gure14-

4LaneCSICameraConnection AvailableCameraControl CSIConnection SDCa「dConnection AudioCodecConnection SPI BasicSPIMasterandSlave SPITopolog JetsonXavierNXUAR丁 」etsonXavie「NXCAN 」etsonXavierNXFan DebugUAR丁Connect GeneralPCBRouting CommonMode ListListofDG-09693-001_v091ITable1- Abb「eviationsand Table2- JetsonXavierNX Table2-2.」etsonXavierNXConnecto「[260-PinSO-DIMM]PinOutMat「 Table3- JetsonXavierNXPowe「andSystemPin Table4- JetsonXavie「NXUSB2.0Pin Table4- JetsonXavie「NXUSB3.1andPClePin Table4-3.」etsonXav呵NXUSB3.10andPCleLaneMapping Table4- USB2.0InterfaceSignalRouting Table4- Table4- XavierUSB2.0Signal Table4- MiscellaneousUSB2.0Signal Table4- XavierUSB3.1Signal Table4- PCleInterfaceSignalRoutingRequirements[to Table4- Table4- JetsonXavie「NXGigabitEthernetPin Table4- EthernetMDIlnte「faceSignalRouting Table4- EthernetSignalC Table5- JetsonXavie「NXeDPandDPPin Table5- DPandHDMIPin Table5- ePDandDPMainLinkSignalRequirementsIncludingDP— Table5- eDPandDPSignal Table5- HDMIlnte「faceSignalRoutingRequi「 Table5- HDMISignal Table6- JetsonXavie「NXCSIPinDesc「 Table6-2.」etsonXavie「NXCame「aMiscellaneousPinDesc「|pt Table6- CSIConfigu「 Table6- MIPICSIlnte「faceSignalRouting Table6- MIPICSISignalC Table6- MiscellaneousCamera Table7- JetsonXavierNXSDIOPin Table7- SDCardandSDIOInterfaceSignalRouting Table7- SDCardandSDIOSignal Table8-1.」etsonXavie「NXAudioPin Table8- 12SInterfaceSignalRouting Table8- AudioSignal Table9- JetsonXavie「NX12CPinDesc「|pt Table9- 12CInterfaceSignalRouting PRELIMINARYPRELIMINARYNVIDIAJetsonXavie「DG-09693-001_v091ITable9- 12CSignalCon Table9- JetsonXavie「NXSPIPinDesc「|pt Table9- Table9- SPI Table9-7.」etsonXavie「NXUAR丁PinDesc「 Table9- UARTSignal Table9-9.」etsonXavie「NXCANPin Table9- CANlnte「faceSignalRouting Table9- CANSignalC Table9- JetsonXavie「NXFanPinDesc「 Table9-13」etsonXavie「NXDebugUAR丁PinDesc「 Table9- DebugUAR丁Connect Table10- PinsPulledorDrivenHighbyXavierPriortoSYS—REST* Table10- Table11- UnusedMPIOPinsandPin Table12- Table13- JetsonXavierNXConnectorPinDesc「|ptions-Odd Table13- JetsonXavie「NXConnectorPinDesc「|ptions-Even Table14- Signal丁ype Table14- CommonHigh-SpeedInterface ??????????EmbeddedElectrostaticEmbeddedElectromagneticlnterfe「GeneralPurposeInputHighDef1n1t1onMult1med1aInterICInterICSoundLowDropout[voltage「egulatoLowPowe「DoubleDataRateDRAM,FourthMedium-Dependentlnte「1/100DthofanMobileIndustryProcessorlnte「PCPulseCodePhysicalInterface[1eUSBSPSCmodula「connecto「used1nEthernetandothe「dataRealTimeSecu「eD1g1tal1/0Single-SerialPeripheral甘ans1t1on-m1n1m1zedd1ffe「ent1alUn1ve「salSe「|al DG-09693-001_v091I????????JetsonXavierJetsonXavierQSPINOR32MBPMICCPU/GPU&CorePower&VoltageCAMMCLKCSI:3x4or6HPD2x,I2C3x–I2C1x–CANUARTSPIPCIex1+SDUSB3.1USB2.0 AUDIOI2S ModuleSignalPinPinModuleSignalModuleSignalPinPinModuleSignal123456789!??Signalformoduleon/off:highlevelon,lowleveloff.ConnectstomodulePMICEN0throughconverterlogic.POWER_ENisroutedtoaSchmitttriggerbufferonthemodule.A100k?pulldownisalsoonthe??z1(PMICGPIO432KCLKOut)Sleep/SuspendSleep/suspendclockfordevicessuchasM.2KeyECMOS–?? CarrierEN ModuleCarrierBoardTT<T>T>T<????? ?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z0z?0?0?z?z?z?z0z?0?0z?z?z?z?zXavierLaneLaneLaneLaneLaneLaneUSB11x4+PCIe0lanePCIe0lanePCIe0lanePCIe0lanePCIe1lanePortPCIex4connectorordevice(I.E.M.2Keydevice(i.e.M.2KeyUSBdeviceorDDGSAvailableforconnector,device,Hub(i.e.M.2KeyE)Load # USBUSB& DataRate/UI 5.0/Gbps/DevicemodesupportsGEN1speed10.0/MaxNumberof190ΩOn-dieterminationatTX&ElectricalInsertionLoss(IL-GEN1(Type@GEN1(Type@@GEN1(Micro≤@ResonanceDip>Theresonancedipcouldbecausedbyaviastubfortransitionortracestubforco- Ω@Tr=200ps(10%-@Tr=61ps(10%-NearEndCrosstalk≤DC–5GHzpereachTX-RXTrace Diffpair/Single85/Ω±15%.IntrinsicZdf,doesnotaccountforcouplingfromtraceReferenceTraceTracelosscharacteristic @2.5GHz(seeFigure4-@5GHz(SeeFigure4-Thefollowingmaxlengthisderivedbasedonthischaracteristic.Thelengthconstraintmustbere-definediflosscharacteristicisBreakoutRegion–Max 3MinimumtracewidthandMaxTraceLength GEN1ormmMaxTraceLength GEN151mmMaxIntra-PairSkew(RX/TX_Nto0.15mmDonotperformlengthmatchingwithinbreakoutregion.lengthmatchingshouldbedonebeforediscontinuities.See26.29mmTraceSpacingforTX/RXTraceSpacing(Microstrip/ Pair-ToRefplaneandSMTTounrelatedhigh-speed4x/4x/4x/DielectricTraceSpacingforTX/RXNon-TX-RXXtalkisverycriticalinPCBtracerouting.TheidealsolutionistorouteTXandRXondifferentIfroutingonthesamelayer,stronglyrecommendnotinterleavingTXandRXIfhavetohaveinterleavingroutinginbreakout,alltheinter-pairspacingshouldfollowtheruleofinter-SNEXT(betweenTX/RXpairThebreakouttracewidthissuggestedtobetheminimumtoincreaseinter-pairDonotperformserpentineroutingforintra-pairskewcompensationinthebreakoutMinInter- Main-DielectricThisistherecommendeddimensionsformeetingtheStriplinestructureinaGSSGstructureisassumed(holdsinbroadside-coupledstriplinestructure)Max Main-MaxtracelengthViaproximity(SignalviatoGNDreturn<3.8mmSeeNoteY-patternisKeepY-patternhelpswithXtalksuppression.Itcanalsoreducelimitofthepair-pairdistance.Reviewneeded(NEXT/FEXTcheck)ifviaplacementdoesnotuseY-pattern.SeeFigureGNDPlaceGNDviaassymmetricallyaspossibletodatapairvias.Upto4signalvias(2pairs)canshareasingleGNDreturnGNDviaisusedtomaintainreturnpath,whileitsXtalksuppressionislimitedMax#of PTHMicro4ifallviasarePTHNotlimitedaslongastotalchannellossmeetsILMaxViaStublongviastubrequiresreview(ILandresonancedipChip?ACcapacitor(TXonly)?commonmodechoke?ESD?SeeFigure4-SeeFigure4-AC 0.075/OnlyrequiredforTXpairwhenroutedtoLocation(maxlengthtoadjacent8Discontinuityisconnector,via,orcomponentGND/PWRvoidunder/abovecapisVoidingisrequiredifACcapsizeis0603orMaxJunctioncapacitance(IOtoe.g.SEMTECHPadshouldbeonthenet–nottraceSeeFigure4-Location(maxlengthtoadjacent8Discontinuityisconnector,via,orcomponentCommon-modeChoke(Notrecommended–onlyusedifabsolutelyrequiredforEMIissues).SeeAppendixAfordetailsonCMCifFPC(AdditionallengthofFlexiblePrintedCircuitTheFPCroutingshouldbeincludedforPCBtracecalculations(maxlength,CharacteristicSameasLossStronglyrecommendbeingthesamethePCBorIfworsethanPCB,thePCBandFPClengthmustbeSMTConnectorGNDGNDplaneundersignalpadshouldbevoided.SizeofvoidshouldbethesamesizeastheConnectorusedmustbeUSB-IFGeneral:SeeChapter14forguidelinesrelatedtoserpentinerouting,routingovervoidsandnoiseUSBUSBandDG-09693-001_v091IFigu「e4- Via一Figu「e4- ComponentOrde Figure4- ComponentFigu「e4- ouCommonUSBRoutingIfroutingtoUSBdeviceorUSBconnectorincludesaflexor2ndPCB,thetotalroutingincludingallPCBs/flexesmustbeusedforthemaxtraceandskewcalculationsKeepc「|ticalUSBrelatedt「acesawayfromothersignaltracesorunrelatedpowertraces/a「easorpowe「supplycomponentsTable4- XavierUSB2.0SignalModuleBallTe「Ifused,90[)common-modechokesclosetoconnecto「ESDP「otect1onbetweenchokeandconnectoroneachlinetoUSBD1ffe「ent1alDataPa|「Connecthubo「anothe「deviceonthePCBTable4- MiscellaneousUSB2.0SignalModulePin Te「AUSBOVBUSEnableConnecttoVBUSpinofUSBconnecto「「ece1v1ngUSBO_+/-interfacethroughlevelshifterAlsoconnectstoVBUSpowersupply1fhostmodeTable4- XavierUSB3.1SignalModulePinTe「USBSS_ [USB31Port「equ1「ConnecttoUSB31connectors,hubsordevicesonthe [USB31PortIfroutedd1「ectlytocapsa「eneededfo「thepe「|phe「alTXlinesESDprotectionnearconnector1f「equ1「DataPa叮sConnecttoUSB31connecto「s,hubso「othe「devicesonthePCB SoC-

SeeNote

PCIe0LanePCIe0LanePCIe0LanePCIe0Lane

PCIe0(Ctrl#5)PCIex4(i.e.M.2Key

SeeNote

PCIe1Lane

PCIe0(Ctrl#4)PCIex1conn/device(i.e.M.2KeyE)

PCIe1(Ctrl#4)PCIex1(i.e.M.2KeySharedwakepinPCIe0(Ctrl#5)–PCIex4

NVHS0_REFCLK/PMux

(i.e.M.2KeySoC-SeeSoC-SeeNoteSeeNotePCIE0_TX3_N Mux NVHS0_REFCLK/PMuxPCIe0(Ctrl DataRate/UI8.0/Gbps/4.0GHz,half-rateConfiguration/Device1ΩToGNDSingleEndedforP&Trace differential/Single85/Ω±15%.SeeNoteReferenceTraceSpacing Pair–ToplaneandcapacitorTounrelatedhigh-speed3x/3x/3x/TXandRXshouldnotberoutedonthelayer.SeeNoteBreakoutregion(MaxMinimumwidthandspacing.4xordielectricheightspacingisMaxtraceToPCIeConnector DirecttoPCIe 5.55.599inAssumptionusedis178ps/inforStriplineand150ps/inforMaxPCBviadistancefromtheMaxdistancefromBGAballtofirstPCBPCBwithinpair(intra-pair)0.075mmDotracelengthmatchingbeforeWithinpair(intra-pair)matching0.075mmDifferentialpairuncoupledViaPlaceGNDviasassymmetricallyaspossibletodatapairvias.GNDviadistanceshouldbelessthan1xthediffpairviaMax#of PTHMicro-2forTXtracesand2forRXNoMaxViastubLongerviastubswouldrequireRoutingsignalsoverNotAC GEN3:0.075/0.176/0.1uFor0.22uFrecommendedforGEN1or0.22uFrecommendedforGEN3.OnlyrequiredforTXpairwhenroutedtoconnectorLocation(maxlengthtoadjacent8Discontinuitysuchasedgefinger,componentVoidingtheplanedirectlyunderthepad3-4milslargerthanthepadsizeisSeeFigure4-VoidingtheplanedirectlyunderthepadmilslargerthanthepadsizeisSeeFigure4-General:SeeChapter14forguidelinesrelatedtoserpentinerouting,routingovervoidsandnoise ModulePinPCIeInterface0(x4–ControllerDIFFSeries0.22uFDifferentialTransmitDataPairs:ConnecttoTX_N/PpinsofPCIeconnectororRX_N/PpinofPCIedevicethroughACcapaccordingtosupportedconfiguration.DIFFSeries0.22uFcapacitorsJetsonXavierNXpinsordeviceifdeviceonmainPCB.DifferentialReceiveDataPairs:ConnecttoRX_N/PpinsofconnectororTX_N/PpinofPCIedevicethroughACcapaccordingtosupportedconfiguration.DIFFIN(Endpoint)DifferentialReferenceClockOutput:ConnectedtoamuxonthemodulethatselectseitherPEX_CLK5orNVHS0_REFCLK.ConnecttoREFCLK_N/PpinsofPCIedevice/connector.ForRootPortoperation,setthemuxtoselectPEX_CLK3(CAN0_EN=0).ForEndpoint,setthemuxtoselectNVHS0_REFCLK(CAN_EN=1).I/O(RootI47kΩpull-upVDD_3V3_SYSonPCIeClockRequestforPCIE0_CLK:ConnecttoCLKREQpinsO(RootI4.7kΩpull-upVDD_3V3_SYSonPCIeReset:ConnecttoPERSTpinsonPCIeInterface1(x1–ControllerDIFFSeries0.22uFDifferentialTransmitDataPair:ConnecttoTX_N/PpinsofPCIeconnectororRX_N/PpinofPCIedevicethroughACcapaccordingtosupportedDIFFSeries0.22uFcapacitorsnearJetsonXavierNXpinsordeviceifdeviceonmainPCB.DifferentialReceiveDataPair:ConnecttoRX_N/PpinsofPCIeconnectororTX_N/PpinofPCIedevicethroughACcapaccordingtosupportedconfiguration.DIFFDifferentialReferenceClockOutput:ConnecttoREFCLK_N/PofPCIe47kΩpull-upVDD_3V3_SYSonPCIeClockRequestforPCIE1_CLK:ConnecttoCLKREQpinsO4.7kΩpull-upVDD_3V3_SYSonPCIeReset:ConnecttoPERSTpinsonI100kΩpull-upVDD_3V3_SYSonPCIeWake:ConnecttoWAKEpinsondeviceor????????????????????ENETPHY_INTPlaceresistors&capacitoraroundchassisGNDshape

(J8)TXD3-(J5)TXD2-(J2)TXD0-

0.1u ConnecttoMagneticsConnecttogreenLEDcathodeonRJ45connector.AnodeconnectedtoVDD_3V3_SYSConnecttoyellowLEDcathodeonRJ45connector.AnodeconnectedtoVDD_3V3_SYS?z?z?z?z?z?z?z?zzz?z?z?z?z?z?z?z?zzSoC–SoC–Level . 13HDMI987654321 CommonChokes&PN PRELIMINARYPRELIMINARYNVIDIAJetsonXavie「DG-09693-001_v091ITracelosscharacteristic Upto00dB/in舊27GHzdB/in@/4OGthischaracteristicSeeNote2MaxPCBviadistfromconnecto「NoreqummTXtoconnectorUptoHBR2[St「|pl1ne/M1c「ost「|plHBR3[Stripline/Mmm175ps/1nchassumpt1onforstripl1ne,150ps/1nchform1crostr1pTracespacing[pair-pair] M1crostr1pM1crostr1pTracespacing [MainlinktoAUX]3xIMaxintra-pair[with1npa葉o1s11mmSeeNoteSeeNoteMaxGNDtrans1t1onvia<1d1ffpairsymmetricalGNDst1tch1ngvianearsignalViaImpedancedipRecommendedviad1mens1on for1mpedancecontrol Ant1pad[miniViapitch[mini(l＠35pskeepsymmetryY-patternhelpsw1thXtalksuppressionItcanalsoreducethel1m1tofpair-pairdistanceNeed「ev1ew[NEXT/FEXTcheck1fviaplacement1snotY-patternSeeeDP/DPgu1del1neFigure5-5For1n-l1nevia,thedistancefromaviaofonelanetotheadjacentviafromanotherlane>=12mmcenter-centerSeeeDP/DPgu1del1neF1gu「e5-PlaceGNDv1aassymmetricallyaspossibletodatapa|「v1asUptofourGNDreturnviawhileitsXtalksuppression1sl1m1ted PTHMic「o21fallv1asarePTHNotl1m1tedaslongastotalchannellossmeetsILspec0AC0 to Norequ0Vo心 Vo心ng「pad3-4m1lslargerthanthepadsize1sConnectoVo心 Norequ1rementHBR2:StandardDPconnectorVo心ngrequirement1sstack-updependentFortypicalstack-ups,vo心ngonthelayerundertheconnectorpad1srequiredtobe57millargerthantheconnecto「padGeneral:SeeChapter14forgu1del1nesrelatedtoSerpentinerouting,routingovervoidsandnrnseForeDP/DP,thespecputsahighe「P「IO「|tyonthetracelosscharacte「isticthanontheimpedance.Howeve「,beforeselecting850forimpedance,itisimportanttomakesuretheselectedstack-up,materialandtracedimensioncanachievetheneededlowlossLongertracelengthsmaybepossibleifthetotaltracelossisequaltoorbette「thantheta「get.Ifthelossisgreate「themaxtracelengthswillneedtobereducedDonotperformlengthmatchingwithinbreakoutregion.Recommenddoingtracelengthmatchingto<1psbeforev1asor蘆continuitytominimizecommonmodeconve「/4_TheaverageofthedifferentialsignalsisusedforlengthThefollowingfiguresshowtheeDPandDPinterfacesignalroutingFigure5- S-Parameter(upto。-----窀.Ei-『-『---

S-parmneter Freq.Figu「e5- S-Paramete「(upto050050505050505050505051234567891Freq.1Figure5- ViaTopologyFigure5- ViaTopology.-2i.-2iliii-- ModuleModulePinTe「Desc「DPx_TXD[3Se「|esO1uFcapac1to「sandESDtoGNDoneDP/DPDifferentialCLK/DataLanes:ConnecttomatchingpinsondisplayconnectorDSeriesO1uFcapacitors1OOk(lpulldownDPO_AUX_Pand100kDpull-uptoVDD_3V3_SYSonDPO_AUX_NES□toGNDonbothondisplayconnector|Frommodulepin1Ok(lpull-upto18V,levelshifterand100k0pulldown,100k0se「|esresistoronconnectorsideofshifter,andeDP/DP:HotPlugDetect:ConnecttoHPDpinondisplayconnectorthroughlevelshifterAstandardDP1.2aorHDMIV2.0inte「faceissuppo「ted.SeeFigure5-7fo「moreLoadLoadSoC–LevelLevelTypeDDC/CECLevel(seenote)98R7654321LoadGS Chokes&(SeeNoteMainRoute–SegA--Seg*NoteSeg*NoteSeg*NoteSeg*Note100?SegSeeNotePCBPCBChokeor SeeNoteMaxfrequency/5.94/Gbps/Perlane–nottotallink AtΩDifferentialTo3.3VatOn-ToGNDnearElectrical<=dB@<=dB@<=dB@<dB@resonancedip>TDR>=Ω@10%-90%.IfTDRdipis75~85ohmthatdipshould<FEXT<=-dBatPSNEXTisderivedfromanalgebraicsummationof<=-dBatindividualNEXTeffectsoneachpairbytheother<=-dBatIL/FEXTplot:SeeHDMIGuidelineFigure5-TDRplot:SeeFigure5-Trace DiffΩ±10%.Targetis100Ω.ΩforthebreakoutandrouteisanimplementationReferenceTraceTraceloss<<dB/in.@dB/in.@ThemaxlengthisderivedbasedonthisSeeNoteTracespacing(pair-Microstrip:preMicrostrip:5xtoForStripline,thisis3xofthethinnerofaboveandTrace (Mainlinkto ForStripline,thisis3xofthethinnerofaboveMaxtotallength/delay(1.4b/2.0-upto5.94Gbps)Microstrip(5xspacing)Microstrip(7x63.5/2.550.8/2.063.5/2.5mm/inPropagationdelay:175ps/in.forstripline,150ps/in.forMaxTotalLength/Delay(Pre-1.4b)(upto 225/8.5mm/inPropagationdelay:175ps/in.forstripline,150ps/in.forMaxintra-pair(withinpair)0.15mmSeenotes1,2,andMaxinter-pair(pairtopair)Seenotes1,2,andMaxGNDtransitionviaDiffpairviaForsignalsswitchingreferencelayers,addoneortwogroundstitchingvias.ItisrecommendedtheybesymmetricaltosignalY-patterniskeepXtalksuppressionisthebestbyY-pattern.Alsoitcanreducethelimitofpair-pairdistance.Needreview(NEXT/FEXTcheck)ifviaplacementisnotY-pattern.SeeFigure5-11MinimumimpedanceRecommendedviaviaGNDPlaceGNDviaassymmetricallyaspossibletodatavias.Uptofoursignalvias(2diffpairs)cansharesingleGNDreturnGNDviaisusedtomaintainreturnpath,whileitssuppressionisMax#of PTH4ifallviasarePTHNotlimitedaslongastotalchannellossmeetsILMaxviastublongviastubrequiresreview(ILandresonanceThemainrouteviadimensionsshouldcomplywiththeviastructurerules(SeeviaSeetopologyinFigure5-Fortheconnectorpinvias,followtherulesfortheconnectorpinvias(SeeviaThetracesaftermainrouteviashouldberoutedas100?differentialorasuncoupledSEtracesonPCBtoporMaxdistancefromRPDtomaintrace(segB)1MaxdistancefromACcaptoMaxdistancebetweenESDsignal3ExampleofacasewherespacelimitedforplacingTop:SeeFigure5-Bottom:SeeFigure5-ACMaxviadistancefrom7.62mmmustbeplacedbeforepull-downThedistancebetweentheACcapandthe PTHMicro-viaPlacecaponbottomlayerifmainrouteabovePlacecapontoplayerifmainroutebelowNotGND(orPWR)voidunder/abovethecapisVoidsize=SMTarea+1xdielectricheightkeepoutSeeFigure5-Pull-downResistor(RPD),ΩMustbeplacedafterACPlacement:SeeFigure5-LayerofSamelayerasACcap.TheFETandchokecanbeontheoppositelayerthruaPTHChokebetweenRPDandFETMaxtraceRdcMaxtrace1CanbechokeorTrace.RecommendedoptionHDMI2.0HF1-9GND/PWRvoidunder/abovecapisCommon-modeChoke(Notrecommended–onlyusedifabsolutelyrequiredforEMISeeChapter14fordetailsonCMCifESD(On-chipprotectiondiodecanwithstand2kVHMM.ExternalESDisoptional.DesignsshouldincludeESDfootprintasastuffing(IOtoe.g.TexasInstrumentsPadrightonthenetinsteadoftraceSeeFigure5-Afterpull-downresistor/CMCandbeforeGND/PWRvoidunder/abovethecapisneeded.size=1mmx2mmfor1SeeFigure5-SeriesResistor(RS)–SeriesresistoronN/PpathforHDMI2.0≤?±10%.0ohmisacceptableifthedesignpassestheHDMI2.0HF1-9test.Otherwise,adjusttheRSvaluetoensuretheHDMI2.0testspass:Eyediagram,VlowtestandHF1-9TDRAfterallcomponentsandbeforeHDMIGND/PWRvoidunder/abovetheRSdeviceisneeded.Voidsize=SMTarea+1xdielectricheightkeepoutTraceatComponent?±AtcomponentregionTraceenteringtheSMTOneSeeFigure5-TracebetweenSeeFigure5-HDMIVoidingthegroundbelowthesignal0.1448(5.7mil)largerthanthepinSeeFigure5-General:SeeChapter14forguidelinesrelatedtoSerpentinerouting,routingovervoidsandnoisePRELIMINARYPRELIMINARYNVIDIAJetsonXavie「DG-09693-001_v091IThefollowingfiguresshowtheHDMIinte「facesignal「outing「Figure5- IL/FEXT 01002OO31104005006007OOOOO90moon1”“2OO'10040”50n60”1OOOOO90己．妒Figure5- HOMIVia? Add-OnComponents-)f_t\)f_t\寸)f)f,VJ/干Figure5- ACCap RPO/Choke,FET100ohrn點：團(tuán)機

.,-l·LMain-route PTHviatoconnectwithshortstub (andoptionalchoke)onoppositesideFigu「e5- ESDFigu「e5- Figu「e5- SMTPadTraceFigu「e5- SMTPadT「aceFigu「e5- Connector ModulePinTe「mination[seenoteonDesc「D01uFseriesACcAP5000RP□[controlledbyFETIES□toGND吐ClRs[seriesresistor]HDMIDifferentialClock:Connectto/C+andpinsonHDMIHDMIDifferentialData:ConnecttoHDMIDatapins[SeeTable5-21|Frommodulepin10k0PUto1SVlevels同100kCJseriesresistor100kCJtoGNDonconnectorside100pF/12pFcapstoGNDES□toHDMIHotPlugDetect:ConnecttopinonHDMIGatingc|「cu1try,SeeconnectionfigureforHDMIConsumerElectronicsConnecttoCEConHDMIconnectorthroughc1「cu1tryDFrommodulepins1OkOPUto33Vlevelsh1/terPUo5VES□toGNDHDMI:DDCInterface-ClockandConnectDP1_AUX_NtoSDAandDP1_AUX_PtoSCLonHDlv1IconnectarHDMI5VpAdequatedecoupl1ng[O1uFand1OuFrecommended]onsupplynearconnectarandES□toHDMI5Vsupplytoconnector:Connectto+5VonHDMIconnector.Note:AnyES□and/orEMIsolutionsmustsupporttargetedmodes[f「?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?z?zzz4-lane CSI5(DSI2-Lanes1of6√2of6√√3of6√4of6√√5of6√6of6√4-Lanes1of3√√2of3√√3of3√√Camera0Camera1 46935

Camera1OnlyCSI0Camera2OnlyCSI2 1/1.5/2.5MIPICSIVideoTable6- MiscellaneousCameraModuleModulePin。22kClpull-upsVDD_3V3_SYS[onJetsonXavierNXICamera12CInterface:Connectto12CSCLandSDAp1nsofTheCAM_l2Cinterface1sconnectedtothepowermon1to「deviceonthemodulewhichuses12Caddress7'h40CAM[1GPI001[optGPIO11[optCameraMasterClocks:ConnecttocamerareferenceclockCAM[lCameraPowerControlsignals(orGPIOs[1:0ll:Connecttopowe「downpinsoncamera[s]。PRELIMINARYNVIDIAJetsonXavie「 DG-09693-001_v091I0.1uD0.1uFGSSee to pinof pinof pinsof2.2uF0.1u2.2uF0.1u

AudioCodec

10uF10uF10uF0.1uF

GPIO(seenoteI2S0or

10uF0.1u

GPIO2/BCLK2/GPIO3/PDM_SCLDACDAT2/GPIO5_DMIC1_SCL

AudioPanel

I2C(seenote

IN2P/INL/DMIC2_SDA/

25

4.7uF4.7uF0.1uF4.7u

25Table8- 12SInterfaceSignalRoutingConf1guration/deviceorgan1Max8ReferenceBreakoutregionMin。Trace士Viaprox1m1ty[signalto<38mmSeenoteTrace M1crostriporSt「InSeenote~16InSeenoteNote:UptofoursignalviascanshareasingleGNDreturnTable8- AudioSignalModulePin12S1112S[1125FrameSelectLeft/RightClock):Connecttoco「respondingpinofaudio125[1DataOutput:Connecttodatainputpinofaudio12S[1|DataInput:Connecttodataoutputpinofaudio DG-09693-001_v091Izzzzzz On-On-SoC–Max Standard-mode/Fm/100/400/SeeNoteMax Standard-mode/Fm/TotalofallReferenceGNDorTrace50–ΩTraceMaxtrace StandardFm,Fm+34001700ps2.2k?pull-upstoVDD_3V3_SYSonXavierI2C#0ClockandData.ConnecttoCLKandDatapinsofany3.3V2.2k?pull-upstoVDD_3V3_SYSonXavierI2C#1ClockandData.ConnecttoCLKandDatapinsof3.3V2.2k?pull-upstoVDD_1V8onXavierI2C#2ClockandData.ConnecttoCLKandDatapinsofany1.8V2.2k?pull-upstoVDD_3V3_SYSonXavierCameraI2CClockandData.ConnecttoCLKandDatapinsofanyzzSoC–devices(separateCSforeach)JetsonJetsonSPISlaveMOSI(Masterout,SlaveMISO(Masterin,SlaveJetsonSPIMasterMOSI(Masterout,SlaveMISO(Masterin,Slave Branch-MainBranch- Branch-MainBranch- MainMainBranch-MainBranch-MaxConfiguration/device4Maxloading(totalofallReferenceBreakoutregionMinimumwidthandMaxPCBbreakoutTrace50–ΩViaproximity(signalto<3.8mmSeeNoteTrace Microstrip/4x/Maxtracelength/delay(PCBmain ForMOSI,MISO,SCKand 2x-loadmm 2x-loadforMOSI,MISO,SCKand75mmMaxtracelength/delayskewfromMOSI,MISOandCSto16mmAtanyModulePinNamesGPIO03SPIClock.:ConnecttoperipheralCLKGPIO05SPIDataOutput:ConnecttoslaveperipheralMOSIGPIO04SPIDataInput:ConnecttoslaveperipheralMISOGPIO06SPIChipSelects.:ConnectoneCSx*pinperSPIinterfacetoeachslaveCSpinonthezSoC–UART MaxDataRate/1Mbps/1ReferenceTraceΩViaproximity(SignalviatoGNDreturn<3.8mmSeeNoteTrace Microstrip/4x/MaxTraceLength(forRX&TXmmSeeNoteMaxTraceLength/DelaySkewfromRXto8mmSeeNote ?? SoC–SoC–

D

S

10uF

12

DGS

S LevelChapter10.JetsonXavie「NXsignalsthatcomefromtheSoCmayglitchwhentheassociatedpowerrail1senabled.ThismayaffectpinsthatareusedasGPIOoutputs.Designersshouldtakethisintoaccount.GPIOoutputsthatmustmaintainalowstateevenwhilethepowerra仆isbeingrampedupmayrequirespecialhandlingInternalPull-upsforDualVoltageBlockPinsPowerat1.8VSeveraloftheMPIOpadsareonblocksdesignedtobepoweredateither1.8Vor3.3V丁heseblocksa「epowe「edat1.BVonJetsonXavie「NXandtheinternalpull-upatinitialPowe「-ONISnoteffective丁hesignalmayonlybepulledupafractionofthe1.BV國il.Oncethesystemboots,softwa「ecanconfigurethepinsfo「1.8Voperationandtheinternalpull-upswillwo「kcorrectly.Ifthesesignalsneedthepull-upsduringPowe「-ON,externalpull-up飛sisto「Sshouldbeadded.丁hefollowingpinslistedaretheaffectedpins.ThesearetheJetsonXav1e「NXpinsonthedualvoltageblockspowe「edat1.8VwithPower-ONresetdefaultofInternalpull-upenabled.?SDMMC—DA丁?SDMMC—DA丁?SDMMC—?SDMMC—DA丁?SDMMC—?SPI1—?SPl1SchmittTriggerTheMPIOpinshaveanoptiontoenableordisableSchmitt-triggermodeonaper-pinbasisThismodeisrecommendedforpinsusedforedge-sensitivefunctionssuchasinputclocks,orotherfunctionswhereeachedgedetectedwillaffecttheoperationofadevice.Schmitt-triggermodep「ovidesbetternois