KK74ACT258D中文資料

1、KK74ACT258D中文資料TECHNICAL DATA KK 74ACT258 Quad 2-Input Data Selector/Multiplexer with 3-State OutputsHigh-Speed Silicon-Gate CMOS The KK HC/HCT258. The KK 74ACT258 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.This device selects a (4-bit) nibble from

2、 either the A or B inputs as determined by the Select input. The nibble is presented at the outputs in inverted from when the Output Enable pin is at a low level. A high level on the Output Enable pin switches the outputs into the high-impedancestate.? TTL/NMOS Compatible Input Levels? Outputs Direc

3、tly Interface to CMOS, NMOS, and TTL? Operating Voltage Range: 4.5 to 5.5 V? Low Input Current: 1.0 A; 0.1 A 25C ? Outputs Source/Sink 24 mAFUNCTION TABLEX=dont careZ = high-impedance stateA0-A3,B0-B3=the levels of the respective Nibble InputsPIN ASSIGNMENTLOGIC DIAGRAM PIN 16 =V CCPIN 8 = GND MAXIM

4、UM RATINGS*Symbol Parameter ValueUnit V CC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 VV IN DC Input Voltage (Referenced to GND) -0.5 to V CC +0.5 VV OUT DC Output Voltage (Referenced to GND) -0.5 to V CC +0.5 VI IN DC Input Current, per Pin 20 mAI OUT DC Output Sink/Source Current, per Pin

5、50 mAI CC DC Supply Current, V CC and GND Pins 50 mAP D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750500mWTstg Storage Temperature -65 to +150 CT L Lead Temperature, 1 mm from Case for 10 Seconds(Plastic DIP or SOIC Package)260 C*Maximum Ratings are those values beyond which damage

6、to the device may occur.Functional operation should be restricted to the Recommended Operating Conditions.+Derating - Plastic DIP: - 10 mW/C from 65 to 125CSOIC Package: : - 7 mW/C from 65 to 125CRECOMMENDED OPERATING CONDITIONSSymbol Parameter MinMaxUnit V CC DC Supply Voltage (Referenced to GND) 4

7、.5 5.5 VV IN, V OUT DC Input Voltage, Output Voltage (Referenced to GND) 0 V CC VT J Junction Temperature (PDIP) 140 CT A Operating Temperature, All Package Types -40 +85 CI OH Output Current - High -24 mAI OL Output Current - Low 24 mAt r, t f Input Rise and Fall Time *(except Schmitt Inputs) V CC

8、=4.5 VV CC =5.5 V 108.0ns/V* VINfrom 0.8 V to 2.0 VThis device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circu

9、it. For proper operation, V IN and V OUT should be constrained to the range GND(V IN or V OUT)V CC.Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)V CC Guara

10、nteed Limits Symbol Parameter TestConditions V25 C -40C to85CUnitV IH Minimum High-Level Input Voltage V OUT=0.1 V or V CC-0.1 V 4.55.52.02.02.02.0VV IL Maximum Low -Level Input Voltage V OUT=0.1 V or V CC-0.1 V 4.55.50.80.80.80.8VV OH Minimum High-Level Output Voltage I OUT -50 A 4.55.54.45.44.45.4

11、V*VIN=V IH or V ILI OH=-24 mAI OH=-24 mA4.55.53.864.863.764.76V OL Maximum Low-Level Output Voltage I OUT 50 A 4.55.50.10.10.10.1V*VIN=V IH or V ILI OL=24 mAI OL=24 mA4.55.50.360.360.440.44I IN Maximum InputLeakage CurrentV IN=V CC or GND 5.50.1 1.0 A?I CCT Additional Max.I CC/InputV IN=V CC - 2.1 V

12、 5.5 1.5 mAI OZ Maximum Three-State LeakageCurrent V IN(OE)= V IH or V ILV IN =V CC or GNDV OUT =V CC or GND5.50.5 5.0 AI OLD+Minimum DynamicOutput CurrentV OLD=1.65 V Max 5.575 mAI OHD+Minimum DynamicOutput CurrentV OHD=3.85 V Min 5.5-75 mAI CC Maximum QuiescentSupply Current(per Package)V IN=V CC

13、or GND 5.58.0 80 A* All outputs loaded; thresholds on input associated with output under test.+Maximum test duration 2.0 ms, one output loaded at a time.AC ELECTRICAL CHARACTERISTICS (V CC=5.0 V 10%, C L=50pF, Input t r=t f=3.0 ns)Guaranteed LimitsSymbol Parameter 25 C -40C to 85C UnitMaxMin Max Min

14、2.0 8.5 1.5 9.5 nst PLH Propagation Delay, Nibble A or B to Output Y(Figure 1)t PHL Propagation Delay, Nibble A or B to Output Y2.0 7.5 1.5 8.0 ns(Figure 1)3.0 10.5 2.0 11.5 nst PLH Propagation Delay, Select to Output Y(Figure 2)1.5 9.5 1.5 11.0 nst PHL Propagation Delay, Select to Output Y(Figure 2)2.0 8.5 1.5 9.5 nst PZH Propagation Delay, Output Enable to Output Y(Figure 3)2.0 8.5 1.5 9.5 nst PZL Propagation Delay, Output Enable to Output Y(Figure 3)1.5 9.0 1.0 10.0 nst PHZ Propagation Delay, Output Enable to Output Y(Figure 3)2.0 8.0 1.5 9.0 nst PLZ Propagation Delay, Output Enable