數(shù)字時(shí)鐘顯示實(shí)驗(yàn)報(bào)告

1、實(shí)驗(yàn)名稱(chēng)：數(shù)字時(shí)鐘設(shè)計(jì)實(shí)驗(yàn)儀器及軟件：計(jì)算機(jī)，quartas。實(shí)驗(yàn)?zāi)康模?全面了解如何應(yīng)用該硬件描述語(yǔ)言進(jìn)行高速集成電路設(shè)計(jì)；2.通過(guò)對(duì)數(shù)字時(shí)鐘軟件設(shè)計(jì)環(huán)節(jié)與仿真環(huán)節(jié)熟悉quartus ii設(shè)計(jì)與仿真環(huán)境；3. 通過(guò)對(duì)數(shù)字時(shí)鐘的設(shè)計(jì)，掌握硬件系統(tǒng)設(shè)計(jì)方法（自底向上或自頂向下），熟悉vhdl語(yǔ)言三種設(shè)計(jì)風(fēng)格，熟悉其芯片硬件實(shí)現(xiàn)的過(guò)程。4 體會(huì)硬件設(shè)計(jì)語(yǔ)言在工程中的重要性。全面掌握設(shè)計(jì)方法和過(guò)程。實(shí)驗(yàn)要求：設(shè)計(jì)一個(gè)數(shù)字時(shí)鐘，并輸出到數(shù)碼管顯示時(shí)，分，秒。實(shí)驗(yàn)原理：a 整體系統(tǒng)實(shí)行自頂下的原則，通過(guò)頂層實(shí)體分別串接各個(gè)設(shè)計(jì)部件，各個(gè)部件接口通過(guò)端口映射的方式進(jìn)行串接，從而達(dá)到設(shè)計(jì)目的。b 整個(gè)程序中

2、涉及的部件有：（1）分頻器，對(duì)輸入時(shí)鐘40mhz進(jìn)行40000000分頻，得到1hz信號(hào)，作為計(jì)數(shù)器的計(jì)數(shù)時(shí)鐘；對(duì)輸入時(shí)鐘40mhz進(jìn)行400000分頻，得到100hz信號(hào)，作為數(shù)碼顯示管位掃描信號(hào)（2）計(jì)數(shù)器，用24進(jìn)制計(jì)數(shù)器作為小時(shí)位的計(jì)數(shù)，用60進(jìn)制計(jì)數(shù)器作為分位，秒位的計(jì)數(shù)。（3）位選程序，實(shí)現(xiàn)六個(gè)數(shù)碼顯示管動(dòng)態(tài)掃描顯示，（4）led顯示程序：用于顯示信號(hào)在數(shù)碼管。（5）頂層模塊實(shí)體部分，指明了輸入輸出端口，各部分的聯(lián)系和鏈接，以及通過(guò)端口映射連接各部分，實(shí)現(xiàn)整個(gè)程序功能。c 關(guān)于動(dòng)態(tài)顯示，掃描頻率設(shè)置為100hz，這個(gè)頻率大于要求的50hz，利用人眼的視覺(jué)暫留效果，則看不到閃爍現(xiàn)象，

3、可以實(shí)現(xiàn)動(dòng)態(tài)顯示功能。d 在計(jì)數(shù)器的時(shí)鐘選擇上，選擇的是1hz頻率，滿足了每秒一次的要求。設(shè)計(jì)思路及vhdl代碼e兩個(gè)模60的計(jì)數(shù)器來(lái)代表時(shí)鐘的秒針，分針，再用一個(gè)模23的計(jì)數(shù)器來(lái)代替時(shí)針。外部基礎(chǔ)時(shí)鐘信號(hào)作為秒針計(jì)數(shù)器的時(shí)鐘信號(hào)，秒針計(jì)數(shù)器的近進(jìn)位信號(hào)作為分針計(jì)數(shù)器的時(shí)鐘信號(hào)，分針計(jì)數(shù)器的進(jìn)位信號(hào)有作為時(shí)針計(jì)數(shù)器的時(shí)鐘信號(hào)，最后在統(tǒng)一輸出。需要注意的是到23時(shí)59分59秒后下次跳動(dòng)清零，從頭開(kāi)始。基礎(chǔ)時(shí)鐘信號(hào)選擇1hz最為簡(jiǎn)單。我們做了以40mhz為基礎(chǔ)時(shí)鐘信號(hào)的時(shí)鐘，主要要點(diǎn)在將40mhz分頻到1hz。下面通過(guò)原理結(jié)構(gòu)圖描述系統(tǒng)m=3計(jì)數(shù)器 數(shù)碼管譯碼器時(shí)鐘信號(hào)進(jìn)位信號(hào)m=10計(jì)數(shù)器 數(shù)碼

4、管譯碼器時(shí)鐘信號(hào)進(jìn)位信號(hào)m=6計(jì)數(shù)器 數(shù)碼管譯碼器進(jìn)位信號(hào)時(shí)鐘信號(hào)m=10計(jì)數(shù)器 數(shù)碼管譯碼器m=10計(jì)數(shù)器 數(shù)碼管譯碼器秒針個(gè)位顯示信號(hào)秒針計(jì)數(shù)器m=6計(jì)數(shù)器 數(shù)碼管譯碼器時(shí)鐘信號(hào)進(jìn)位信號(hào)秒針十位顯示信號(hào)時(shí)鐘信號(hào)進(jìn)位信號(hào)分針個(gè)位顯示信號(hào)分針十位顯示信號(hào)時(shí)針個(gè)位顯示信號(hào)時(shí)針十位顯示信號(hào)分針計(jì)數(shù)器時(shí)針計(jì)數(shù)器s110=s110+1s110=”0101”?時(shí)鐘信號(hào)時(shí)鐘上升沿？s220=”1001”?s220=s220+1s220=”0000”s110=”0000”輸出上升沿脈沖外部基礎(chǔ)時(shí)鐘信號(hào)yny nym110=m110+1m110=”0101”?時(shí)鐘信號(hào)時(shí)鐘上升沿？m220=”1001”?m22

5、0=m220+1m220=”0000”m110=”0000”輸出上升沿脈沖y ny ny秒針計(jì)數(shù)器提供 h110=h110+1h110=”0101”?時(shí)鐘信號(hào)時(shí)鐘上升沿？h220=”1001”?h220=h220+1h220=”0000”h110=”0000”輸出上升沿脈沖分針計(jì)數(shù)器提供y ny ny一，頂層實(shí)體模塊源代碼數(shù)字鐘的頂層模塊程序 clock.vhd library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity clock is

6、port(clk :in std_logic; set :in std_logic; qin_s_1 : in std_logic_vector(3 downto 0); -秒鐘的低位調(diào)整輸入端 qin_s_2 : in std_logic_vector(3 downto 0); -秒鐘的高位調(diào)整輸入端 qin_m_1 : in std_logic_vector(3 downto 0); -分鐘的低位調(diào)整輸入端 qin_m_2 : in std_logic_vector(3 downto 0); -分鐘的高位調(diào)整輸入端 qin_h_1 : in std_logic_vector(3 downt

7、o 0); -時(shí)鐘的低位調(diào)整輸入端 qin_h_2 : in std_logic_vector(3 downto 0); -時(shí)鐘的高位調(diào)整輸入端 qout : out std_logic_vector(6 downto 0); -7段碼輸出 sel : out std_logic_vector(5 downto 0) -位選輸出端 );end clock;architecture behave of clock iscomponent cnt24 is port(clk : in std_logic; set : in std_logic; din1 : in std_logic_vector

8、(3 downto 0); din2 : in std_logic_vector(3 downto 0); qout1 : out std_logic_vector(3 downto 0); qout2 : out std_logic_vector(3 downto 0);end component cnt24;component cnt60 is port(clk : in std_logic; set : in std_logic; din1 : in std_logic_vector(3 downto 0); din2 : in std_logic_vector(3 downto 0);

9、 qout1 : out std_logic_vector(3 downto 0); qout2 : out std_logic_vector(3 downto 0); carry : out std_logic);end component cnt60;component fen1 is port(clk:in std_logic; qout:out std_logic);end component fen1;component fen100 is port(clk:in std_logic; qout:out std_logic);end component fen100;componen

10、t weixuan is port(clk : in std_logic; qin1 : in std_logic_vector(3 downto 0); qin2 : in std_logic_vector(3 downto 0); qin3 : in std_logic_vector(3 downto 0); qin4 : in std_logic_vector(3 downto 0); qin5 : in std_logic_vector(3 downto 0); qin6 : in std_logic_vector(3 downto 0); qout : out std_logic_v

11、ector(3 downto 0); sel : out std_logic_vector(5 downto 0); end component weixuan;component led_driv is port(qin : in std_logic_vector(3 downto 0); qout : out std_logic_vector(6 downto 0);end component led_driv;signal carry1: std_logic;signal carry2: std_logic;signal qout1 : std_logic;signal qout100

12、: std_logic;signal qout_s_1:std_logic_vector(3 downto 0);signal qout_s_2:std_logic_vector(3 downto 0);signal qout_m_1:std_logic_vector(3 downto 0);signal qout_m_2:std_logic_vector(3 downto 0);signal qout_h_1:std_logic_vector(3 downto 0);signal qout_h_2:std_logic_vector(3 downto 0);signal qouti:std_l

13、ogic_vector(3 downto 0);beginu0:fen1 port map(clk=>clk,qout=>qout1);u1:fen100 port map(clk=>clk,qout=>qout100);u2:cnt60 port map(clk=>qout1,set=>set,din1=>qin_s_1,din2=>qin_s_2,qout1=>qout_s_1,qout2=>qout_s_2,carry=>carry1);u3:cnt60 port map(clk=>carry1,set=>se

14、t,din1=>qin_m_1,din2=>qin_m_2,qout1=>qout_m_1,qout2=>qout_m_2,carry=>carry2);u4:cnt24 port map(clk=>carry2,set=>set,din1=>qin_h_1,din2=>qin_h_2,qout1=>qout_h_1,qout2=>qout_h_2);u5:weixuan port map(clk=>qout100,qin1=>qout_s_1,qin2=>qout_s_2,qin3=>qout_m_1,

15、qin4=>qout_m_2,qin5=>qout_h_1,qin6=>qout_h_2,qout=>qouti,sel=>sel);u6:led_driv port map(qin=>qouti,qout=>qout);end behave;這部分實(shí)現(xiàn)的是頂層實(shí)體，它是程序的核心，通過(guò)端口映射把其他各部件程序端口連接為一個(gè)整體，指明系統(tǒng)的輸入端口，輸出端口，輸入型號(hào)，輸出信號(hào)。二，分頻部分1，功 能：對(duì)輸入時(shí)鐘40mhz進(jìn)行40000000分頻，得到1hz信號(hào)接 口：clk -時(shí)鐘輸入 qout-秒輸出信號(hào)library ieee;use ieee.

16、std_logic_1164.all;entity fen1 isport(clk:in std_logic; qout:out std_logic);end fen1;architecture behave of fen1 isconstant counter_len:integer:=10#39999999#;signal cnt:integer range 0 to counter_len;begin process(clk) begin if clk'event and clk='1' then case cnt is when 0 to counter_len

17、/2=>qout<='0' when others =>qout<='1' end case; if cnt=counter_len then cnt<=0; else cnt<=cnt+1; end if; end if; end process;end behave;這部分是用于實(shí)現(xiàn)分頻得到1hz頻率，用于計(jì)數(shù)器的計(jì)數(shù)時(shí)鐘，主要的思路：020mhz為低電平，2040mhz劃為高電平，然后時(shí)間分頻得1hz。2功 能：對(duì)輸入時(shí)鐘40mhz進(jìn)行400000分頻，得到100hz信號(hào)， 作為數(shù)碼顯示管位掃描信號(hào)接 口：clk -時(shí)鐘

18、輸入 qout-100hz輸出信號(hào)library ieee;use ieee.std_logic_1164.all;entity fen100 isport(clk:in std_logic; qout:out std_logic);end fen100;architecture behave of fen100 isconstant counter_len:integer:=10#399999#;signal cnt:integer range 0 to counter_len;begin process(clk) begin if clk'event and clk='1&

19、#39; then case cnt is when 0 to counter_len/2=>qout<='0' when others=>qout<='1' end case; if cnt=counter_len then cnt<=0; else cnt<=cnt+1; end if; end if; end process;end behave;這部分實(shí)現(xiàn)了由40mhz分頻得到100hz頻率，用于動(dòng)態(tài)顯示頻率的產(chǎn)生。三，功 能：實(shí)現(xiàn)六個(gè)數(shù)碼顯示管動(dòng)態(tài)掃描顯示-接 口：clk -時(shí)鐘輸入- qin1-第一個(gè)數(shù)碼顯示管要顯

20、示內(nèi)容輸入- qin2-第二個(gè)數(shù)碼顯示管要顯示內(nèi)容輸入- qin3-第三個(gè)數(shù)碼顯示管要顯示內(nèi)容輸入- qin4-第四個(gè)數(shù)碼顯示管要顯示內(nèi)容輸入- qin5-第五個(gè)數(shù)碼顯示管要顯示內(nèi)容輸入- qin6-第六個(gè)數(shù)碼顯示管要顯示內(nèi)容輸入- sel -位選信號(hào)輸出-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity weixuan isport(clk : in std_logic; qin1 : in std_logic_vector(

21、3 downto 0); qin2 : in std_logic_vector(3 downto 0); qin3 : in std_logic_vector(3 downto 0); qin4 : in std_logic_vector(3 downto 0); qin5 : in std_logic_vector(3 downto 0); qin6 : in std_logic_vector(3 downto 0); qout : out std_logic_vector(3 downto 0); sel : out std_logic_vector(5 downto 0);end wei

22、xuan;architecture behave of weixuan isbegin process(clk) variable cnt:integer range 0 to 5; begin if clk'event and clk='1' then case cnt is when 0=>qout<=qin1; sel<="111110" when 1=>qout<=qin2; sel<="111101" when 2=>qout<=qin3; sel<="11

23、1011" when 3=>qout<=qin4; sel<="110111" when 4=>qout<=qin5; sel<="101111" when 5=>qout<=qin6; sel<="011111" when others=>qout<="0000" sel<="111111" end case; if cnt=5 then cnt:=0; else cnt:=cnt+1; end if; end

24、if; end process;end behave; 這部分程序?qū)崿F(xiàn)的是位選功能，用于動(dòng)態(tài)顯示，調(diào)整秒位，分位，時(shí)位。四，計(jì)數(shù)器的設(shè)計(jì)功 能：24進(jìn)制計(jì)數(shù)器-接 口：clk -時(shí)鐘輸入- set -時(shí)間使能端- din1 -個(gè)位數(shù)據(jù)預(yù)置輸入- din2 -十位數(shù)據(jù)預(yù)置輸入- qout1-個(gè)位bcd輸出- qout2-十位bcd輸出library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity cnt24 is port(clk : in s

25、td_logic; set : in std_logic; din1 : in std_logic_vector(3 downto 0); din2 : in std_logic_vector(3 downto 0); qout1 : out std_logic_vector(3 downto 0); qout2 : out std_logic_vector(3 downto 0);end cnt24;architecture behave of cnt24 issignal tem1:std_logic_vector(3 downto 0);signal tem2:std_logic_vec

26、tor(3 downto 0);begin process(clk,set,din1,din2) begin if set='1' then tem1<=din1; tem2<=din2; elsif clk'event and clk='1' then if (tem2="0010" and tem1="0011") then tem1<="0000" tem2<="0000" elsif(tem2/="0010" and tem

27、1="1001") then tem2<=tem2+1; tem1<="0000" else tem2<=tem2; tem1<=tem1+1; end if; end if; end process; qout1<=tem1; qout2<=tem2;end behave;這部分設(shè)計(jì)了一個(gè)24進(jìn)制計(jì)數(shù)器，用于小時(shí)位的計(jì)數(shù)，解決了時(shí)鐘位顯示的問(wèn)題。-功 能：24進(jìn)制計(jì)數(shù)器-接 口：clk -時(shí)鐘輸入- set -時(shí)間使能端- din1 -個(gè)位數(shù)據(jù)預(yù)置輸入- din2 -十位數(shù)據(jù)預(yù)置輸入- qout1-個(gè)位bcd輸出-

28、qout2-十位bcd輸出-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity cnt24 is port(clk : in std_logic; set : in std_logic; din1 : in std_logic_vector(3 downto 0); din2 : in std_logic_vector(3 downto 0); qout1 : out std_logic_vector(3 downto 0); q

29、out2 : out std_logic_vector(3 downto 0);end cnt24;architecture behave of cnt24 issignal tem1:std_logic_vector(3 downto 0);signal tem2:std_logic_vector(3 downto 0);begin process(clk,set,din1,din2) begin if set='1' then tem1<=din1; tem2<=din2; elsif clk'event and clk='1' then

30、 if (tem2="0010" and tem1="0011") then tem1<="0000" tem2<="0000" elsif(tem2/="0010" and tem1="1001") then tem2<=tem2+1; tem1<="0000" else tem2<=tem2; tem1<=tem1+1; end if; end if; end process; qout1<=tem1; qou

31、t2<=tem2;end behave;這個(gè)部分設(shè)計(jì)了一個(gè)60進(jìn)制計(jì)數(shù)器，用于分位，和秒位的設(shè)計(jì)，解決了分，秒計(jì)數(shù)的問(wèn)題。五，顯示部分設(shè)計(jì)-功 能：實(shí)現(xiàn)共陰數(shù)碼顯示管的編碼顯示-接 口：qin -bcd碼輸入- qout-七段碼輸出-library ieee;use ieee.std_logic_1164.all;entity led_driv isport(qin : in std_logic_vector(3 downto 0); qout : out std_logic_vector(6 downto 0);end led_driv;architecture behave of l

32、ed_driv isbegin process(qin) begin case qin is when "0000"=>qout<="0111111" -顯示0 when "0001"=>qout<="0000110" -顯示1 when "0010"=>qout<="1011011" -顯示2 when "0011"=>qout<="1001111" -顯示3 when "01

33、00"=>qout<="1100110" -顯示4 when "0101"=>qout<="1101101" -顯示5 when "0110"=>qout<="1111101" -顯示6 when "0111"=>qout<="0000111" -顯示7 when "1000"=>qout<="1111111" -顯示8 when "10

34、01"=>qout<="1101111" -顯示9 when others=>null; end case; end process;end behave; -這部分的設(shè)計(jì)用于數(shù)碼管上的顯示，動(dòng)態(tài)掃描的頻率用100hz，這個(gè)頻率是分頻得到的。解決了數(shù)字顯示的問(wèn)題。實(shí)驗(yàn)結(jié)果和分析數(shù)字時(shí)鐘顯示仿真圖整體輸入輸出數(shù)字時(shí)鐘顯示仿真如上圖所示，clk1為外部輸入時(shí)鐘信號(hào)為,qout依次為時(shí)鐘各位對(duì)應(yīng)數(shù)碼管的信號(hào).圖二所示數(shù)碼管上顯示。二十四進(jìn)制計(jì)數(shù)器仿真圖六十進(jìn)制計(jì)數(shù)器仿真圖100hz分頻器仿真圖 位選部分仿真圖led顯示仿真圖故障排除及問(wèn)題分析1， 開(kāi)始

35、時(shí)，分頻器沒(méi)有設(shè)計(jì)，直接將現(xiàn)有頻率加入，沒(méi)有顯示出結(jié)果，后反復(fù)思考，加入了分頻器部分，重新將端口調(diào)整，成功顯示出了結(jié)果。2， 在老師的指導(dǎo)下，有加入了報(bào)時(shí)功能，事先選擇的是將到12：00：00直接送一個(gè)信號(hào)給輸出端，事先報(bào)時(shí)，設(shè)計(jì)程序如下library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity baoshi isport( qin_s_1 : in std_logic_vector(3 downto 0); -秒鐘的低位調(diào)整輸入端 qin_s_2 : in std_logic_vector(3 downto 0); -秒鐘的高位調(diào)整輸入端 qin_m_1 : in std_logic_vector(3 downto 0); -分鐘的低位調(diào)整輸入端 qin_m_2 : in std_logic_vector(3 downto 0); -分鐘的高位調(diào)整輸入端 qin_h_1 : in st