VHDL流水線加法器

1、如果您需要使用本文檔，請點(diǎn)擊下載按鈕下載!可編程實(shí)驗(yàn)報(bào)告實(shí)驗(yàn)報(bào)告要求：1、任務(wù)的簡單描述2、畫出電路圖3、寫出源代碼4、仿真結(jié)果5、分析和討論1、3-8譯碼器源代碼：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_signed.all;entity dc38 isport(sel:instd_logic_vector(2 downto 0);y:outstd_logic_vector(7 downto 0);end dc38;architecture behavio

2、r of dc38 isbeginy<="11111110" when sel = "000" else"11111101" when sel = "001" else"11111011" when sel = "010" else"11110111" when sel = "011" else"11101111" when sel = "100" else"11011111&qu

3、ot; when sel = "101" else"10111111" when sel = "110" else"01111111" when sel = "111" else"zzzzzzzz"end behavior;仿真結(jié)果：1 / 13如果您需要使用本文檔，請點(diǎn)擊下載按鈕下載!一位全加器 a b ci s co 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1

4、12 / 13如果您需要使用本文檔，請點(diǎn)擊下載按鈕下載!四級流水加法器3 / 13如果您需要使用本文檔，請點(diǎn)擊下載按鈕下載!一位全加器 第 一 級 鎖 存 器 第 三 級 鎖 存 器 一位全加器第 二 級 鎖 存 器一位全加器 第 四 級 鎖 存 器一位全加器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity adder isport(clk,rst : in std_logic;a,b : in std_logic_vector

5、(3 downto 0);sum : out std_logic_vector(3 downto 0);c : out std_logic);end entity adder;architecture depict of adder issignal reg1: std_logic_vector(7 downto 0);signal reg2: std_logic_vector(6 downto 0);signal reg3: std_logic_vector(5 downto 0);beginbit0:process(clk,rst)beginif(rst='1') then

6、reg1<="00000000"elsif(rising_edge(clk) thenreg1(0)<= a(0) xor b(0); 4 / 13如果您需要使用本文檔，請點(diǎn)擊下載按鈕下載!reg1(1)<= a(0) and b(0);reg1(2)<= a(1); reg1(3)<= b(1);reg1(4)<= a(2);reg1(5)<= b(2);reg1(6)<= a(3);reg1(7)<= b(3);end if;end process bit0;bit1:process(clk,rst)beginif(

7、rst='1') thenreg2<="0000000"elsif(rising_edge(clk) thenreg2(0)<= reg1(0);reg2(1)<= reg1(1) xor reg1(2) xor reg1(3);reg2(2)<= (reg1(1) and reg1(2)or(reg1(1)and reg1(3)or(reg1(2)and reg1(3);reg2(6 downto 3)<=reg1(7 downto 4);end if; end process bit1;bit2:process(clk,rs

8、t)beginif(rst='1') thenreg3<="000000"elsif(rising_edge(clk) thenreg3(1 downto 0)<=reg2(1 downto 0);reg3(2)<=reg2(2)xor reg2(3)xor reg2(4);reg3(3)<=(reg2(2)and reg2(3)or(reg2(2)and reg2(4)or(reg2(3)and reg2(4);reg3(5 downto 4)<=reg2( 6 downto 5);end if;end process bit

9、2;bit3:process(clk,rst)beginif(rst='1') thensum<="0000"c<='0'elsif(rising_edge(clk) thensum(2 downto 0)<=reg3(2 downto 0);sum(3)<=reg3(3)xor reg3(4)xor reg3(5);c<=(reg3(3)and reg3(4)or(reg3(3)and reg3(5)or(reg3(4)and reg3(5);end if;5 / 13如果您需要使用本文檔，請點(diǎn)擊下載按鈕下載!

10、end process bit3;end depict;library ieee;use ieee.std_logic_1164.all;6 / 13如果您需要使用本文檔，請點(diǎn)擊下載按鈕下載!use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity noadd isport(clk,rst : in std_logic;a,b : in std_logic_vector(3 downto 0);sum : out std_logic_vector(3 downto 0);c : out std_logic);end

11、entity noadd;architecture depict of noadd issignal reg : std_logic_vector(4 downto 0);signal rega: std_logic_vector(4 downto 0);signal regb: std_logic_vector(4 downto 0);beginprocess(clk) beginif(rising_edge(clk)thenrega<='0'& a;regb<='0'& b; end if;end process;process(

12、clk)beginif(rst='1')thenreg<="00000"elsif(rising_edge(clk)thenreg<=rega+regb;end if;end process;sum<=reg(3 downto 0);c<=reg(4);end depict;7 / 13如果您需要使用本文檔，請點(diǎn)擊下載按鈕下載!4位十進(jìn)制數(shù)計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arit

13、h.all;entity dec_disp is port(clk_cnt : in std_logic;sel1 : out std_logic_vector(3 downto 0);8 / 13如果您需要使用本文檔，請點(diǎn)擊下載按鈕下載!sel2 : out std_logic_vector(3 downto 0);sel3 : out std_logic_vector(3 downto 0);sel4 : out std_logic_vector(3 downto 0);end dec_disp;architecture behav of dec_disp issignal data1 :

14、 std_logic_vector(3 downto 0);signal data2 : std_logic_vector(3 downto 0);signal data3 : std_logic_vector(3 downto 0);signal data4 : std_logic_vector(3 downto 0);begin count:process(clk_cnt) begin if(rising_edge(clk_cnt)then if(data1="1001")then data1<="0000" else if(data2=&qu

15、ot;1001")then data2<="0000" data1<=data1+1; else if(data3="1001")then data3<="0000" data2<=data2+1; else if(data4="1001")then data4<="0000" data3<=data3+1; else data4<=data4+1; end if; end if; end if; end if;end if;end proce

16、ss count;sel1<=data1;sel2<=data2;sel3<=data3;sel4<=data4;end behav;9 / 13如果您需要使用本文檔，請點(diǎn)擊下載按鈕下載!正弦波發(fā)生器10 / 13如果您需要使用本文檔，請點(diǎn)擊下載按鈕下載!11 / 13如果您需要使用本文檔，請點(diǎn)擊下載按鈕下載!13 / 13如果您需要使用本文檔，請點(diǎn)擊下載按鈕下載!13 / 13如果您需要使用本文檔，請點(diǎn)擊下載按鈕下載!sin.mif文件depth=256;width=8;address_radix=dec;data_radix=dec;content13 / 13如果

17、您需要使用本文檔，請點(diǎn)擊下載按鈕下載!begin 0: 131; 1: 134; 2: 137; 3: 141; 4: 144; 5: 147; 6: 150; 7: 153; 8: 156; 9: 159; 10: 162; 11: 165; 12: 168; 13: 171; 14: 174; 15: 177; 16: 180; 17: 183; 18: 186; 19: 188; 20: 191; 21: 194; 22: 196; 23: 199; 24: 202; 25: 204; 26: 207; 27: 209; 28: 212; 29: 214; 30: 216; 31!219

18、; 32:221; 33:223; 34:225; 35:227; 36:229; 37:231; 38:233; 39:234; 40:236; 41:238; 42:239; 43:241; 44:242; 45:244; 46:245; 47:246; 48:247; 49:249; 50:250; 51:250; 52:251; 53:252; 54:253; 55:254; 56:254; 57:255; 58:255; 59:255; 60:255; 61:255; 62:255; 63:255; 64:255; 65:255; 66:255; 67:255; 68:255; 69

19、:255; 70:254; 71:254; 72:253; 73:252; 74:251; 75:250; 76:250; 77:249; 78:247; 79:246; 80:245; 81:244; 82:242; 83:241; 84:239; 85:238; 86:236; 87:234; 88:233; 89:231; 90:229; 91:227; 92:225; 93:223; 94:221; 95:219; 96:216; 97:214; 98:212; 99:209; 100:207; 101:204; 102:202; 103:199; 104:196; 105:194;

20、106:191; 107:188; 108:186; 109:183; 110:180; 111:177;112:174; 113:171; 114:168; 115:165; 116:162; 117:159; 118:156; 119:153; 120:150; 121:147;122:144; 123:141; 124:137; 125:134; 126:131; 127:128; 128:125; 129:122; 130:119; 15 / 13如果您需要使用本文檔，請點(diǎn)擊下載按鈕下載!131:115; 132:112; 133:109; 134:106; 135:103; 136:10; 137:97; 138:94; 139:91;140:88; 141:85; 142:82; 143:79; 144:76; 145:73; 146:70; 147:68; 148:65; 149:62; 150:60; 151:57; 152:54; 153:52; 154:49; 155:47; 156:44; 157:42; 158:40; 159:37; 160:35; 161:33; 162:31; 163:29; 164:27; 165:25;166:23; 167:22;168:20; 169:18; 170