EDA程序設計試題及答案資料

1、1請畫出下段程序的真值表，并說明該電路的功能。library ieee;use ieee.std_logic_1164.all;entity aaa isport( oe,dir :in std_logic ;a,b : inout std_logic_vector(7 downto 0 ) ;end aaa ;architecture ar of aaa isbeginprocess(oe , dir )輸入輸出begina1a0x3x2x1x0if oe=?0? then a<=” zzzzzzzz”;1,”b<= ” zzzzzzzz”;000001elsif oe=?1?

2、then010010if dir= ?0? then b<=a;100100elsif dir= ?1? then a<=b;111000endif;end if ;end process ;end ar ;功能為：24譯碼器.4分2請說明下段程序的功能，寫出真值表，并畫出輸入輸出波形。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity aaa isport( reset,clk: in std_logic;q: bu

3、ffer std_logic_vector(2 downto 0);end aaa;architecture bd of aaa isbeginprocess(clk,reset)beginif (reset='0') then q<="000"elsif (clk'event and clk='1') thenif (q=5) then q<="000"else q<=q+1;end if;end if;end process;end bd;功能為：帶進位借位的4位加/減法器。 .3分輸入輸出波

4、形圖如下： 7分a3.0:一：=. b3.0c3.0一，一 ;:d1.試用vhdl語言編程實現(xiàn)74ls273芯片的功能。libraryuseieee;ieee.std_logic_1164.all;2?entityls273is1?port(endls273;architectureclr, dq);clklock8beginprocess ( clk )beginif (clr= ?0?)in std_logic;in std_logic_vector(7 downto 0 );out std_logic_vector(7 downto 0 );of ls273 isthen q<=&

5、quot;00000000” ；elseif (clk ?event and clk= ?1 ? then q<=d;elseif ( clk= ?0?) then q<=q;end if;end process;end lock8;3.請用vhdl語言編程實現(xiàn)一個狀態(tài)向量發(fā)生器。libraryieee;use ieee.std_logic_1164.all;entitystasisport(cp, rst:in std_logic;p:buffer std_logic_vector(7 downto 0 ););end stas;architecturebeginarstasof

6、 stasis4?1?1?2?3?1?2?1?2?1?1?1?1?process (cp )beginif(rst="0")then p<= "00000000elseif (cp ?event and cp= ?1 ?)p<= "10101010”when00000000”；”01010101”when10101010”；”00001111”when01010101” ；”11110000”when00001111” ；”11111111”when11110000” ；”00000000”when11111111” ；”00000000”w

7、henothers;with p select6?end ifend process;end arstas;1.閱讀下段程序，畫出該電路的真值表，并詳細說明該電路的功能library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ab_8 isport( a, b : in std_logic_vector(7 downto 0); ahb, alb, aeb: out std_logic);end ab_8;architecture bd of ab_8 isbeginprocess(a,b)b

8、eginif a>b then ahb<=?1? alb<=?0?; aeb<=?0?;elsif a<b then ahb<=?0? alb<=?1? aeb<=?0?else ahb<=?0?; alb<=?0? aeb<=?1?end if;1”，其余端輸出為“ 0”(2?)end process;end bd;1. (1)真值表如下：(5?)輸 入輸 出a、bahbalbaeba>b100a<b010a=b001（2）該電路是一個8位兩輸入比較器，（2?）a、b是兩個8位輸入端；（1?）ahb、alb和aeb

9、為比較結果輸出端，某種比較結果為真時，相應的輸出端為1 .試用vhdl語言編程實現(xiàn)一個2-4譯碼器，其真表如下:輸入端輸出端enselecty0xx1111”1001110"1011101"1101011"1110111”2-4譯碼器碼 參考程序如下:(答案不唯一，用 case語句、withselect語句都可以。) library ieee;use ieee.std_logic_1164.all;(1?)entity ym24 isport( en : in std_logic;select : out std_logic_vector(1 downto 0);

10、y : out std_logic_vector(3 downto 0)(3?);end ym24;architecture bd of ym24 isbeginprocess(en)(1 ?)if (en=?1?) theny<=“1110”whenselect="00"else“1101”whenselect ="01"else“1011”whenselect ="10"else“0111”whenselect ="11”else(4?)a a a 1111 ;else y<="1111”;end

11、process;end bd;a、b、c、d、e、f都是8位輸入總2 .試用vhdl語言設計一個六路8位總線復用器，其中線，q為8位輸出總線，s為3位選擇端，其功能如下:輸入端輸出端s2s1s0q7q0000q=a001q=b010q=c011q=d100q=e101q=f其它b= "00000000”六路8位總線復用器 參考程序:(答案不唯一)library ieee;use ieee.std_logic_1164.all;entity mux6 isport(s : in std_logic_vector(2 downto 0);a,b,c,d,e,f: in std_logic

12、_vector(7 downto 0);q: out std_logic_vector(7 downto 0);end mux6;architecture bd of mux6 isbeginprocess(s)begincase s iswhen "000"=>q<=a;when "001"=>q<=b;when "010"=>q<=c;when "011"=>q<=d;when "100"=>q<=e;when "101&

13、quot;=>q<=f;when others=>q<="00000000"end case;end process;(1?)(3?)(1?)(4?)end bd;2、已知三選一電路如圖，判斷下列程序是否有錯誤，如有則指出錯誤所在，并給出完整程序。(10分)library ieee;use ieee.std_logic_1164.all;entity max isport(a1,a2,a3,s0,s1:in bit;outy:out bit);end max;( 2?)architecture one of max iscomponent mux21

14、aport(a,b,s:in std_logic;y:out std_logic);end component; (2?)signal temp std_logic;_ (2?)beginu1:mux21a port map(a2,a3,s0,temp);(2?)u2:mux21a port map(a1,temp,s1,outy);2 2?)end one;1.已知電路原理圖如下，請用 vhdl語言編寫其程序冷is:答：library ieee;use ieee.std_logic_1164.all;entity mux21 is port(a,b,s:in bit;y:out bit);e

15、nd mux21;(4?)architecture one of mux21 is single d,e:bit;begind<=a and (not)s;e<=b and s; y<=d or e;end one;2.設計一個帶有異步清零功能的十進制計數(shù)器。計數(shù)器時鐘clk上升沿有效、清零端clrn、co。進位輸出glk dqut £3. s：心lrhco答：library ieee;use ieee.std_logic_1164.all;entity counter10 isport(clk,clrn:in std_logic;dout:out integer

16、range 0 to 9);end counter10;architecture behav of counter10 isbeginprocess(clk)variable cnt:integer range 0 to 9; begin if clrn='0' thencnt:=0;elsifclk='1'and clk'event then(5?)(3?)if cnt=9 thencnt:=0;elsecnt:=cnt+1;end if;end if;dout<=cnt;end process;end behav;(7?)3. 1)用vhdl語

17、言編寫半加器和或門器件的程序，如圖所示：h-rdderor2a答：半加器程序：library ieee;use ieee.std_logic_1164.all;entity h_adder isport(a,b:in std_logic;co,so:out std_logic);end h_adder;architecture one of h_adder isbeginso<=not(a xor(not b);co<=a and b;end one;或門程序：library ieee;use ieee.std_logic_1164.all;entity or2a isport(a

18、,b:in std_logic;c:out std_logic);end or2a;architecture one of or2a isbeginc<=a or b;end one;2)在上道題目的基礎上用元件例化語句設計1位全加器。(2?)(3?)(2?)bin匚堂前匕將bl i i "i i i b 1 bl 19 i 1h_ adderhaddera"o3im主程序：library ieee;use ieee.std_logic_1164.all;entity f_adder isport(ain,bin,cin:in std_logic;cout,sum:o

19、ut std_logic);end entity f_adder;architecture fd1 of f_adder iscomponent h_adderport(a,b:in std_logic;co,so:out std_logic);end component;(5?)component or2aport(a,b:in std_logic;c:out std_logic);end component;signal d,e,f:std_logic;beginu1 : h_adder port map(a=>ain,b=>bin,co=>d,so=>e);u2

20、: h_adder port map(a=>e,b=>cin,co=>f,so=>sum);u3 : or2a port map(d,f,cout);end fd1;(5?)1,試用vhdl語言編程實現(xiàn)一個總線開關，其真值表如下:輸入輸出enselecta0a6b0b6y0y6,0?,x?zzzzzzz”,1?,0?a,1?,1?b1 .總線開關的參考程序如下：library ieee;use ieee.std_logic_1164.all;(1?)entity aaa isport( en, select : in std_logic ;a, b : in std_l

21、ogic_vector(6 downto 0 ) ;y : out std_logic_vector(6 downto 0)end aaa ;(4?)architecture ar of aaa isbeginprocess(en, select ) beginif en=?0? then y<= ” zzzzzzz ”;elsif en=?1? thenif select=?0? then y<=a;elsif select=?1? then y<=b; end if;end if ;end process ;end ar ;(5?)2.試用vhdl語言編程實現(xiàn)一個m10計

22、數(shù)器，要求該計數(shù)器有一個時鐘輸入端 clk, 一個復位端 rst (低電平復位)，一個使能端en (高電平時允許計數(shù))，一個“計數(shù)到”輸出端cout, 一個4位二進制 當前計數(shù)值輸出口 q； cout 端僅當計數(shù)滿的一個時鐘周期輸出高電平，其余時刻全保持低電平。2. m10 計數(shù)器參考程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;( 1?)entity aaa isport(clk, rst, en : in std_logic;c

23、out: out std_logic;q: buffer std_logic_vector(3 downto 0) );end aaa;(4?)architecture bd of aaa isbeginprocess(clk,reset,en) beginif (rst='0') then q<="0000"elsif (clk'event and clk='1') then if en= ?1? thenif (q=9) then q<="0000"else q<=q+1;end if;end

24、 if;end if;end process;(10?)end bd;3.請用vhdl語言編程，用一個狀態(tài)機模型實現(xiàn)一個七段碼 led字符發(fā)生器。該電路有一個復位輸入 端rst, 一個時鐘輸入端cp, 一組七段碼輸出端ag。在led上七個段的排列位置如圖所示。該電路 的功能為，當復位輸入端 rst為低電平時，輸出端口輸出全零，無顯示；當 rst為高電平時，在時鐘信號cp的每個上升沿，輸出端依次輪流輸出5個字符“happy”的七段碼（共陰極接法），周而復始3.用vhdl語言編程實現(xiàn)一個 led字符發(fā)生器參考程序:library ieee;use ieee.std_logic_1164.all;e

25、ntity gencis(1?)port( rst, cp:in std_logic;a,b,c,d,e,f,g: out std_logic );(1?)end genc;architecture aa of genc istype state is(s0,s1, s2, s3, s4, s5 );signal pstate: state;signal dout: std_logic_vector(6 downto 0 );(27)beginpr1: process(cp, rst,) beginif rst='0' then pstate <=s0;elsif (cp

26、'event and cp='0' ) thencase pstate iswhen s0=> pstate <=s1;when s1=> pstate <=s2;when s2=> pstate <=s3;when s3=> pstate <=s4;when s4=> pstate <=s5;when s5=> pstate <=s1;when others=> pstate <=s0;end case;end if;end process;(57) pr2: process(psta

27、te)begincase state iswhen s0 => dout<="0000000”;-無顯示when si => dout<="0110111”;-h”when s2 => dout<="1110111”;-a ”when s3 => dout<="1100111”;-p”when s4 => dout<="1100111”;-p”when s5 => dout<="0111011”;-y”when others=> dout<="

28、;0000000”;- 無顯示 end case;(5?)end process;a<=dout(6); b<=dout(5); c<=dout(4); d<=dout(3); e<=dout(2); f<=dout;g<=dout(0);end aa;(1?)2 .試用vhdl語言和進程語句，編程實現(xiàn)一個3-8譯碼器。該譯碼器的功能為，當使能信號en為低電平時，輸出端y7y0全為高電平(沒有輸出端被選中)； 當en為高電平時，每一種abc的輸入狀態(tài)組合能惟一地選中一路輸出(被選中的端輸出低電平)。真值表如下:輸 入輸出abceny7y6y5y4y3y

29、2y1y00001口111111r 000111111110101011111101101r 1 i111 111011r 1100111101111101111011111110 111011111口1111101111口xxx011111111library ieee;use ieee.std_logic_1164.all;entity ym38 isport( a, b, c, en :iny :out);end ym38;architecture arc38beginprocess(en) signal din : begin din<=a&b&c&en;

30、 with2?1?std_logic;std_logic_vector(7 downto 0 );3?of ls273 is1?1?std_logic_vector(7 downto 0 );1?din select1?y<= "11111110'when 0001 ”11111101”when0011”；”11111011”when0101"；”11110111”when0111"；”11101111”when1001"；”11011111”when1011"；”10111111”when1101” ；”01111111”whe

31、n1111” ；”11111111”whenothers;endprocess;5?end arc38;1.試用vhdl語言編程實現(xiàn)一個多路開關。該電路的功能為，當選擇端so和si為不同狀態(tài)組合時，如果使能信號en為電平，輸出端x和y分別與不同的輸入通道a0b0、a1b1、a2b2和a3b3接通并保持，當 en為低電平時，x、丫輸出為高阻態(tài)。真值表如下：輸 入輸出s1s0ena0b0a1b1a2b2a3b3xy1 001xxxxxxxxa。b01011xxxxxxxxa1b1101xxxxxxxxa2b21 111xxxxxxxxa3b3 1xx0xxxxxxxxzz1.多路開關的參考程序如下

32、:library ieee;use ieee.std_logic_1164.all;entity mulkey is port(s0,s1,en, a0,b0,a1,b1,a2,b2,a3,b3: in std_logic;x, y : out std_logic_vector(7 downto 0 );3?)；end mulkey;architecture armk of mulkey is signal sel : std_logic_vecter (1 downto 0 ) beginsel<=s1&s0;2?process (en )?beginif (en=?0?) t

33、henx<=?z?；y<=?z?;elseif (sel="00") thenx<=a0 ;y<=b0;elseif (sel="01") thenx<=a1 ;y<=b1;elseif (sel="10")thenx<=a2;y<=b2;elseif (sel="11")thenx<=a3 ;y<=b3;end if;end process;endarmk;六、寫vhdl1序：（10分）1. 設計 10 進制加法計數(shù)器，要求含異步清0 和同步時鐘使能。注

34、意：時鐘信號命名為clk,使能信號為en,清零信號為rst,計數(shù)輸出為cq。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt10 isport (clk,rst,en : in std_logic;cq : out std_logic_vector(3 downto 0);cout : out std_logic );end cnt10;architecture behav of cnt10 isbeginprocess(clk, rst, en)variable cqi :

35、std_logic_vector(3 downto 0);begin計數(shù)器異步復位檢測時鐘上升沿檢測是否允許計數(shù)（同步使能）允許計數(shù) , 檢測是否小于 9大于9 ，計數(shù)值清零計數(shù)大于 9 ，輸出進位信號if rst = '1' then cqi := (others =>'0') ; -elsif clk'event and clk='1' then -if en = '1' then-if cqi < 9 then cqi := cqi + 1;-else cqi := (others =>'0

36、');-end if;end if;end if;if cqi = 9 then cout <= '1'-else cout <= '0'end if;cq <= cqi; -將計數(shù)值向端口輸出end process;end behav;2. 試描述一個帶進位輸入、輸出的 8 位全加器端口： a 、 b 為加數(shù)， cin 為進位輸入， s 為加和， cout 為進位輸出library ieee;use ieee.std_logic_1164.all;entity adder8 isport (a, b : in std_logic_ve

37、ctor (7 downto 0);cin : in std_logic;cout : out std_logic;s : out std_logic_vector (7 downto 0) );end adder8;architecture one of adder8 issignal ts : std_logic_vector (8 downto 0);begints <= ( , 0? & a) + (, 0? & b) + cin;s <= ts(7 downto 0);cout <= ts(8);end one;七、vhdls序設計：(20分)設計一

38、數(shù)據(jù)選擇器mux, 其系統(tǒng)模塊圖和功能表如下圖所示。試采用下面三種方式中的兩種來描述該數(shù)據(jù)選擇器mux的結構體。sel(1:o)sel00011011others(a)用if語句。(b)用case語句。(c)用when else語句。library ieee;use ieee.std_logic_1164.all;entity mymux isport ( sel : in std_logic_vector(1 downto 0);ain, bin : in std_logic_vector(1 downto 0);cout : out std_logic_vector(1 downto 0)

39、;end mymux;architecture one of mymux isbeginprocess (sel, ain, bin)beginif sel =00" then cout <= ain and bin;elsif sel =01 " then cout <= ain xor bin;elsif sel ='10 " then cout <= not ain;else cout <= not bin;end if;end process;end one;architecture two of mymux is begi

40、nprocess (sel, ain, bin)begincase sel iswhen00"=> cout<= ain and bin;when01 "=> cout<= ain xor bin;when'10"=> cout<= not ain;when others => cout <= not bin;end case;end process;end two;architecture three of mymux isbegincout <= ain and bin when sel = ain

41、 xor bin when sel = not ain when sel =00" else01 " else "10" else not bin;end three;設計一個7段數(shù)碼顯示譯碼器，并逐行進行解釋library ieee ;use ieee.std_logic_1164.all ;coutain and binaim xor binnot ainnot biny選擇信號輸入 數(shù)據(jù)輸入entity decl7s isport ( a : in std_logic_vector(3 downto 0);led7s : out std_logic

42、_vector(6 downto 0) ) ;end ;architecture one of decl7s isbeginprocess( a )begincase a iswhen "0000" => led7s <= "0111111" ;when "0001" => led7s <= "0000110" ;when "0010" => led7s <= "1011011" ;when "0011" => l

43、ed7s <= "1001111" ;when "0100" => led7s <= "1100110" ;when "0101" => led7s <= "1101101" ;when "0110" => led7s <= "1111101" ;when "0111" => led7s <= "0000111" ;when "1000" =&

44、gt; led7s <= "1111111" ;when "1001" => led7s <= "1101111" ;when "1010" => led7s <= "1110111" ;when "1011" => led7s <= "1111100" ;when "1100" => led7s <= "0111001" ;when "1101&quo

45、t; => led7s <= "1011110" ;when "1110" => led7s <= "1111001" ;when "1111" => led7s <= "1110001" ;when others => null ;end case ;end process ;end ;關于數(shù)據(jù)選擇器餓設計1 、 4 選 1 多路選擇器的if 語句描述library ieee;use ieee.std_logic_1164.all;entity mul

46、tiplexers_1 is port (a, b, c, d : in std_logic;s : in std_logic_vector (1 downto 0);o : out std_logic);end multiplexers_1;architecture archi of multiplexers_1 is beginprocess (a, b, c, d, s)beginif (s = "00") then o <= a;elsif (s = "01") then o <= b;elsif (s = "10"

47、;) then o <= c;else o <= d;end if;end process;end archi;2、4選1多路選擇器的case語句描述 library ieee;use ieee.std_logic_1164.all;entity multiplexers_2 isport (a, b, c, d : in std_logic;s : in std_logic_vector (1 downto 0);o : out std_logic);end multiplexers_2;architecture archi of multiplexers_2 isbeginpr

48、ocess (a, b, c, d, s)begincase s iswhen "00" => o <= a;when "01" => o <= b;when "10" => o <= c;when others => o <= d;end case;end process;end archi;3、用選擇用條件信號賦值語句描述四選一電路entity mux4 isport(i0, i1, i2, i3 : in std_logic;sel: in std_logic_vector(1 d

49、ownto 0);q : out std_logic);end mux4;architecture rtl of mux4 isbeginq<=i0 when sel =“ 00 ”elsei1 when sel =“ 01 ”elsei2 when sel =“10”elsei3 when sel =“11”;end rtl;4、信號賦值語句描述四選一電路entity mux4 isport(i0, i1, i2, i3 : in std_logic;sel: in std_logic_vector(1 downto 0);q : out std_logic);end mux4;arc

50、hitecture rtl of mux4 issignal sel : std_logic_vector (1 downto 0); beginwith sel selectq<=i0 when sel =“ 00i1whensel =“ 01 ”,i2whensel =“ 10 ”,i3whensel =“ 11 ”, x when others ；end rtl;關于編碼器和譯碼器的設計1 、順序描述語句中 if 語句之 8-3 線編碼器library ieee;use ieee.std_logic_1164.all;entity priority_encoder isport (

51、 sel : in std_logic_vector (7 downto 0); code :out std_logic_vector (2 downto 0); end priority_encoder;architecture archi of priority_encoder isbeginprocess (sel)beginif sel(0)='1' then code<="000"elsif sel(1)='1' then code<="001"elsif sel(2)='1' the

52、n code<="010"elsif sel(3)='1' then code<="011"elsif sel(4)='1' then code<="100"elsif sel(5)='1' then code<="101"elsif sel(6)='1' then code<="110"else code<="111"end if;end process;end archi;

53、2 、并發(fā)描述語句之 8-3 線編碼器library ieee;use ieee.std_logic_1164.all;entity priority_encoder_1 isport ( sel : in std_logic_vector (7 downto 0);code :out std_logic_vector (2 downto 0);end priority_encoder_1;architecture archi of priority_encoder_1 is begincode <= "000" when sel(0) = '1' e

54、lse"001" when sel(1) = '1' else"010" when sel(2) = '1' else"011" when sel(3) = '1' else"100" when sel(4) = '1' else"101" when sel(5) = '1' else"110" when sel(6) = '1' else"111" when

55、sel(7) = '1' else "zzz"end archi;3 、順序描述語句中 case 語句之 3-8 譯碼器library ieee;use ieee.std_logic_1164.all;entity encoder_38 isport ( sel : in std_logic_vector (2 downto 0);en : in std_logiccode :out std_logic_vector (7 downto 0);end encoder_38;architecture rtl of encoder_38 isbeginproce

56、ss (sel,en)beginif (en= 1 ) thencase sel iswhen "000" =>code <= " 00000001 "when "001" =>code <= " 00000010 "when "010" =>code <= " 00000100 "when "011" =>code <= " 00001000 "when“ 100" =>

57、code <=" 00010000"when“ 101" =>code <=" 00100000"when“ 110" =>code <=" 01000000"when“ 111" =>code <=" 10000000"when others =>code <= " 00000000 "end case;else code <= " zzzzzzzz "end if;end proce

58、ss;end rtl;并發(fā)描述語句之 3-8 譯碼器library ieee;use ieee.std_logic_1164.all;entity encoder_38 isport ( sel : in std_logic_vector (2 downto 0);code :out std_logic_vector (7 downto 0);end encoder_38;architecture archi of encoder_38 issignal sel: std_logic_vector (2 downto 0);beginwith sel selectcode <= " 00000001" when sel="000", "00000010" when sel="001"," 00000100 " when sel= "010" ," 00001000 " when sel="011&