基于VHDL的空調(diào)控制器設(shè)計(jì)

1、數(shù)字系統(tǒng)設(shè)計(jì)與硬件描述語(yǔ)言期末考試作業(yè)題目： 空調(diào)控制器的設(shè)計(jì) 學(xué)院： 電子信息工程學(xué)院 專業(yè)： 物聯(lián)網(wǎng)工程 學(xué)號(hào)： 3014204328 姓名： 劉涵凱 2016-12-14一、 選題設(shè)計(jì)描述1. 功能介紹設(shè)計(jì)內(nèi)容為空調(diào)控制器，可實(shí)現(xiàn)空調(diào)的開(kāi)關(guān)、模式切換、溫度控制、風(fēng)速控制、定時(shí)設(shè)置。模式默認(rèn)為制冷，可切換為制熱、除濕。溫度默認(rèn)為26度，可按“溫度+”、“溫度-”調(diào)節(jié)，每次調(diào)節(jié)1度，最高30度，最低16度。風(fēng)速默認(rèn)為中擋，可按“風(fēng)速+”、“風(fēng)速-”切換為低擋、高擋、睡眠模式。睡眠模式中，在低擋與停止間循環(huán)。定時(shí)設(shè)置默認(rèn)關(guān)閉，開(kāi)啟時(shí)默認(rèn)30分鐘，可按“定時(shí)+”、“定時(shí)-”調(diào)節(jié)，每次調(diào)節(jié)30分鐘

2、，最高24小時(shí)，最低30分鐘。定時(shí)倒計(jì)時(shí)結(jié)束時(shí)，關(guān)閉空調(diào)。定時(shí)開(kāi)啟時(shí)，可按“取消定時(shí)”關(guān)閉定時(shí)?？照{(diào)控制器模擬界面如下：2. 算法簡(jiǎn)介1）空調(diào)控制器 其輸入與輸出在主程序kt中已標(biāo)明，在此不做介紹。2）單脈沖模塊這是非常重要以及核心的模塊。當(dāng)a產(chǎn)生一個(gè)上升沿時(shí)，輸出一個(gè)單脈沖，脈沖將持續(xù)到經(jīng)過(guò)一個(gè)clk上升沿后的clk下降沿。3）開(kāi)關(guān)模塊a連接空調(diào)的開(kāi)關(guān)，b連接開(kāi)關(guān)控制模塊的輸出，c為空調(diào)各工作模塊的開(kāi)關(guān)信號(hào)，d連接數(shù)碼管顯示開(kāi)關(guān)狀況。當(dāng)定時(shí)時(shí)間結(jié)束，b輸入一個(gè)單脈沖，空調(diào)關(guān)閉。4）開(kāi)關(guān)控制模塊此模塊的作用是保證開(kāi)關(guān)模塊能夠正常工作。開(kāi)關(guān)打開(kāi)時(shí)，a輸入一個(gè)單脈沖，重置c。b連接定時(shí)模塊，當(dāng)定時(shí)

3、結(jié)束，b輸入一個(gè)單脈沖，使c輸出1，使開(kāi)關(guān)模塊輸出05）溫度模塊a連接開(kāi)關(guān)模塊，b為溫度+1，c為溫度-1，輸出為溫度的十位和個(gè)位。6）風(fēng)速模塊a連接開(kāi)關(guān)模塊，b為風(fēng)速+1，c為風(fēng)速-1。di，zhong，gao為抵擋、中擋、高擋的狀態(tài)（無(wú)睡眠模式，因?yàn)樗吣Ｊ绞堑謸?停止模式）。其他連接數(shù)碼管，顯示睡眠模式、抵擋、中擋、高擋的狀態(tài)。7）模式模塊b連接開(kāi)關(guān)模塊，c為切換模式，輸出類似于模式模塊。8）定時(shí)模塊a連接開(kāi)關(guān)模塊，b為定時(shí)模塊開(kāi)啟，c為取消定時(shí)，up、down為定時(shí)時(shí)間+、-。clk1為空調(diào)時(shí)鐘，clk2為模擬的倒計(jì)時(shí)時(shí)鐘（周期1分鐘）。clk2周期遠(yuǎn)大于clk1。當(dāng)時(shí)間倒計(jì)時(shí)結(jié)束時(shí)，

4、sw1輸出1，使開(kāi)關(guān)控制模塊控制開(kāi)關(guān)關(guān)閉。其他輸出連接倒計(jì)時(shí)模塊。9）倒計(jì)時(shí)模塊a連接開(kāi)關(guān)模塊，clk連接定時(shí)模塊的clk2，輸入時(shí)間發(fā)生變化時(shí)，重新倒計(jì)時(shí)。倒計(jì)時(shí)結(jié)束時(shí)，finish輸出1，使定時(shí)模塊的sw1輸出1。10）數(shù)碼管模塊a連接開(kāi)關(guān)模塊，此為7段譯碼器。11）計(jì)數(shù)器模塊此為六位計(jì)數(shù)器。a連接睡眠模式開(kāi)關(guān)，rst為睡眠模式打開(kāi)時(shí)的重置信號(hào)，每6次輸出一次1。二、 程序源代碼及說(shuō)明1）空調(diào)控制器LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;ENTITY kt IS PORT(swit

5、chin,modeset,fanup,fandown,tempup,tempdown,timerop,timercancel,timerup,timerdown,clk1,clk2: IN STD_LOGIC; -電源開(kāi)關(guān)、模式切換、風(fēng)速+、風(fēng)速-、溫度+、溫度-、定時(shí)、取消定時(shí)、定時(shí)+、定時(shí)-、時(shí)鐘信號(hào)、倒計(jì)時(shí)時(shí)鐘信號(hào) cools,heats,drys,dis,zhongs,gaos: OUT STD_LOGIC; -通向空調(diào)內(nèi)部的制冷、制熱、除濕、抵擋、中擋、高擋狀態(tài)輸出 switchstate,tempd,temps,coolstate,heatstate,drystate,distat

6、e,zhongstate,gaostate,sleepstate,hdstate,hsstate,tdstate,tsstate: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -由數(shù)碼管顯示的開(kāi)關(guān)、溫度、制冷、制熱、除濕、抵擋、中擋、高擋、睡眠狀態(tài)和倒計(jì)時(shí)剩余時(shí)間END ENTITY kt;ARCHITECTURE behave OF kt ISCOMPONENT switch -開(kāi)關(guān)模塊 PORT(a,b,clk: IN STD_LOGIC; -b受定時(shí)模塊的控制，時(shí)間減為0時(shí)，關(guān)閉開(kāi)關(guān) c: OUT STD_LOGIC; d: OUT STD_LOGIC_VECTO

7、R(3 DOWNTO 0); -輸送給數(shù)碼管 END COMPONENT switch; COMPONENT control -開(kāi)關(guān)控制模塊 PORT(a,b,clk: IN STD_LOGIC; c: OUT STD_LOGIC); END COMPONENT control; COMPONENT fan -風(fēng)速模塊 PORT(a,b,c,clk: IN STD_LOGIC; di,zhong,gao: OUT STD_LOGIC; -由于high和low是敏感詞匯，所以此處用拼音，可以看到此處沒(méi)有睡眠模式，是因?yàn)樗吣Ｊ狡鋵?shí)是抵擋-停止模式 ssleep,sdi,szhong,sgao:

8、OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -不同于發(fā)給空調(diào)內(nèi)部的信號(hào)，睡眠模式的狀態(tài)應(yīng)顯示在外 END COMPONENT fan; COMPONENT BCD7 -數(shù)碼管模塊 PORT(a: IN STD_LOGIC; b: IN STD_LOGIC_VECTOR(3 DOWNTO 0); q : OUT STD_LOGIC_VECTOR(0 TO 6) ); END COMPONENT BCD7; COMPONENT pulse -單脈沖模塊 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pu

9、lse; COMPONENT temp -溫度模塊 PORT(a,b,c,clk: IN STD_LOGIC; -a控制開(kāi)關(guān)，b提高1度，c降低1度 temp1,temp2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END COMPONENT temp; COMPONENT timer -定時(shí)模塊 PORT(a,b,c,up,down,clk1,clk2: IN STD_LOGIC; sw1: OUT STD_LOGIC; -總開(kāi)關(guān)關(guān)閉信號(hào) oh1,oh2,ot1,ot2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -輸送給數(shù)碼管顯示剩余時(shí)

10、間 END COMPONENT timer; COMPONENT mode PORT(b,c,clk: IN STD_LOGIC; cool,heat,dry: OUT STD_LOGIC; cool1,heat1,dry1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END COMPONENT mode;SIGNAL swa,swb,swc:STD_LOGIC;SIGNAL sigBCD7_1,sigBCD7_2,sigBCD7_3,sigBCD7_4,sigBCD7_5,sigBCD7_6,sigBCD7_7,sigBCD7_8,sigBCD7_9,sigBCD7

11、_10,sigBCD7_11,sigBCD7_12,sigBCD7_13,sigBCD7_14:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINU1: switch PORT MAP(a=>switchin,b=>swb,c=>swa,clk=>clk1,d=>sigBCD7_1); U2: control PORT MAP(a=>switchin,b=>swc,clk=>clk1,c=>swb);U3: fan PORT MAP(a=>swa,b=>fanup,c=>fandown,clk=>c

12、lk1,di=>dis,zhong=>zhongs,gao=>gaos,ssleep=>sigBCD7_2,sdi=>sigBCD7_3,szhong=>sigBCD7_4,sgao=>sigBCD7_5); U4: temp PORT MAP(a=>swa,b=>tempup,c=>tempdown,clk=>clk1,temp1=>sigBCD7_6,temp2=>sigBCD7_7); U5: timer PORT MAP(a=>swa,clk1=>clk1,clk2=>clk2,b=>

13、timerop,c=>timercancel,up=>timerup,down=>timerdown,sw1=>swc,oh1=>sigBCD7_8,oh2=>sigBCD7_9,ot1=>sigBCD7_10,ot2=>sigBCD7_11); U6: mode PORT MAP(b=>swa,c=>modeset,clk=>clk1,cool=>cools,heat=>heats,dry=>drys,cool1=>sigBCD7_12,heat1=>sigBCD7_13,dry1=>sig

14、BCD7_14); U7: BCD7 PORT MAP(a=>swa,b=>sigBCD7_1,q=>switchstate); U8: BCD7 PORT MAP(a=>swa,b=>sigBCD7_2,q=>sleepstate); U9: BCD7 PORT MAP(a=>swa,b=>sigBCD7_3,q=>distate); U10: BCD7 PORT MAP(a=>swa,b=>sigBCD7_4,q=>zhongstate); U11: BCD7 PORT MAP(a=>swa,b=>sigB

15、CD7_5,q=>gaostate);U12: BCD7 PORT MAP(a=>swa,b=>sigBCD7_6,q=>tempd); U13: BCD7 PORT MAP(a=>swa,b=>sigBCD7_7,q=>temps); U14: BCD7 PORT MAP(a=>swa,b=>sigBCD7_8,q=>hdstate); U15: BCD7 PORT MAP(a=>swa,b=>sigBCD7_9,q=>hsstate); U16: BCD7 PORT MAP(a=>swa,b=>sig

16、BCD7_10,q=>tdstate);U17: BCD7 PORT MAP(a=>swa,b=>sigBCD7_11,q=>tsstate); U18: BCD7 PORT MAP(a=>swa,b=>sigBCD7_12,q=>coolstate); U19: BCD7 PORT MAP(a=>swa,b=>sigBCD7_13,q=>heatstate); U20: BCD7 PORT MAP(a=>swa,b=>sigBCD7_14,q=>drystate); PROCESS(clk1)BEGINEND PR

17、OCESS;END ARCHITECTURE behave;2）單脈沖模塊LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;ENTITY pulse IS -單脈沖模塊 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC);END ENTITY pulse;ARCHITECTURE behave OF pulse ISSIGNAL d:STD_LOGIC:='0'SIGNAL f:STD_LOGIC:='0'SIGNAL g:ST

18、D_LOGIC:='0' -確保經(jīng)過(guò)第一個(gè)clk上升沿時(shí)輸出1SIGNAL h:STD_LOGIC:='0' -同上BEGINPROCESS(a,clk) BEGINIF(clk'EVENT AND clk='1')THENIF(f='1')THENg<='1'ELSE g<='0'END IF;END IF;END PROCESS;PROCESS(a,clk) BEGINIF(clk'EVENT AND clk='0')THENIF(a='1&#

19、39;)THENIF(f='1')THENIF(g='1')THEN d<='1'ELSE d<='0'END IF;ELSE d<='1'END IF;ELSE d<='0' -a為0時(shí)，重置此單脈沖發(fā)生器END IF;END IF;END PROCESS;PROCESS(d) BEGINIF(a='1')THENIF(d='1')THENf<='0' ELSE f<='1'END IF;ELSE

20、f<='0'END IF;b<=f;END PROCESS;END ARCHITECTURE behave;3）開(kāi)關(guān)模塊LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;ENTITY switch IS -開(kāi)關(guān)模塊 PORT(a,b,clk: IN STD_LOGIC; -b受定時(shí)模塊的控制，時(shí)間減為0時(shí)，關(guān)閉開(kāi)關(guān) c: OUT STD_LOGIC; d: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -輸送給數(shù)碼管END ENTITY switch;ARCHITECTURE behave OF switch

21、ISCOMPONENT pulse -調(diào)用單脈沖模塊 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pulse; SIGNAL p1 : STD_LOGIC:='0'SIGNAL p2 : STD_LOGIC:='0'BEGINU1: pulse PORT MAP(a=>a,b=>p1,clk=>clk); U2: pulse PORT MAP(a=>b,b=>p2,clk=>clk); PROCESS(a,b,clk) BEGIN IF(clk'

22、EVENT AND clk='1')THEN IF(p1='1')THEN -空調(diào)開(kāi)關(guān)打開(kāi) c<='1'd<="0001" END IF; IF(p2='1')THEN -時(shí)間減為0時(shí)，定時(shí)模塊返回1，關(guān)閉開(kāi)關(guān) c<='0'd<="0000" END IF; END IF; END PROCESS;END ARCHITECTURE behave;4）開(kāi)關(guān)控制模塊LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;ENTI

23、TY control IS -開(kāi)關(guān)控制模塊 PORT(a,b,clk: IN STD_LOGIC; c: OUT STD_LOGIC);END ENTITY control;ARCHITECTURE behave OF control ISCOMPONENT pulse -調(diào)用單脈沖模塊 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pulse; SIGNAL p1 : STD_LOGIC:='0'SIGNAL p2 : STD_LOGIC:='0'BEGINU1: pulse PORT M

24、AP(a=>a,b=>p1,clk=>clk); U2: pulse PORT MAP(a=>b,b=>p2,clk=>clk); PROCESS(a,b,clk) BEGIN IF(clk'EVENT AND clk='1')THEN IF(p1='1')THEN -空調(diào)開(kāi)關(guān)打開(kāi) c<='0' END IF; IF(p2='1')THEN -時(shí)間減為0時(shí)，定時(shí)模塊返回1，關(guān)閉開(kāi)關(guān) c<='1' END IF; END IF; END PROCESS;END

25、ARCHITECTURE behave;5）溫度模塊LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;ENTITY temp IS -溫度模塊,最高30度，最低16度，默認(rèn)26度 PORT(a,b,c,clk: IN STD_LOGIC; -a控制開(kāi)關(guān)，b提高1度，c降低1度 temp1,temp2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END ENTITY temp;ARCHITECTURE behave OF temp ISCOMPONENT pulse -調(diào)

26、用單脈沖模塊 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pulse; SIGNAL t1 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL t2 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL p1 : STD_LOGIC:='0'SIGNAL p2 : STD_LOGIC:='0'SIGNAL p3 : STD_LOGIC:='0'BEGINU1:

27、pulse PORT MAP(a=>b,b=>p1,clk=>clk); U2: pulse PORT MAP(a=>c,b=>p2,clk=>clk); U3: pulse PORT MAP(a=>a,b=>p3,clk=>clk); PROCESS(a,clk)BEGIN IF(clk'EVENT AND clk='1')THEN IF(p3='1')THEN -開(kāi)關(guān)打開(kāi)時(shí)，默認(rèn)26度 t1<="0010"t2<="0110"ELSIF(a=&#

28、39;0')THEN t1<="0000"t2<="0000"END IF; IF(a='1')THENIF(p1='1')THEN -判斷"溫度+"按鍵按下IF(t1="0011")THEN t1<="0011"t2<="0000" ELSIF(t2="1001")THENt1<=t1+'1' t2<="0000" ELSE t2<=t2

29、+'1' END IF; END IF; IF(p2='1')THEN -判斷"溫度-"按鍵按下 IF(t1="0001")THEN IF(t2="0110")THEN t1<="0001"t2<="0110"ELSE t2<=t2-'1' END IF; ELSIF(t2="0000")THEN t1<=t1-'1' t2<="1001" ELSE t2<

30、=t2-'1' END IF; END IF;ELSE t1<="0000"t2<="0000"END IF; END IF;temp1<=t1;temp2<=t2;END PROCESS;END ARCHITECTURE behave;6）風(fēng)速模塊LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;ENTITY fan IS -風(fēng)速模塊：睡眠、低、中、高；默認(rèn)中擋；睡眠模式在低擋和停止之間循環(huán) PORT(a,b,c,

31、clk: IN STD_LOGIC; di,zhong,gao: OUT STD_LOGIC; -由于high和low是敏感詞匯，所以此處用拼音，可以看到此處沒(méi)有睡眠模式，是因?yàn)樗吣Ｊ狡鋵?shí)是抵擋-停止模式 ssleep,sdi,szhong,sgao: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -不同于發(fā)給空調(diào)內(nèi)部的信號(hào)，睡眠模式的狀態(tài)應(yīng)顯示在外END ENTITY fan;ARCHITECTURE behave OF fan ISCOMPONENT pulse -調(diào)用單脈沖模塊 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC)

32、; END COMPONENT pulse; COMPONENT count6 -調(diào)用計(jì)數(shù)器 PORT ( a,clk,rst : IN STD_LOGIC; o: OUT STD_LOGIC); END COMPONENT count6; SIGNAL e : STD_LOGIC_VECTOR(2 DOWNTO 0):="000" -停止000、睡眠001、抵擋010、中擋011、高擋100SIGNAL p1 : STD_LOGIC:='0'SIGNAL p2 : STD_LOGIC:='0'SIGNAL p3 : STD_LOGIC:=&

33、#39;0'SIGNAL op : STD_LOGIC:='0'SIGNAL op1 : STD_LOGIC:='0' -其上升沿用于開(kāi)啟睡眠模式SIGNAL op2 : STD_LOGIC:='0' SIGNAL rst1 : STD_LOGIC:='0'SIGNAL rst2 : STD_LOGIC:='0'SIGNAL change : STD_LOGIC:='0'SIGNAL m : STD_LOGIC:='0' -睡眠模式中使用，由于睡眠模式是循環(huán)模式，所以不設(shè)置置

34、0BEGIN -模式在按鍵操作下可循環(huán)滾動(dòng)U1: pulse PORT MAP(a=>b,b=>p1,clk=>clk); U2: pulse PORT MAP(a=>c,b=>p2,clk=>clk); U3: pulse PORT MAP(a=>a,b=>p3,clk=>clk); U4: pulse PORT MAP(a=>rst1,b=>rst2,clk=>clk); U5: count6 PORT MAP(a=>op,rst=>rst2,clk=>clk,o=>change); PROCE

35、SS(a,clk)BEGIN IF(clk'EVENT AND clk='1')THEN op1<=op2;IF(p3='1')THEN -開(kāi)關(guān)打開(kāi)時(shí)，默認(rèn)中擋 e<="011"ELSIF(a='0')THEN e<="000"END IF; IF(a='1')THENIF(p1='1')THEN -判斷"風(fēng)速+"按鍵按下IF(e="100")THEN -高擋時(shí)按下，則切換為睡眠 e<="001

36、"op1<='1' ELSE e<=e+'1'op1<='0' END IF; END IF; IF(p2='1')THEN -判斷"風(fēng)速"-"按鍵按下 IF(e="001")THEN -睡眠時(shí)按下，則切換為高擋 e<="100"op1<='0'ELSIF(e="010")THENe<=e-'1'op1<='1'ELSE e<=e-

37、9;1'op1<='0' END IF; END IF;ELSE e<="000"END IF; END IF;END PROCESS;PROCESS(change)BEGINIF(change'EVENT AND change='1')THENIF(m='1')THENm<='0'ELSE m<='1'END IF;END IF;END PROCESS; PROCESS(e)BEGINop2<=op1;IF(e="001")TH

38、EN -睡眠時(shí)的低擋-停止循環(huán)IF(op2'EVENT AND op2='1')THENop<='1'rst1<='1'END IF;op<='1'CASE m IS WHEN '1' => di<='1'zhong<='0'gao<='0'ssleep<="0001"sdi<="0000"szhong<="0000"sgao<=&qu

39、ot;0000" WHEN '0' => di<='0'zhong<='0'gao<='0'ssleep<="0001"sdi<="0000"szhong<="0000"sgao<="0000" END CASE;ELSEop<='0'-關(guān)閉睡眠模式 IF(e="010")THEN di<='1'zhong<='0&#

40、39;gao<='0'ssleep<="0000"sdi<="0001"szhong<="0000"sgao<="0000" ELSIF(e="011")THEN di<='0'zhong<='1'gao<='0'ssleep<="0000"sdi<="0000"szhong<="0001"sgao<=

41、"0000" ELSIF(e="100")THEN di<='0'zhong<='0'gao<='1'ssleep<="0000"sdi<="0000"szhong<="0000"sgao<="0001" ELSIF(e="000")THEN di<='0'zhong<='0'gao<='0'sslee

42、p<="0000"sdi<="0000"szhong<="0000"sgao<="0000" END IF; END IF; END PROCESS;END ARCHITECTURE behave;7）模式模塊LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;ENTITY mode IS -模式模塊：制冷、制熱、除濕 PORT(b,c,clk: IN STD_LOGIC; cool,heat,

43、dry: OUT STD_LOGIC; cool1,heat1,dry1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END ENTITY mode;ARCHITECTURE behave OF mode ISCOMPONENT pulse -單脈沖模塊 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pulse; SIGNAL e : STD_LOGIC_VECTOR(1 DOWNTO 0):="00"SIGNAL p1 : STD_LOGIC:='0'SIGN

44、AL p2 : STD_LOGIC:='0'BEGINU1: pulse PORT MAP(a=>b,b=>p1,clk=>clk); U2: pulse PORT MAP(a=>c,b=>p2,clk=>clk); PROCESS(b,c,p1,p2,clk) -按鍵選擇模式BEGINIF(clk'EVENT AND clk='1')THENIF(b='1')THENIF(p1='1')THEN -默認(rèn)制冷模式e<="01"END IF;IF(p2='

45、1')THENIF(e="11")THENe<="01"ELSE e<=e+'1'END IF;END IF;ELSE e<="00"END IF;END IF;END PROCESS; PROCESS(e)BEGIN -由于第一個(gè)PROCESS中，a為0時(shí)e為"00"，所以此處不再考慮a CASE e IS WHEN "01" => cool<='1'heat<='0'dry<='0

46、9;cool1<="0001"heat1<="0000"dry1<="0000" WHEN "10" => cool<='0'heat<='1'dry<='0'cool1<="0000"heat1<="0001"dry1<="0000"WHEN "11" => cool<='0'heat<=

47、9;0'dry<='1'cool1<="0000"heat1<="0000"dry1<="0001"WHEN OTHERS => cool<='0'heat<='0'dry<='0'cool1<="0000"heat1<="0000"dry1<="0000" END CASE; END PROCESS;END ARCHITECTURE be

48、have;8）定時(shí)模塊ENTITY timer IS -定時(shí)模塊：最低30分鐘，最高24小時(shí)，每次按鍵調(diào)整30分鐘，可取消定時(shí) PORT(a,b,c,up,down,clk1,clk2: IN STD_LOGIC; sw1: OUT STD_LOGIC; -總開(kāi)關(guān)關(guān)閉信號(hào) oh1,oh2,ot1,ot2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -輸送給數(shù)碼管顯示剩余時(shí)間END ENTITY timer;ARCHITECTURE behave OF timer ISCOMPONENT pulse -調(diào)用單脈沖模塊 PORT(a,clk: IN STD_LOGIC;

49、b: OUT STD_LOGIC); END COMPONENT pulse; COMPONENT cd -調(diào)用倒計(jì)時(shí)模塊 PORT(a,clk: IN STD_LOGIC; time1,time2,time3,time4: IN STD_LOGIC_VECTOR(3 DOWNTO 0); finish: OUT STD_LOGIC; outtime1,outtime2,outtime3,outtime4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END COMPONENT cd; SIGNAL cl : STD_LOGIC:='0' SIGNAL

50、op : STD_LOGIC:='0'SIGNAL p1 : STD_LOGIC:='0'SIGNAL p2 : STD_LOGIC:='0'SIGNAL p3 : STD_LOGIC:='0'SIGNAL sw : STD_LOGIC:='0'-倒計(jì)時(shí)模塊開(kāi)關(guān)信號(hào)SIGNAL h11 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL h22 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL t1

51、1 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0011"SIGNAL t22 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL h1 : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL h2 : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL t1 : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL t2 : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN U1: pulse PORT MAP(a=

52、>b,b=>op,clk=>clk1); U2: pulse PORT MAP(a=>c,b=>cl,clk=>clk1); U3: pulse PORT MAP(a=>up,b=>p1,clk=>clk1); U4: pulse PORT MAP(a=>down,b=>p2,clk=>clk1); U5: pulse PORT MAP(a=>sw,b=>p3,clk=>clk1); U6: cd PORT MAP(a=>sw,clk=>clk2,time1=>h1,time2=>

53、h2,time3=>t1,time4=>t2,finish=>sw1,outtime1=>oh1,outtime2=>oh2,outtime3=>ot1,outtime4=>ot2); PROCESS(a,op,cl)BEGINIF(a='1')THENIF(op='1')THEN sw<='1'END IF;IF(cl='1')THEN sw<='0'END IF;ELSE sw<='0'END IF;END PROCESS;PROCES

54、S(sw,clk1)BEGINIF(clk1'EVENT AND clk1='1')THEN IF(p3='1')THEN -定時(shí)開(kāi)啟時(shí)，默認(rèn)30分鐘 h11<="0000"h22<="0000"t11<="0011"t22<="0000"ELSIF(sw='0')THEN h11<="0000"h22<="0000"t11<="0000"t22<=&q

55、uot;0000"END IF; IF(sw='1')THENIF(p1='1')THEN -判斷"時(shí)間+"按鍵按下IF(h11="0010")THENIF(h22="0100")THENh11<="0010"h22<="0100"t11<="0000"t22<="0000"ELSIF(t11="0000")THENt11<="0011"ELSE

56、 h22<=h22+'1't11<="0000"END IF;ELSIF(h22="1001")THENIF(t11="0000")THENt11<="0011"ELSE h11<=h11+'1'h22<="0000"t11<="0000"END IF;ELSIF (t11="0011")THENh22<=h22+'1't11<="0000"

57、ELSE t11<="0011"END IF;END IF; IF(p2='1')THEN -判斷"時(shí)間-"按鍵按下 IF(h11="0000")THEN IF(h22="0000")THENh11<="0000"h22<="0000"t11<="0011"t22<="0000"ELSIF(t11="0011")THENt11<="0000"EL

58、SE h22<=h22-'1't11<="0011"END IF;ELSIF(h22="0000")THENIF(t11="0011")THENt11<="0000"ELSE h11<=h11-'1'h22<="1001"t11<="0011"END IF;ELSIF (t11="0011")THENt11<="0000"ELSE h22<=h22-'

59、;1't11<="0011"END IF;END IF;END IF;END IF;h1<=h11;h2<=h22;t1<=t11;t2<=t22;END PROCESS;END ARCHITECTURE behave;9）倒計(jì)時(shí)模塊LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;ENTITY cd IS -倒計(jì)時(shí)模塊，僅在定時(shí)開(kāi)啟時(shí)有效 PORT(a,clk: IN STD_LOGIC; time1,time2,time3,time4

60、: IN STD_LOGIC_VECTOR(3 DOWNTO 0); finish: OUT STD_LOGIC; outtime1,outtime2,outtime3,outtime4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ENTITY cd;ARCHITECTURE behave OF cd ISCOMPONENT pulse -調(diào)用單脈沖模塊 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pulse; SIGNAL s : STD_LOGIC:='0'SIGNAL

61、 intime11 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL intime22 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL intime33 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL intime44 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL stime1 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL stime2 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL stime3 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL stime4 : STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"SIGNAL intime5 : STD_LOGIC_VECTOR (1 DOWNTO 0):=&quo