EDA(第8章)-10.5

1、CPLD/FPGACPLD/FPGA的開發(fā)與應(yīng)用的開發(fā)與應(yīng)用第第8 8章章 VHDLVHDL應(yīng)用舉例應(yīng)用舉例n帶權(quán)表決器帶權(quán)表決器n奇數(shù)分頻器設(shè)計奇數(shù)分頻器設(shè)計n數(shù)控分頻器設(shè)計數(shù)控分頻器設(shè)計n計數(shù)計數(shù)/譯碼驅(qū)動譯碼驅(qū)動/掃描顯示電路掃描顯示電路n串串-并轉(zhuǎn)換與并并轉(zhuǎn)換與并-串轉(zhuǎn)換串轉(zhuǎn)換n模式可控移位寄存器模式可控移位寄存器n數(shù)字序列的產(chǎn)生與檢測數(shù)字序列的產(chǎn)生與檢測n多功能端口設(shè)計多功能端口設(shè)計n數(shù)字基帶編碼設(shè)計數(shù)字基帶編碼設(shè)計帶權(quán)表決器的帶權(quán)表決器的VHDL設(shè)計設(shè)計奇數(shù)分頻器的奇數(shù)分頻器的VHDL設(shè)計設(shè)計clkinclkoutf p_11inst奇數(shù)分頻器仿真波形奇數(shù)分頻器仿真波形分頻系數(shù)分頻

2、系數(shù)=11數(shù)控分頻器的數(shù)控分頻器的VHDL設(shè)計設(shè)計LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY FPQ IS PORT ( CLKIN : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLKOUT : OUT STD_LOGIC );END FPQ;ARCHITECTURE one OF FPQ IS SIGNAL FULL : STD_LOGIC;BEGIN P1: PROCESS(CLKIN) VARIABLE CNT8

3、 : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN IF CLKINEVENT AND CLKIN = 1 THEN IF CNT8 = 11111111 THEN CLKIND7.0CLKOUTfpqinst CNT8 := D; -當(dāng)當(dāng)CNT8CNT8計數(shù)計滿時，輸入數(shù)據(jù)計數(shù)計滿時，輸入數(shù)據(jù)D D被同步預(yù)置給計數(shù)器被同步預(yù)置給計數(shù)器CNT8CNT8 FULL = 1; -同時使溢出標志信號同時使溢出標志信號FULLFULL輸出為高電平輸出為高電平 ELSE CNT8 := CNT8 + 1; -否則繼續(xù)作加否則繼續(xù)作加1 1計數(shù)計數(shù) FULL = 0; -且輸出溢

4、出標志信號且輸出溢出標志信號FULLFULL為低電平為低電平 END IF; END IF; END PROCESS P1 ; P2: PROCESS(FULL) VARIABLE CNT2 : STD_LOGIC; BEGIN IF FULLEVENT AND FULL = 1 THEN CNT2 := NOT CNT2; -如果溢出標志信號如果溢出標志信號FULLFULL為高電平，輸出取反為高電平，輸出取反 CLKOUT 88* *25Hz)25Hz)，實現(xiàn)掃描顯示的目的。，實現(xiàn)掃描顯示的目的。 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IE

5、EE.STD_LOGIC_UNSIGNED.ALL;ENTITY SCAN_LED IS PORT ( CLK : IN STD_LOGIC; -掃描時鐘掃描時鐘信號輸入信號輸入 A1，A2，A3，A4，A5，A6，A7，A8 : IN INTEGER RANGE 0 TO 15; SG: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -段控制信號輸出段控制信號輸出(g-a)(g-a) BT: OUT STD_LOGIC_VECTOR(8 DOWNTO 1)）;-位控制信號輸出位控制信號輸出(k8-k1)(k8-k1) END SCAN_LED;ARCHITECTURE

6、one OF SCAN_LED ISSIGNAL CNT8:STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL A :INTEGER RANGE 0 TO 15;BEGINP1：PROCESS( CNT8 ) BEGIN 掃描譯碼顯示電路的掃描譯碼顯示電路的VHDLVHDL設(shè)計設(shè)計CLKA13.0A23.0A33.0A43.0A53.0A63.0A73.0A83.0SG6.0BT8.1SCAN_LEDinst CASE CNT8 IS WHEN 000 = BT = 00000001 ; A BT = 00000010 ; A BT = 00000100 ; A BT =

7、 00001000 ; A BT = 00010000 ; A BT = 00100000 ; A BT = 01000000 ; A BT = 10000000 ; A NULL ; END CASE ; END PROCESS P1; P2：PROCESS(CLK) BEGIN IF CLKEVENT AND CLK = 1 THEN CNT8 SG SG SG SG SG SG SG SG SG SG SG SG SG SG SG SG NULL ; END CASE ; END PROCESS P3; END one; 共陰數(shù)碼管及其電路共陰數(shù)碼管及其電路 CASE A IS WHEN

8、 0 = SG SG SG SG SG SG SG SG SG SG SG SG SG SG SG SG NULL ; END CASE ; Library ieee;Use ieee.std_logic_1164.all;Entity c_b isPort (clr,din,clk: in std_logic; y: out std_logic_vector(4 downto 0);End c_b;Architecture behav of c_b issignal tem:std_logic_vector(5 downto 0);beginp1: process(clk) begin if

9、 (clkevent and clk=1) thenif clr=0 thentem=000000;elsif tem(0)=0 thentem=din & 01111;elsetem=din & tem(5 downto 1);end if;end if;end process p1;p2: process(tem) begin if tem(0)=0 then y=tem(5 downto 1); else y CY = REG(7); REG(7 DOWNTO 1) = REG(6 DOWNTO 0); REG(0) CY = REG(7); REG(7 DOWNTO 1

10、) = REG(6 DOWNTO 0); REG(0) CY = REG(0); REG(6 DOWNTO 0) = REG(7 DOWNTO 1); REG(7) CY = REG(0); REG(6 DOWNTO 0) = REG(7 DOWNTO 1); REG(7) REG(7 DOWNTO 0) REG = REG ; CY = CY ; -保持保持 END CASE; END IF; END PROCESS;QB(7 DOWNTO 0) = REG(7 DOWNTO 0); CN = CY; -移位后輸出移位后輸出 END BEHAV; -帶進位左移帶進位左移-自循環(huán)左移自循環(huán)左移

11、-自循環(huán)右移自循環(huán)右移 -帶進位右移帶進位右移（接上頁）（接上頁）模式可控移位寄存器仿真波形模式可控移位寄存器仿真波形（MD=001） 數(shù)字序列信號發(fā)生器的數(shù)字序列信號發(fā)生器的VHDL設(shè)計設(shè)計cpresyxxinst數(shù)字序列信號產(chǎn)生波形數(shù)字序列信號產(chǎn)生波形當(dāng)當(dāng)reg、n定義為變量時，有何不同？請修改完善！定義為變量時，有何不同？請修改完善！數(shù)字序列檢測器的數(shù)字序列檢測器的VHDL設(shè)計設(shè)計cpcxycxjcinst數(shù)字序列檢測數(shù)字序列檢測仿真波形仿真波形數(shù)字序列檢測數(shù)字序列檢測State MachinaState Machina Viewer Viewer分析波形，找出問題，修改完善！分析波形，

12、找出問題，修改完善！8位并行數(shù)據(jù)位并行數(shù)據(jù)“0”個數(shù)檢測器的個數(shù)檢測器的VHDL設(shè)計設(shè)計clkclrd7.0q2.0zerojcinst8 8位并行數(shù)據(jù)位并行數(shù)據(jù)“0”0”個數(shù)檢測仿真波形個數(shù)檢測仿真波形library ieee;use ieee.std_logic_1164.all;entity tri_state isport (control : in std_logic; in1: in std_logic_vector(7 downto 0); q : inout std_logic_vector(7 downto 0); x : out std_logic_vector(7 dow

13、nto 0);end tri_state;architecture body_tri of tri_state isbeginprocess(control,q,in1)beginif (control = 0) then x = q ; else q = in1; x=ZZZZZZZZ ；end if;end process;end body_tri; 雙向端口的雙向端口的VHDL設(shè)計設(shè)計1【例【例5-13】controlin17.0 x7.0q7.0qqinst 1.0s 1.5s 2.0s 2.5s 3.0s 3.5s 雙向端口仿真波形雙向端口仿真波形1 1雙向端口綜合結(jié)果雙向端口綜合結(jié)

14、果1 1library ieee;use ieee.std_logic_1164.all;entity tri_state isport (control : in std_logic; in1: in std_logic_vector(7 downto 0); q : inout std_logic_vector(7 downto 0); x : out std_logic_vector(7 downto 0);end tri_state;architecture body_tri of tri_state isbeginprocess(control,q,in1)beginif (cont

15、rol = 0) then x = q ; q=ZZZZZZZZ ; else q = in1; x=ZZZZZZZZ ; ;end if;end process;end body_tri; 雙向端口的雙向端口的VHDL設(shè)計設(shè)計2【例【例5-14】controlin17.0 x7.0q7.0qqinst 1.0s 1.5s 2.0s 2.5s 3.0s 3.5s 雙向端口仿真波形雙向端口仿真波形2 2雙向端口綜合結(jié)果雙向端口綜合結(jié)果2 2【例【例5-15】 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY tri1 IS port ( input3

16、, input2, input1, input0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); enable : IN STD_LOGIC_VECTOR (1 DOWNTO 0); output : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END tri1 ; ARCHITECTURE multiple_drivers OF tri1 ISBEGINPROCESS(enable,input3, input2, input1, input0 ) BEGIN IF enable = 00 THEN output = input3 ; ELSE

17、output Z); END IF ; IF enable = 01 THEN output = input2 ; ELSE output Z); END IF ; （接下頁）（接下頁） 三態(tài)總線電路的三態(tài)總線電路的VHDL設(shè)計設(shè)計1input37.0input27.0input17.0input07.0enable1.0output7.0tri1inst（接上頁）（接上頁） IF enable = 10 THEN output = input1 ; ELSE output Z); END IF ; IF enable = 11 THEN output = input0 ; ELSE outp

18、ut Z); END IF ; END PROCESS;END multiple_drivers; 三態(tài)總線綜合結(jié)果三態(tài)總線綜合結(jié)果1 1【例【例5-16】library ieee;use ieee.std_logic_1164.all;entity tri2 isport ( ctl : in std_logic_vector(1 downto 0); datain1， datain2，datain3， datain4 : in std_logic_vector (7 downto 0); q : out std_logic_vector(7 downto 0) );end tri2;arc

19、hitecture body_tri of tri2 isbegin q Z) ; q Z) ; q Z) ; q Z) ;end body_tri; 三態(tài)總線電路的三態(tài)總線電路的VHDL設(shè)計設(shè)計2注：例注：例5-15可用可用4個并行的個并行的process語句正確設(shè)計語句正確設(shè)計ctl1.0datain17.0datain27.0datain37.0datain47.0q7.0tri2inst三三態(tài)態(tài)總總線線綜綜合合結(jié)結(jié)果果2 2ttttttttt01000011000001010二進制代碼(a)(b)(c)(d)(e)(f)(g)(h)(i)數(shù)數(shù)字字基基帶帶信信號號的的常常用用碼碼型型(a

20、)(a) 單極性單極性(NRZ)(NRZ)碼碼 ；(b) (b) 雙極性雙極性(NRZ)(NRZ)碼；碼；(c) (c) 單極性單極性(RZ)(RZ)碼；碼； (d) (d) 雙極性雙極性(RZ)(RZ)碼；碼；(e) (e) 差分碼；差分碼；(f) (f) 交替極性碼交替極性碼(AMI)(AMI)； (g) (g) 三階高密度雙極性三階高密度雙極性碼碼(HDB(HDB3 3) )；(h) (h) 分相碼；分相碼；( (i i) ) 信號反轉(zhuǎn)碼信號反轉(zhuǎn)碼(CMI) (CMI) 數(shù)字序列數(shù)字序列AMI編碼設(shè)計編碼設(shè)計 AMI AMI碼是傳號交替反轉(zhuǎn)碼，在碼是傳號交替反轉(zhuǎn)碼，在AMIAMI碼中，二進制碼碼中，二進制碼0 0用用0 0電平表示，二進制碼電平表示，二進制碼1 1交替地用交替地用+1+1和和-1-1表示表示 。其編碼