Lec3 FIR Digital Filters(實(shí)時(shí)信號(hào)處理系統(tǒng))

1、實(shí)時(shí)信號(hào)處理系統(tǒng)設(shè)計(jì)與實(shí)現(xiàn)實(shí)時(shí)信號(hào)處理系統(tǒng)設(shè)計(jì)與實(shí)現(xiàn)第第3章章 FIR 數(shù)字濾波器數(shù)字濾波器講授內(nèi)容安排l1.數(shù)字濾波器和FIR理論 轉(zhuǎn)置結(jié)構(gòu)FIR濾波器 FIR濾波器的對(duì)稱性 線性相位FIR濾波器l2.FIR濾波器設(shè)計(jì) 直接窗函數(shù)設(shè)計(jì)法 等紋波設(shè)計(jì)法l3.常系數(shù)FIR濾波器設(shè)計(jì) 直接FIR設(shè)計(jì) 轉(zhuǎn)置結(jié)構(gòu)FIR濾波器 用分布式算法設(shè)計(jì)FIR濾波器 IP核FIR濾波器設(shè)計(jì) 基于DA和基于RAG的FIR濾波器比較I. 數(shù)字濾波器和FIR理論數(shù)字濾波器（1）l線性時(shí)不變?yōu)V波器（Linear Time-Invariant，LTI）l有限脈沖響應(yīng)濾波器（Finite Impulse Response,

2、FIR）采樣數(shù)量有限，濾波器在每個(gè)采樣時(shí)刻進(jìn)行有限次卷積l無(wú)限脈沖響應(yīng)濾波器（Infinite Impulse Response, IIR）1. 濾波器在每個(gè)采樣時(shí)刻進(jìn)行無(wú)限次卷積 kky nx nf nx k f nkf k x nk數(shù)字濾波器（2）l模擬濾波器 利用微分方程和Laplace變換進(jìn)行建模與分析 利用RLC元件和運(yùn)算放大器實(shí)現(xiàn) 可以用作IIR濾波器設(shè)計(jì)的原型l數(shù)字濾波器 是數(shù)字信號(hào)處理的主要組成部分 正在逐漸替代模擬濾波器 IIR濾波器以模擬濾波器為原型進(jìn)行設(shè)計(jì)，F(xiàn)IR濾波器直接用數(shù)字方法進(jìn)行設(shè)計(jì)FIR濾波器理論（1）l對(duì)于輸入時(shí)間序列xn，常系數(shù)L階FIR濾波器的輸出yn為

3、為濾波器的系數(shù)，對(duì)應(yīng)FIR濾波器的脈沖響應(yīng)。l用 Z 域表示F(z)是FIR濾波器的傳遞函數(shù) 10Lky nx nf nf k x nk ,0,1,1f kkL Y zF z X z 10LkkF zf k z直接形式FIR濾波器結(jié)構(gòu)l關(guān)鍵路徑： TA ：加法器的延遲，TM ：乘法器的延遲 關(guān)鍵路徑延遲：1 TM + (M-1) TA l面積： M-1 個(gè)寄存器，M 個(gè)乘法器，M-1 個(gè)加法器l遲滯： 遲滯為x(0)和y(0), x(1)和y(1),之間的時(shí)鐘周期數(shù)。 0 時(shí)鐘周期遲滯。l運(yùn)算復(fù)雜度： M 次乘法/采樣數(shù) + M-1次加法/采樣數(shù)x(n)Z-1Z-1Z-1h0h1h2hM-1y

4、(n)FIR濾波器理論（2）lFIR濾波器僅有零點(diǎn)存在，系統(tǒng)穩(wěn)定 多項(xiàng)式F(z)的根確定零點(diǎn) CIC濾波器（Cascade Integrator Comb Filter，級(jí)聯(lián)積分梳狀濾波器 ）具有遞歸性，但遞歸部分產(chǎn)生的極點(diǎn)被非遞歸部分抵消，只有零點(diǎn)。 非遞歸實(shí)現(xiàn)濾波器均為FIR濾波器，但遞歸實(shí)現(xiàn)濾波器可以是FIR濾波器，也可以是I IR濾波器。轉(zhuǎn)置結(jié)構(gòu)FIR濾波器l轉(zhuǎn)置結(jié)構(gòu) FIR 濾波器是FIR濾波器的常見(jiàn)實(shí)現(xiàn)方式，結(jié)構(gòu)上具有如下優(yōu)點(diǎn)：不需要給輸入xn提供額外的移位寄存器；不需要為了獲得高流量而在乘積的加法器樹(shù)中加入流水線不改變系統(tǒng)功能l構(gòu)造方法利用信號(hào)流圖反轉(zhuǎn)，是直接形式FIR濾波器的一

5、種變形：將輸入和輸出互換；顛倒信號(hào)流的方向；1.用分支（fork）替換加法器，反之亦然。轉(zhuǎn)置結(jié)構(gòu)FIR濾波器結(jié)構(gòu)x(n)Z-1Z-1Z-1hM-1hM-2hM-3h0y(n)l采用信號(hào)流圖反轉(zhuǎn)來(lái)縮短關(guān)鍵路徑長(zhǎng)度 轉(zhuǎn)置結(jié)構(gòu)l關(guān)鍵路徑延遲：1 TM + 1 TA l面積：M-1個(gè)寄存器，M個(gè)乘法器，M-1個(gè)加法器l遲滯:0 時(shí)鐘周期遲滯l運(yùn)算復(fù)雜度：M 次乘法/采樣數(shù) + M-1次加法/采樣數(shù)l缺點(diǎn)：寄存器的大小取決于量化機(jī)制x(n)的扇出太多FIR濾波器VHDL設(shè)計(jì)（1）l舉例3.1：可編程FIR濾波器 考慮線性卷積和數(shù)據(jù)（或系數(shù)）的位寬為Bx，濾波器長(zhǎng)度為L(zhǎng)，對(duì)無(wú)符號(hào)SOP運(yùn)算提供log2L個(gè)

6、保護(hù)位，對(duì)有符號(hào)SOP運(yùn)算提供(log2L)1個(gè)保護(hù)位。例如，有符號(hào)數(shù)據(jù)（或系數(shù)）的位寬為9，L = 4，則加法器的位寬為9 + 9 + log24 1=19. 10Lky nx nf nf k x nkFIR濾波器VHDL設(shè)計(jì)（2）- This is a generic FIR filter generator - It uses W1 bit data/coefficients bitsLIBRARY lpm; - Using predefined packagesUSE lpm.lpm_components.ALL;LIBRARY ieee;USE ieee.std_logic_1164

7、.ALL;USE ieee.std_logic_arith.ALL;USE ieee.std_logic_unsigned.ALL;ENTITY fir_gen IS - Interface GENERIC (W1 : INTEGER := 9; - Input bit width W2 : INTEGER := 18;- Multiplier bit width 2*W1 W3 : INTEGER := 19;- Adder width = W2+log2(L)-1 W4 : INTEGER := 11;- Output bit width L : INTEGER := 4; - Filte

8、r length Mpipe : INTEGER := 3- Pipeline steps of multiplier );FIR濾波器VHDL設(shè)計(jì)（3）PORT ( clk : IN STD_LOGIC; Load_x : IN STD_LOGIC; x_in : IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0); c_in : IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0); y_out : OUT STD_LOGIC_VECTOR(W4-1 DOWNTO 0);END fir_gen;ARCHITECTURE flex OF fir_gen IS

9、 SUBTYPE N1BIT IS STD_LOGIC_VECTOR(W1-1 DOWNTO 0); SUBTYPE N2BIT IS STD_LOGIC_VECTOR(W2-1 DOWNTO 0); SUBTYPE N3BIT IS STD_LOGIC_VECTOR(W3-1 DOWNTO 0); TYPE ARRAY_N1BIT IS ARRAY (0 TO L-1) OF N1BIT; TYPE ARRAY_N2BIT IS ARRAY (0 TO L-1) OF N2BIT; TYPE ARRAY_N3BIT IS ARRAY (0 TO L-1) OF N3BIT; SIGNAL x

10、 : N1BIT; SIGNAL y : N3BIT; SIGNAL c : ARRAY_N1BIT; - Coefficient array SIGNAL p : ARRAY_N2BIT; - Product array SIGNAL a : ARRAY_N3BIT; - Adder array FIR濾波器VHDL設(shè)計(jì)（4）BEGIN Load: PROCESS - Load data or coefficient BEGIN WAIT UNTIL clk = 1; IF (Load_x = 0) THEN c(L-1) = c_in; - Store coefficient in reg

11、ister FOR I IN L-2 DOWNTO 0 LOOP - Coefficients shift one c(I) = c(I+1); END LOOP; ELSE x Compute sum-of-products BEGIN IF clkevent and (clk = 1) THEN FOR I IN 0 TO L-2 LOOP - Compute the transposed a(I) = (p(I)(W2-1) & p(I) + a(I+1); - filter adds END LOOP; a(L-1) = p(L-1)(W2-1) & p(L-1); -

12、 First TAP has END IF; - only a register y W1, LPM_WIDTHB = W1, LPM_PIPELINE = Mpipe, LPM_REPRESENTATION = SIGNED, LPM_WIDTHP = W2, LPM_WIDTHS = W2) PORT MAP ( clock = clk, dataa = x, datab = c(I), result = p(I); END GENERATE; y_out Interface PORT (clk : IN STD_LOGIC; x : IN BYTE; y : OUT BYTE);END

13、fir_srg;ARCHITECTURE flex OF fir_srg IS SIGNAL tap : ARRAY_BYTE; - Tapped delay line of bytes直接FIR濾波器設(shè)計(jì)舉例（3）BEGIN p1: PROCESS - Behavioral Style BEGIN WAIT UNTIL clk = 1; - Compute output y with the filter coefficients weight. - The coefficients are -1 3.75 3.75 -1. - Division for Altera VHDL is onl

14、y allowed for - powers-of-two values! y = 2 * tap(1) + tap(1) + tap(1) / 2 + tap(1) / 4 + 2 * tap(2) + tap(2) + tap(2) / 2 + tap(2) / 4 - tap(3) - tap(0); FOR I IN 3 DOWNTO 1 LOOP tap(I) = tap(I-1); - Tapped delay line: shift one END LOOP; tap(0) Interface PORT (clk : IN STD_LOGIC; x_in0, x_in1, x_i

15、n2 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); y : OUT INTEGER RANGE 0 TO 63);END dafsm;DA-FIR VHDL設(shè)計(jì)（2）ARCHITECTURE flex OF dafsm IS TYPE STATE_TYPE IS (s0, s1); SIGNAL state : STATE_TYPE; SIGNAL x0, x1, x2, table_in : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL table_out : INTEGER RANGE 0 TO 7;BEGIN table_in(0) =

16、 x0(0); table_in(1) = x1(0); table_in(2) DA in behavioral style VARIABLE p : INTEGER RANGE 0 TO 63;- temp. register VARIABLE count : INTEGER RANGE 0 TO 3; - counts shifts BEGIN WAIT UNTIL clk = 1; CASE state IS WHEN s0 = - Initialization step state = s1; count := 0; p := 0; x0 = x_in0; x1 = x_in1; x

17、2 - Processing step IF count = 3 THEN - Is sum of product done ? y = p; - Output of result to y and state = s0; - start next sum of product ELSE p := p / 2 + table_out * 4; x0(0) = x0(1); x0(1) = x0(2); x1(0) = x1(1); x1(1) = x1(2); x2(0) = x2(1); x2(1) = x2(2); count := count + 1; state table_in, t

18、able_out = table_out);END flex;DA-FIR VHDL設(shè)計(jì)（4） 系數(shù)2, 3, 1的DA算法LUT實(shí)現(xiàn)LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;ENTITY case3 IS PORT ( table_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0); table_out : OUT INTEGER RANGE 0 TO 6);END case3;ARCHITECTURE LCs OF case3 ISBEGIN- This is the D

19、A CASE table for- the 3 coefficients: 2, 3, 1 - automatically generated with dagen.exe - DO NOT EDIT! DA-FIR VHDL設(shè)計(jì)（5）PROCESS (table_in) BEGIN CASE table_in IS WHEN 000 = table_out table_out table_out table_out table_out table_out table_out table_out table_out = 0; END CASE; END PROCESS;END LCs;基于邏輯

20、單元的DA-FIR實(shí)現(xiàn)l低階FIR濾波器實(shí)現(xiàn)采用小規(guī)模LUT （FIR階數(shù)L4） ，用邏輯單元實(shí)現(xiàn)LUTl高階FIR濾波器實(shí)現(xiàn)像構(gòu)造低階FIR一樣直接用邏輯單元實(shí)現(xiàn)大規(guī)模LUT會(huì)造成邏輯單元資源緊張，例如2bb規(guī)模LUT利用FIR濾波器線性相位特性，可以將低階FIR的輸出相加構(gòu)成高階FIR的輸出響應(yīng)LUT實(shí)現(xiàn)方式：利用FPGA內(nèi)部存儲(chǔ)模塊，如M4K，實(shí)現(xiàn)LUT。優(yōu)點(diǎn)：運(yùn)算速度恒定，節(jié)省布線資源；問(wèn)題：M4K數(shù)量較少，應(yīng)該節(jié)約使用！利用小規(guī)模LUT（4輸入）和多路選擇器構(gòu)成總線結(jié)構(gòu)實(shí)現(xiàn)較大規(guī)模LUT1.將較大規(guī)模LUT劃分成若干小規(guī)模LUT實(shí)現(xiàn)基于邏輯單元的DA-FIR不同實(shí)現(xiàn)方式比較5輸入DA

21、表（1）LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;ENTITY case5p IS PORT ( clk : IN STD_LOGIC; table_in : IN STD_LOGIC_VECTOR(4 DOWNTO 0); table_out : OUT INTEGER RANGE 0 TO 25);END case5p;ARCHITECTURE LEs OF case5p IS SIGNAL lsbs : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL msbs0 :

22、 STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL table0out00, table0out01 : INTEGER RANGE 0 TO 25;BEGIN- These are the distributed arithmetic CASE tables for- the 5 coefficients: 1, 3, 5, 7, 9- automatically generated with dagen.exe - DO NOT EDIT!5輸入DA表（2） PROCESS BEGIN WAIT UNTIL clk = 1; lsbs(0) = table_in(0

23、); lsbs(1) = table_in(1); lsbs(2) = table_in(2); lsbs(3) = table_in(3); msbs0(0) = table_in(4); msbs0(1) table_out table_out table_out table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out00 table0out

24、00 table0out00 table0out00 table0out00 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 table0out01 INTEGER ENTITY darom IS - Interface PORT (clk : IN STD_LO

25、GIC; x_in0, x_in1, x_in2 : IN STD_LOGIC_VECTOR(2 DOWNTO 0); y : OUT INTEGER RANGE 0 TO 63);END darom;ARCHITECTURE flex OF darom IS TYPE STATE_TYPE IS (s0, s1); SIGNAL state : STATE_TYPE; SIGNAL x0, x1, x2, table_in, mem : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL table_out : INTEGER RANGE 0 TO 7;采用M4K實(shí)現(xiàn)D

26、A FIR 濾波器（2）BEGIN table_in(0) = x0(0); table_in(1) = x1(0); table_in(2) DA in behavioral style VARIABLE p : INTEGER RANGE 0 TO 63; -Temp. register VARIABLE count : INTEGER RANGE 0 TO 3; BEGIN - Counts the shifts WAIT UNTIL clk = 1; CASE state IS WHEN s0 = - Initialization step state = s1; count := 0

27、; p := 0; x0 = x_in0; x1 = x_in1; x2 - Processing step IF count = 3 THEN - Is sum of product done ? y = p; - Output of result to y and state = s0; - start next sum of product ELSE p := p / 2 + table_out * 4; x0(0) = x0(1); x0(1) = x0(2); x1(0) = x1(1); x1(1) = x1(2); x2(0) = x2(1); x2(1) = x2(2); co

28、unt := count + 1; state 3, LPM_WIDTHAD = 3, LPM_OUTDATA = UNREGISTERED, LPM_ADDRESS_CONTROL = UNREGISTERED, LPM_FILE = darom3.mif) PORT MAP ( address = table_in, q = mem); table_out Interface PORT (clk : IN STD_LOGIC; x_in0, x_in1, x_in2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); y : OUT INTEGER RANGE -64 T

29、O 63);END dasign;有符號(hào)DA FIR濾波器設(shè)計(jì)（2）ARCHITECTURE flex OF dasign IS TYPE STATE_TYPE IS (s0, s1); SIGNAL state : STATE_TYPE; SIGNAL table_in : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL x0, x1, x2 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL table_out : INTEGER RANGE -2 TO 4;BEGIN table_in(0) = x0(0); table_in(1) =

30、 x1(0); table_in(2) DA in behavioral style VARIABLE p : INTEGER RANGE -64 TO 63;- Temporary reg. VARIABLE count : INTEGER RANGE 0 TO 4; - Counts the BEGIN - shifts WAIT UNTIL clk = 1; CASE state IS WHEN s0 = - Initialization step state = s1; count := 0; p := 0; x0 = x_in0; x1 = x_in1; x2 - Processin

31、g step IF count = 4 THEN - Is sum of product done? y = p; - Output of result to y and state = s0; - start next sum of product ELSE IF count = 3 THEN - Subtract for last p := p / 2 - table_out * 8; - accumulator step ELSE p := p / 2 + table_out * 8; - Accumulation for END IF; - all other steps FOR k

32、IN 0 TO 2 LOOP - Shift bits x0(k) = x0(k+1); x1(k) = x1(k+1); x2(k) = x2(k+1); END LOOP; count := count + 1; state table_in, table_out = table_out);END flex;有符號(hào)DA FIR濾波器設(shè)計(jì)（4） LE表LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;ENTITY case3s IS PORT ( table_in : IN STD_LOGIC_VECT

33、OR(2 DOWNTO 0); table_out : OUT INTEGER RANGE -2 TO 4);END case3s;ARCHITECTURE LEs OF case3s ISBEGIN- This is the DA CASE table for- the 3 coefficients: -2, 3, 1- automatically generated with dagen.exe - DO NOT EDIT! 有符號(hào)DA FIR濾波器設(shè)計(jì)（5）PROCESS (table_in) BEGIN CASE table_in IS WHEN 000 = table_out table_out table_out table_out table_out table_out table_out table_out table_out Interface PORT (clk : IN STD_LOGIC; x_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); y : OUT INTEGER RANGE -46 TO 44);END dapara;展開(kāi)結(jié)構(gòu)DA-FIR VHDL 設(shè)計(jì)（2）ARCHITECTURE flex OF dapara IS SIGNAL x0, x1, x2, x3 : STD_LOGIC_VECTOR(2 DOW