可編程邏輯實驗報告

1、西安郵電大學(xué)可編程邏輯實驗報告系 別電院學(xué) 號成 績班 級光電1104班姓 名教師簽字 實驗名稱 用原理圖輸入法設(shè)計門電路一：實驗?zāi)康?. 掌握PLD芯片的基本使用方法，熟悉EDA軟件MAX+PLUS操作。2. 學(xué)會利用軟件方針和硬件實現(xiàn)對數(shù)字電路的邏輯功能進行驗證和分析。3. 能夠利用CPLD器件開發(fā)具有基本與非邏輯功能的數(shù)字電路。二：實驗所用儀表及主要器材PC， EDA軟件MAX+PLUS。三：實驗原理簡述（原程序、真值表、原理圖）及實驗測量記錄（數(shù)據(jù)、仿真波形圖及分析、原程序分析、硬件測試實分析）實驗一：用原理圖輸入法實現(xiàn)F=和F=AB+CD邏輯電路，要求原理圖輸入、 編譯并仿真。 (1

2、)F=ABF001011101110真值表 仿真結(jié)果圖 (2) F=AB+CD 真值表ABCDF00000000100010000111010000101001100011111000010010101001011111001110111110111111仿真結(jié)果圖 西安郵電大學(xué)可編程邏輯實驗報告系 別電院學(xué) 號成 績班 級光電1104班姓 名雷曉丹教師簽字 實驗名稱 用文本輸入法設(shè)計門電路一：實驗?zāi)康?.進一步熟悉MAX+plus II軟件，學(xué)習(xí)用文本輸入法設(shè)計電路。 2.進一步熟悉 CPLD 數(shù)字電路設(shè)計流程。 3.學(xué)習(xí)初步的 VHDL 程序設(shè)計方法。二：實驗所用儀表及主要器材 PC，可編

3、程邏輯電路板，下載線，USB電源線，雙蹤示波器，數(shù)字萬用表，導(dǎo)線若干三：實驗原理簡述（原程序、真值表、原理圖）及實驗測量記錄（數(shù)據(jù)、仿真波形圖及分析、原程序分析、硬件測試實分析）實驗二：用VHDL實現(xiàn)或非門、同或門。(1) 或非門F= 真值表ABF001010100110 原程序library ieee;use ieee.std_logic_1164.all;entity nor2 isport(a,b:in std_logic; y:out std_logic );end;architecture rel_1 of nor2 isbegin y<=a nor b ;end;仿真結(jié)果圖(

4、2) 同或門F= 真值表ABF001010100111原程序library ieee;use ieee.std_logic_1164.all;entity xnor2 isport(a,b:in std_logic; y:out std_logic );end;architecture rel_1 of xnor2 issignal h:std_logic;begin h<=a xor b ; y<=not h;end;仿真結(jié)果圖實驗三：（1）多數(shù)表決電路設(shè)計：當(dāng)輸入A、B、C、D有3個或3個以上為1時輸出F為1；輸入為其他狀態(tài)時輸出為0。 真值表ABCDF000000001000

5、10000110010000101001100011111000010010101001011111000110111110111111原程序library ieee;use ieee.std_logic_1164.all;entity text6 isport(a:in std_logic_vector(3 downto 0); y:out std_logic );end;architecture rel of text6 isbegin process(a) begin case a is when"0000"=>y<='0' when&qu

6、ot;0001"=>y<='0' when"0010"=>y<='0' when"0011"=>y<='0' when"0100"=>y<='0' when"0101"=>y<='0' when"0110"=>y<='0' when"0111"=>y<='1' when&q

7、uot;1000"=>y<='0' when"1001"=>y<='0' when"1010"=>y<='0' when"1011"=>y<='1' when"1100"=>y<='0' when"1101"=>y<='1' when"1110"=>y<='1' when&

8、quot;1111"=>y<='1' when others=>y<='Z' end case; end process;end;仿真結(jié)果圖（2）代碼轉(zhuǎn)換電路設(shè)計：要求輸入為8421BCD碼，輸出為余3碼。 代碼轉(zhuǎn)換電路代碼轉(zhuǎn)換表數(shù)字輸入（8421BCD碼）輸出（余3碼）數(shù)字輸入（8421BCD碼）輸出（余3碼）X3X2X1X0Y3Y2Y1Y0X3X2X1X0Y3Y2Y1Y0012340000000100100011010000110100010101100111567890101011001111000100110001001

9、101010111100原程序use ieee.std_logic_1164.all;entity daima isport(a:in std_logic_vector(3 downto 0); y:out std_logic_vector(3 downto 0) );end;architecture rel of daima isbegin process(a) begin case a is when"0000"=>y<="0011" when"0001"=>y<="0100" when

10、"0010"=>y<="0101" when"0011"=>y<="0110" when"0100"=>y<="0111" when"0101"=>y<="1000" when"0110"=>y<="1001" when"0111"=>y<="1010" when"1000&q

11、uot;=>y<="1011" when"1001"=>y<="1100" when others=>y<="ZZZZ" end case; end process;end;仿真結(jié)果圖實驗四：設(shè)計一個二個2位二進制數(shù)相乘電路。A0A1A2A3Y000000000001000000100000001100000100000001010001011000100111001110000000100100101010010010110110110000001101001111100110

12、11111001原程序library ieee;use ieee.std_logic_1164.all;entity liangcheng isport(a:in std_logic_vector(3 downto 0); y:out std_logic_vector(3 downto 0) );end;architecture rel of liangcheng isbeginprocess(a) begin case a is when"0000"=>y<="0000" when"0001"=>y<=&qu

13、ot;0000" when"0010"=>y<="0000" when"0011"=>y<="0000" when"0100"=>y<="0000" when"0101"=>y<="0001" when"0110"=>y<="0010" when"0111"=>y<="0011"

14、; when"1000"=>y<="0000" when"1001"=>y<="0010" when"1010"=>y<="0100" when"1011"=>y<="0110" when"1100"=>y<="0000" when"1101"=>y<="0011" when"

15、1110"=>y<="0110" when"1111"=>y<="1001" when others=>y<="ZZZZ" end case; end process;end;仿真結(jié)果圖實驗五：數(shù)碼管驅(qū)動電路。 真值表輸入輸出數(shù)字A3A2A1A0YaYbYcYdYeYfYg字型01234567891011121314150000000100100011010001010110011110001001101010111100110111101111101111012345

16、6789ABCDEF原程序library ieee;use ieee.std_logic_1164.all;entity bawei isport(a:in std_logic_vector(3 downto 0); y:out std_logic_vector(6 downto 0) );end;architecture rel of bawei isbegin process(a) begin case a is when"0000"=>y<="1111110" when"0001"=>y<="0

17、110000" when"0010"=>y<="1101101" when"0011"=>y<="1111001" when"0100"=>y<="0110011" when"0101"=>y<="1011011" when"0110"=>y<="1011111" when"0111"=>y<=&

18、quot;1110000" when"1000"=>y<="1111111" when"1001"=>y<="1110111" when"1010"=>y<="1110110" when"1011"=>y<="0011111" when"1100"=>y<="1001110" when"1101"=>y

19、<="0111110" when"1110"=>y<="1001111" when"1111"=>y<="1000111" when others=>y<="ZZZZ" end case; end process;end;仿真結(jié)果圖實驗六：(1)JK觸發(fā)器 JK觸發(fā)器功能表 CP J K Q01XXX10XXX00XXX1100111011011111101Hold10Toggle原程序library ieee;use ieee.st

20、d_logic_1164.all;entity jk isport(j,k,prn,clrn,cp:in std_logic; y,yb:out std_logic );end;architecture rtl of jk issignal y_temp:std_logic;begin process(prn,cp) begin if (prn='0') then y_temp<='1' elsif clrn='0' then y_temp<='0' elsif(cp'event and cp='1&#

21、39;)then if j='1' and k='1' then y_temp<=not y_temp; end if; if j='1' and k='0' then y_temp<='1' end if; if j='0' and k='1' then y_temp<='0' end if; if j='0' and k='0' then y_temp<=y_temp; end if; end if; end

22、 process; y<=y_temp; yb<=not y_temp;end;仿真結(jié)果圖(2) D觸發(fā)器 D觸發(fā)器功能表 Clk D Q01XX10XX00XX111110110X10110Hold原程序library ieee;use ieee.std_logic_1164.all;entity d isport(d,prn,clrn,cp:in std_logic; q,qb:out std_logic );end;architecture rtl of d issignal q_temp:std_logic;begin process(prn,cp) begin if (p

23、rn='0') then q_temp<='1' elsif clrn='0' then q_temp<='0' elsif(cp'event and cp='1')then q_temp<=d; end if; end process; q<=q_temp; qb<=not q_temp;end;仿真結(jié)果圖實驗七：(1)設(shè)計一個能自啟動的環(huán)形計數(shù)器，實現(xiàn)如圖所示狀態(tài)轉(zhuǎn)換圖。 0010 0001 0100 1000 原程序library ieee;use ieee.std_lo

24、gic_1164.all;entity ztzh isport(cp:in std_logic; y:buffer std_logic_vector(3 downto 0) );end;architecture rtl of ztzh isbegin process(cp) begin if(cp'event and cp='1')then case y is when"0001"=>y<="1000" when"0010"=>y<="0001" when"

25、0100"=>y<="0010" when"1000"=>y<="0100" when others=>y<="1000" end case; end if; end process; end;仿真結(jié)果圖實驗八：設(shè)計一個同步帶清零、帶有進位輸出端的二十四進制（8421BCD）計數(shù)器，且能夠自啟動及具有進位端輸出。原程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ershisi isport(rd,ep,