集成電路封裝介紹（精品ＰＰＴ）

1、w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o m集成電路封裝 港灣網絡通用IC組w w w . h a r b o u r n e t w o r k s . c o m 封裝功能n封裝的定義：內含一個或多個半導體芯片的一種外殼，可提供電連接及機械和環(huán)境保護n封裝的發(fā)展趨勢：更多的引腳數(shù)，更大的熱耗散，更高的封裝密度和多芯片封裝，以便改進電子系統(tǒng)的性能，使其具有更多的功能及更強的能力。w w w . h a r b o u r n e t w o r k s .

2、c o m 與封裝相關的常用參數(shù)nATAB TAB焊球陣列 TAB ball grid arraynBGA 焊球陣列 Ball grid arraynCC 片式載體 Chip carriernC4 受控塌陷芯片連接 nCERDIP 玻璃熔封陶瓷雙列直插封裝 nCMOS 互補金屬氧化物半導體nCQFP 陶瓷四邊引線扁平封裝nDIP 雙列直插封裝 Dual in-line packagenECL 射級耦合邏輯nFQFP 窄節(jié)距四邊引線扁平封裝 Fine pitch quad flat packnLCC 無引線片式載體 Leadless chip carrierw w w . h a r b o u

3、 r n e t w o r k s . c o mnLCC 無引線片式載體 Leadless chip carriernLGA 面或無引線焊點陣列 Leadless(land) grid arraynLSI 大規(guī)模集成 nMCM 多芯片模塊 Multichip modulenMCP 多芯片封裝nMSI 中規(guī)模集成nPBGA 塑球焊球陣列 Plastic ball grid arraynPGA 針柵陣列 Pin grid arraynPLCC 塑料有引線片式載體 Plastic leaded chip carriernPWB 印制線路板 nQFP 四邊引線扁平封裝 Quad flat pack

4、nQUIP 四邊直插封裝 Quad in-line packagenSIMM 單邊直插存儲器模塊 Singe in-line memory modulenSIP 單列直插 Single in-line packagenSMTPGA 表面安裝針柵陣列 Surface mount pin grid arrayw w w . h a r b o u r n e t w o r k s . c o mnSO 小外形 Small outlinenSOJ J形引線的SOP Small outline J leadnSOP 小外形封裝 Sop outline packagenSOT 小外形晶體管 nSSOP

5、 縮小的小外形封裝 Shrink small outline packagenSOIC 小外形IC Small outline ICnTAB 載帶自動焊 Metric TABnTCE 熱膨脹系數(shù)nTCM 導熱模塊nTQFP 薄形四邊引線扁平封裝 Thin quad flat packnTSOP 薄形小外形封裝 Thin small outline packagenTSSOP 薄形縮小的小外形封裝 Thin shrink small outline packagenVLSI 超大規(guī)模集成nZIF 零插入力nZIP 單邊交叉雙列直插封裝 Zig-zag in-line packagew w w .

6、 h a r b o u r n e t w o r k s . c o m 集成電路發(fā)展歷程封裝類型縮寫詞60年代70年代80年代90年代雙列直插封裝DIPYYYY扁平封裝FPYYY片式載體CC無引線片式載體LCCYYYY塑料有引線片式載體PLCCYYY柵陣列針柵陣列PGAYYYYw w w . h a r b o u r n e t w o r k s . c o m封裝類型縮寫詞60年代70年代80年代90年代無引線（面）柵陣列LGAYY小外形或小外形ICSO或SOICYYY小外形J形引線SOJYY載帶自動焊TABYYY列直插封裝單列直插封裝SIPYYYY單邊交叉雙列直插封裝ZIPYYY

7、四邊單列直插封裝QUIPYYY單列直插存儲器模塊SIMM（SIP）YYw w w . h a r b o u r n e t w o r k s . c o m封裝類型縮寫詞60年代70年代80年代90年代四邊引線扁平封裝QFPYYY模塑形載體MRCYY窄節(jié)距四邊引線扁平封裝FQFPY薄形四邊引線扁平封裝TQFPY窄節(jié)距小外形封裝SSOPY薄形縮小的小外形封裝TSSOPY柵陣列Y焊球陣列BGAYw w w . h a r b o u r n e t w o r k s . c o m封裝類型縮寫詞60年代70年代80年代90年代塑料焊球陣列PBGAY載帶自動焊球陣列ATABY表面安裝型針柵陣列

8、SMTPGAY公制的TABTABYY多芯片模塊MCMYYYYMCM針柵陣列MCMPGAYYY縮小的DIPYY多I/O引腳數(shù)SIMMSIMM（SIP）Yw w w . h a r b o u r n e t w o r k s . c o mn微電子封裝一般可分為微電子封裝一般可分為 4級級 ,如圖如圖 所示所示 ,即即 :n0級封裝級封裝芯片上器件本體的互連芯片上器件本體的互連n1級封裝級封裝芯片芯片 (1個或多個個或多個 )上的輸入上的輸入 /輸出與基板互連輸出與基板互連 n2級封裝級封裝將封裝好的元器件或多芯片將封裝好的元器件或多芯片組件用多層互連布線板組件用多層互連布線板 ()組裝成電組

9、裝成電子部件子部件 ,插件或小整機插件或小整機n3級封裝級封裝用插件或小整機組裝成機柜用插件或小整機組裝成機柜整機系統(tǒng)整機系統(tǒng)w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o m半導體制造裝備概述n芯片制造（前道）芯片制造（前道） 單晶硅拉制、切片、表面處理、光刻、減薄、單晶硅拉制、切片、表面處理、光刻、減薄、劃片劃片n 芯片封裝（后道）芯片封裝（后道） 測試、測試、 滴膠、滴膠、Die bonding、Wire bonding、壓模壓模w w w . h a r b

10、 o u r n e t w o r k s . c o mn 半導體封裝的基本形式半導體封裝的基本形式n雙列直插式封裝雙列直插式封裝 ()n表面安裝技術表面安裝技術 () 無引線陶瓷片式載體無引線陶瓷片式載體() 塑料有引線片式載體塑料有引線片式載體 () 四邊引線扁平封裝四邊引線扁平封裝 () 四邊引線塑料扁平封裝四邊引線塑料扁平封裝 ()n平面陣列型平面陣列型 (）n球柵陣列封裝球柵陣列封裝 ()w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w .

11、 h a r b o u r n e t w o r k s . c o mChip to substrate interconnect technologiesw w w . h a r b o u r n e t w o r k s . c o m將帶引線的芯片從載帶上切下的示意圖外引線鍵合過程示意圖w w w . h a r b o u r n e t w o r k s . c o m技術中的載帶w w w . h a r b o u r n e t w o r k s . c o mn概括而言 ,電子封裝技術已經歷了四代 ,現(xiàn)正在進入第五代。n第一代 ： 60年代前采用的是接線板焊接

12、的方式 ,框架為電路板 ,主要插裝元件是電子管。n第二代 ：60年代采用穿孔式印刷電路板()封裝 ,主要元件是晶體管和柱型元件。n第三代 ：70年代用自動插裝方式將為代表的集成電路封裝在板上 ,這是穿孔式封裝技術的全盛時期。n第四代 ：從 80年代開始 ,采用將表面安裝元件 ()和表面安裝器件 ()安裝在表面上。這一封裝技術的革命改變了元器件和電子產品的面貌。n第五代 ：這是 90年代顯露頭角的微封裝技術 ,是上一代封裝技術的發(fā)展和延伸 ,是將多層技術、高密度互連技術、微型元器件封裝技術綜合并發(fā)展 ,其代表性技術就是金屬陶瓷封裝 (),典型產品是M。最近由于系統(tǒng)級芯片 ()和全片規(guī)模集成 ()

13、技術的發(fā)展 ,微電子封裝技術正孕育著重大的突破w w w . h a r b o u r n e t w o r k s . c o mn向表面安裝技術向表面安裝技術 ()發(fā)展發(fā)展n1988年技術約占封裝市場份額的年技術約占封裝市場份額的17.5% , 1 993年占年占 44% , 1 998年占年占 75%。傳統(tǒng)的雙列直插。傳統(tǒng)的雙列直插封裝所占份額越來越小封裝所占份額越來越小 ,取而代之的是表面安裝取而代之的是表面安裝類型的封裝類型的封裝 ,如有引線塑料片式載體如有引線塑料片式載體 ,無引線陶瓷無引線陶瓷片式載體片式載體 ,四邊引線塑料扁平封裝四邊引線塑料扁平封裝 ,塑料球柵陣列塑料球柵

14、陣列封裝封裝 ()和陶瓷球柵陣列封裝和陶瓷球柵陣列封裝 ()等等 ,尤其是和兩種類型最具典型尤其是和兩種類型最具典型.w w w . h a r b o u r n e t w o r k s . c o mn向高密度發(fā)展向高密度發(fā)展n目前目前 ,陶瓷外殼陶瓷外殼 ()已達已達 1089只管只管腳、達腳、達 625只管腳、間距達只管腳、間距達 0.5、達、達 376只管腳、達只管腳、達 1 0 0 0只管腳。只管腳。n根據(jù)美國發(fā)展規(guī)劃根據(jù)美國發(fā)展規(guī)劃 ,到到 2 0 0 7年年 ,最最大芯片尺寸將增大到大芯片尺寸將增大到 1 0 0 0*2 ,同時每同時每枚芯片上的輸入枚芯片上的輸入 /輸出數(shù)

15、最多將達到輸出數(shù)最多將達到 50 0 0個個 ,焊點尺寸將縮小到焊點尺寸將縮小到 0.127以下以下w w w . h a r b o u r n e t w o r k s . c o m從單芯片封裝向多芯片封裝發(fā)展從單芯片封裝向多芯片封裝發(fā)展起步于起步于 90年代初年代初 ,由于的高密度、高性能由于的高密度、高性能和高可靠性而倍受青睞。受到世界各國的極大關注和高可靠性而倍受青睞。受到世界各國的極大關注 ,紛紛紛投入巨額資金紛投入巨額資金 ,如美國政府如美國政府 3年投入年投入 5億美元億美元 ,在在 1 0年投入年投入 1 0億美元來發(fā)展億美元來發(fā)展 ,據(jù)預測據(jù)預測 , 1 999年全球產

16、品銷售額將達年全球產品銷售額將達 2 0 0億美元。目前最高億美元。目前最高水平的水平的是的產品是的產品 ,2 0 0*2 、78層、層、3 0 0多萬個通孔多萬個通孔 , 1 40 0互連線互連線 , 1 80 0只管腳只管腳 , 2 0 0功耗功耗w w w . h a r b o u r n e t w o r k s . c o m由陶瓷封裝向塑料封裝發(fā)展由陶瓷封裝向塑料封裝發(fā)展在陶瓷封裝向高密度在陶瓷封裝向高密度 ,多引線和低功耗展的同時多引線和低功耗展的同時 ,越來越多的領域正在由塑料封裝所取代。而且越來越多的領域正在由塑料封裝所取代。而且 ,新的塑料封裝形式層出不窮新的塑料封裝形

17、式層出不窮 ,目前以和目前以和為主為主 ,全部用于表面安裝全部用于表面安裝 ,這些塑料封裝這些塑料封裝占領著占領著 90 %以上的市場以上的市場w w w . h a r b o u r n e t w o r k s . c o m高密度封裝中的關鍵技術高密度封裝中的關鍵技術從技術發(fā)展觀點來看從技術發(fā)展觀點來看 ,作為高密度封裝的關鍵技術主要作為高密度封裝的關鍵技術主要有有 : , , , ,和三維封裝和三維封裝載帶封裝載帶封裝它可以提供超窄的引線間距和很薄的封裝外形它可以提供超窄的引線間距和很薄的封裝外形 ,且在板上占據(jù)很小的面積且在板上占據(jù)很小的面積 ,可用于高可用于高/數(shù)的數(shù)的和微處理

18、器和微處理器 ,東芝公司東芝公司1 996年問世的筆記年問世的筆記本電腦中就使用了承載本電腦中就使用了承載 ,其引線間距其引線間距 0.2 5 ,焊接精度為焊接精度為 3 0 ,據(jù)報道據(jù)報道 ,最小間距最小間距可達可達 0.1 5w w w . h a r b o u r n e t w o r k s . c o m球柵陣列封裝球柵陣列封裝(BGA)技術的最大特點是器件與板之間的互連由引線改為小球 ,制作小球的材料通常采用合金焊料或有機導電樹脂。采用技術容易獲得/數(shù)超過 60 0個的封裝體。由于完全采用與相同的回流焊工藝 ,避免了中的超窄間距 ,可以提供較大的焊盤區(qū) ,因此使焊接工藝更加簡單

19、 ,強度大大提高 ,可靠性明顯改善w w w . h a r b o u r n e t w o r k s . c o m的尺寸通常大于(芯片規(guī)模封裝 ),在 2 1 40之間?？煞譃樗芰?)、陶瓷()或載帶()。在中 ,通常用引線鍵合采用焊球或引線鍵合將芯片貼在陶瓷基板上 ;在中 ,用標準內引線鍵合工藝或焊球將芯片貼在其帶狀框架上w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c

20、o m 芯片規(guī)模封裝與芯片尺寸封裝芯片規(guī)模封裝與芯片尺寸封裝 ()芯片規(guī)模封裝與芯片尺寸封裝統(tǒng)稱為芯片規(guī)模封裝與芯片尺寸封裝統(tǒng)稱為 ,它被認為是它被認為是本世紀先進封裝的主流技術。在芯片規(guī)模封裝中本世紀先進封裝的主流技術。在芯片規(guī)模封裝中 ,封裝體封裝體的尺寸是芯片尺寸的的尺寸是芯片尺寸的 1.2倍以下倍以下 ;芯片尺寸封裝中封裝芯片尺寸封裝中封裝體的尺寸與芯片尺寸基本相當。這是在電路板面積不變的體的尺寸與芯片尺寸基本相當。這是在電路板面積不變的前提下前提下 ,希望更換大芯片的集成電路時提出的。在這種情希望更換大芯片的集成電路時提出的。在這種情況下況下 ,將框架引線伸展到芯片上方形成芯片引線將

21、框架引線伸展到芯片上方形成芯片引線 (),封裝尺寸不變封裝尺寸不變 ,芯片面積增大芯片面積增大 ,封裝體面積與芯片面積的比封裝體面積與芯片面積的比值變小值變小w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o m多芯片組件多芯片組件 ( )將多只合格的裸芯片將多只合格的裸芯片 ()直接封裝在多層互連基板直接封裝在多層互連基板上上 ,并與其它元器件一起構成具有部件或系統(tǒng)功能的多芯并與其它元器件一起構成具有部件或系統(tǒng)功能的多芯片組件片組件 (),已成為蜚聲全球的已成為蜚聲全

22、球的 90年代代表性技術。年代代表性技術。w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mMCM封裝封裝w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mDie Bondingw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k

23、s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mHistory and applications of wirebondingWirebonding is the earliest technique of device assembly, whose first result was published by Bell Laboratories in 1957. Sine then, the technique has been extreme

24、ly developedw w w . h a r b o u r n e t w o r k s . c o m AdvantagenFully automatic machines have been developed for volume production.nBonding parameters can be precisely controlled; mechanical properties of wires can be highly reproduced.nBonding speed can reach 100-125 ms per each wire interconne

25、ction (two welds and a wire loop).nMost reliability problems can be eliminated with properly controlled and much improved tools (capillaries and wedges) and processes.nSpecific bonding tools and wires can be selected by packaging engineers to meet the requirements.nInfrastructure of the technique ha

26、s been comprised by large wirebonding knowledge, manufacturing people, equipment venders and materials.w w w . h a r b o u r n e t w o r k s . c o mThe most popular applications that use wirebonding are: Single and multitiered cofired ceramic and plastic ball grid arrays (BGAs), single chip and mult

27、ichip Ceramic and plastic quad flat packages (CerQuads and PQFPs) Chip scale packages (CSPs) Chip on board (COB)Ball bondWedge bondWirebonding的基本形式的基本形式w w w . h a r b o u r n e t w o r k s . c o mFirst and second bond comparison. (A) Ball bonding first bond. (B) Ball bonding second bond: stitch bon

28、d and tail bond. (C) Wedge bonding first bond. (D) Wedge bonding second bond.w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o m Wedge bondthe bonding process can be defined to three major processes: thermocompression bonding (T/C) ultrasonic bonding (U/S)therm

29、osonic bonding (T/S)as shown in Table 1-1w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mBall Bondingw w w . h a r b o u r n e t w o r k s . c o mThe capillaries are typically 1.585 mm in diameter and 11.1 mm long

30、.They have a large entry hole at the top and then the hole tapersdown to a small hole diameter typically between 38-50 mm,w w w . h a r b o u r n e t w o r k s . c o m40-m pad pitch ball andwedge first bond comparison.w w w . h a r b o u r n e t w o r k s . c o mSchematic of different looping. (A)Ba

31、ll bonding looping. (B) Traditional wedge radial bonding looping. (C) Wedge bonding Constant Gap looping.w w w . h a r b o u r n e t w o r k s . c o m40 mm pitch first bond.w w w . h a r b o u r n e t w o r k s . c o m40 mm looping. Short wires are to ground. Long wires are to the leads.w w w . h a

32、r b o u r n e t w o r k s . c o mWedge stitch bonding.w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mLimitation of wirebon

33、dingFor the application of wirebonding method, terminals of chips have to be arranged at the periphery of the chips, otherwise short circuit is easily caused. Therefore, wirebonding technique is difficult for high I/O(500) interconnections.w w w . h a r b o u r n e t w o r k s . c o m Bonding parame

34、tersBonding parameters are extremely important because they control the bonding yield and reliability directly.The key variables for wire bonding include: Bonding force and pressure uniformity Bonding temperature Bonding time Ultrasonic frequency and powerw w w . h a r b o u r n e t w o r k s . c o

35、m Bond designBall bonding Ball size is approximately 2 to 3 times the wire diameter, 1.5 times for small ball applications with fine pitches, and 3 to 4 times for large bond pad application. Bond size should not exceed 3/4 of the pad size, about 2.5 to 5 times the wire diameter, depending on the geo

36、metry and moving direction of capillary during bonding. Loop heights of 150 um are now common, but very depending on the wire diameter and applications. Loop length should be less than 100 times the wire diameter. However, in some cases, high I/Os for instance, wire lengths have to increase to more

37、than 5 mm. The wirebonder must suspend the length of wire between the die and lead frame without vertical sagging or horizontal swaying.w w w . h a r b o u r n e t w o r k s . c o mWedge bonding A high-strength wedge bond is possible even the bond is only 2-3 mm wider than wire diameter. Pad length

38、must support the long dimension of the wedge bond as well as the tail. The pads long axis should be oriented along the intended wire path. Bond pitch must be designed to maintain consistent distance between wires.w w w . h a r b o u r n e t w o r k s . c o m CleaningTo ensure bondability and reliabi

39、lity of wirebond, one of the critical conditions is that the bonding surface must be free of any contaminants. Therefore cleaning is an important work before bonding. The method usually adapted is molecular cleaning method, plasma or UV-ozone cleaning method.w w w . h a r b o u r n e t w o r k s . c

40、 o m Bond evaluationnDestructive bond pull test (Method 2011)nInternal visual (Method 2010; Test condition A and B)nDelay measurements (Method 3003)nNondestructive bond pull test (Method 2023)nBall bond shear testnConstant acceleration (Method 2001; Test condition E)nRandom vibration (Method 2026)nM

41、echanical shock (Method 2002)nStabilization bake (Method 1008)nMoisture resistance (Method 1004)w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mIf both thebonds are at the same level and the hook is appliedat the center, the forces can be representedWhen the

42、 both angles are 30o, the pull force is equal to the breakload. The failure during pull test may occur at one of the five positions in the wirebond structure:A. Lift off first bondB. Wire break at transition first bondC. Wire break mid spanD. Wire break at transition second bondE. Lift off second bo

43、ndWhen properly pulled, the bond should fail at B or D. If failures occur at A, C, or E, then the bonding parameters, metallization, bonding machine, bonding tool, hook, has to be reviewed.w w w . h a r b o u r n e t w o r k s . c o mFlip-Chip Technologyw w w . h a r b o u r n e t w o r k s . c o m

44、Advantages: Smaller size: Smaller IC footprint (only about 5% of that of packaged IC e.g. quad flat pack), reduced height and weight. Increased functionality: The use of flip chips allow an increase in the number of I/O. I/O is not limited to the perimeter of the chip as in wire bonding. An area arr

45、ay pad layout enables more signal, power and ground connections in less space. A flip chip can easily handle more than 400 pads. Improved performance: Short interconnect delivers low inductance, resistance and capacitance, small electrical delays, good high frequency characteristics, thermal path fr

46、om the back side of the die. Improved reliability: Epoxy underfill in large chips ensures high reliability. Flip-chips can reduce the number connections per pin from three to one. Improved thermal capabilities: Because flip chips are not encapsulated, the back side of the chip can be used for effici

47、ent cooling. Low cost: Batch bumping process, cost of bumping decreases, cost reductions in the underfill-processw w w . h a r b o u r n e t w o r k s . c o m Disadvantages: Difficult testing of bare dies. Limited availability of bumped chips. Challenge for PCB technology as pitches become very fine

48、 and bump counts are high. For inspection of hidden joints an X-ray equipment is needed. Weak process compatibility with SMT. Handling of bare chips is difficult. High assembly accuracy needed. With present day materials underfilling process with a considerable curing time is needed. Low reliability

49、 for some substrates. Repairing is difficult or impossible.w w w . h a r b o u r n e t w o r k s . c o m 底部填充工藝 (Underfilling Process）溫度膨脹系數(shù)小于 3 ppm/的硅器件直接同有機物印制線路板 (溫度膨脹系數(shù)在1 8 50 ppm/ )壓接在一起 ,會產生嚴重的熱機應力和疲勞 ,俗稱“熱機失配底部填充料鎖住倒裝片和印制板示意圖w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n

50、 e t w o r k s . c o mFlip chip joining using adhesives (isotropic, anisotropic, nonconductive)w w w . h a r b o u r n e t w o r k s . c o mFlip chip joining by thermocompression.Flip chip thermosonic joiningw w w . h a r b o u r n e t w o r k s . c o mFlip chip bonding using thermocompressionw w w

51、. h a r b o u r n e t w o r k s . c o mFlip chip process by solder joining die preparing (testing, bumping, dicing) substrate preparing (flux application or solder paste printing) pick, alignment and place reflow soldering cleaning of flux residues (optional) underfill dispensing underfill curing.w

52、w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mFlip chip joining using adhesivesw w w . h a r b o u r n e t w o r k s . c o

53、mw w w . h a r b o u r n e t w o r k s . c o mIntroduction to CSP TechnologyDescription of various types of CSPsw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mBall Grid Array (BGA) Technologyw w w . h a r b o u r n e t w o r k s . c o mIt is an IC package f

54、or active devices intended for surface mount applicationsIt is an area array package, i.e. utilizing whole or part of the device footprint for interconnectionsThe interconnections are made of balls (spheres) of most often a solder alloy or sometimes other metals More specifically, the BGA package us

55、ually fulfils the following additional requirements:The length of the package body (most often square) ranges from 7 to 50 mmLead counts over 1000 possible, but 50 to 500 range most common todayThe pitch, i.e center-to-center distance, of the balls is generally between 1.0 and 1.5 mmw w w . h a r b

56、o u r n e t w o r k s . c o mFigure 2. A 160-lead 0.3 mm (11.8 mil) pitch QFP placed on a grid of 1.5 mm pitch spheres (bottom side of a PBGAS225).w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mFigure 5. A cross-

57、section of a Tape (or TAB) BGA - TBGA.w w w . h a r b o u r n e t w o r k s . c o mA cross-section of a Super BGA - SBGA.w w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o

58、mw w w . h a r b o u r n e t w o r k s . c o mw w w . h a r b o u r n e t w o r k s . c o m港灣目前物料屬性表中常見的港灣目前物料屬性表中常見的IC封裝封裝大類料號大類描述封裝類型05/35大類專用IC/接口器件等BGA、EDQUAD TQFP、ESBGA、FF、FG、PBGA、P-DSO、PEB、P-FQFP、PGA、P-HSBGA、PQFP、P-TQFP、QFP06/3911大類邏輯IC/模擬器件SOIC、TSSOP、SO、SOP、SSOP、PLCC、DIP、SOT、QFP、PQFP、LQFP07/3

59、7大類存儲器TSOP、BGA、DIP、PLCC、PQFP、QFP、SO、SOJ、SOP、TQFP、TS0P、11/33/31二三極管/電源調整ICSOT、STC、TO、TSSOP、DIPw w w . h a r b o u r n e t w o r k s . c o m 封裝選型建議大類料號大類描述建議優(yōu)選封裝列舉05/35大類專用IC/接口器件等由于專用IC的唯一性，無法建議優(yōu)選封裝06/3911大類邏輯IC/模擬器件SOIC、TSSOP、PLCC07/37大類存儲器TSOP、BGA、PLCC、TS0P、11/33/31二三極管/電源調整ICSOT、D-PAK、TO、TSSOP、DIP

60、w w w . h a r b o u r n e t w o r k s . c o mn 集成電路芯片封裝技術簡介n自從美國Intel公司1971年設計制造出4位微處a理器芯片以來，在20多年時間內，CPU從Intel4004、80286、80386、80486發(fā)展到Pentium和Pentium，數(shù)位從4位、8位、16位、32位發(fā)展到64位;主頻從幾兆到今天的400MHz以上，接近GHz;CPU芯片里集成的晶體管數(shù)由2000個躍升到500萬個以上;半導體制造技術的規(guī)模由SSI、MSI、LSI、VLSI達到 ULSI。封裝的輸入/輸出（I/O）引腳從幾十根，逐漸增加到幾百根，下世紀初可能達