NVIDIA2016PhysicalDesign筆試

1、NVIDIA Confidential SH-05-A-ASIC PDNVIDIA 2016 Campus RecruitmentExam Test Paper SH-05-A-ASIC PDCover PageTotal pages: 12Exam Duration: 120 minutes* Please answer all the questions in EnglishApplied Position: ASIC Physical Design Engineer Candidate Chinese Full Name/中文名Candidate School Name/畢業(yè)學(xué)校Cand

2、idate ID Number/身份證號(hào)Candidate Contact Number/手機(jī)號(hào)碼Candidate E-mail address/郵箱地址Current Degree/學(xué)歷Bachelor / Master / PhD *Graduation Time/畢業(yè)時(shí)間 / (Year/ Month)Major/專業(yè)The two questions below are used only for reference, they are not criteria for hiring. Please fill in accurately.(以下兩問題僅作為參考信息，不作為新員工錄用標(biāo)

3、準(zhǔn), 請(qǐng)如實(shí)填寫)Availability for Internship before graduation/畢業(yè)前能否作實(shí)習(xí)生(Yes/No)  When will be available for internship/何時(shí)可以開始實(shí)習(xí) 考生守則&注意事項(xiàng)：1. 請(qǐng)確認(rèn)你的座位上的標(biāo)簽與你的姓名，座位編號(hào)及所應(yīng)考的職位符合；試卷首頁(yè)最上方應(yīng)該是你在網(wǎng)上申請(qǐng)職位的名稱，請(qǐng)確認(rèn)這個(gè)職位是你在網(wǎng)上申請(qǐng)的第一志愿的職位，如果不是，請(qǐng)舉手告訴監(jiān)考人員；2. 請(qǐng)檢查試卷是否有漏頁(yè)，總頁(yè)數(shù)請(qǐng)參考試卷封面；3. 試卷封面所有信息須由中文填寫，試卷封面上需要選擇你投遞職位的勾選框

4、，請(qǐng)一定要進(jìn)行勾選；試題部分請(qǐng)用英文作答；答題盡量寫在試題下方的空白處，如果寫不下，再使用附頁(yè)，但須在題目下方進(jìn)行注明；4. 考試期間，如有發(fā)問，請(qǐng)舉手, 如果你需要更多的草稿紙，請(qǐng)舉手通知監(jiān)考員；5. 除了貴重物品隨身攜帶之外，請(qǐng)確認(rèn)你把你的隨行物品放在包包里面，并把你的包包放在課室的最前方；6. 桌上只準(zhǔn)放文具，計(jì)算機(jī)，簡(jiǎn)歷及身份證；把你的身份證及簡(jiǎn)歷放在桌上的右上角，在開考后監(jiān)考員會(huì)查閱7. 請(qǐng)關(guān)閉所有手機(jī)和移動(dòng)設(shè)備，如果你的手機(jī)響起來(lái)，你將會(huì)被取消考試資格；如果需要了解時(shí)間情況，請(qǐng)聯(lián)系你身邊的監(jiān)考人員；8. 開考30分鐘以后不允許進(jìn)場(chǎng)。請(qǐng)注意黑板上所寫的試卷種類，并請(qǐng)核對(duì)確認(rèn)自己所答試

5、卷的考試時(shí)間，這個(gè)時(shí)間應(yīng)該與你試卷上的時(shí)間一致。監(jiān)考人員會(huì)在考試結(jié)束的前15分鐘、5分鐘之時(shí)提醒大家。請(qǐng)注意你的考卷封面的說(shuō)明，如果你拿到的試卷要求用英文作答，請(qǐng)一定要按照要求作答。如果你完成考卷，可以選擇在開考之后一小時(shí)后提早離開，但不可以在收卷之前十五分鐘離 開考場(chǎng)，監(jiān)考員屆時(shí)會(huì)有所宣布(60min考試的同學(xué)不能提前離開考場(chǎng)；90分鐘考試的同學(xué)可以在15：00-15：15pm之間離開；120分鐘考試的同學(xué)可以在15：00-15：45pm之間離開)；否則你會(huì)被視為違反考場(chǎng)紀(jì)律；9. 如果你選擇提早離開，請(qǐng)舉手通知監(jiān)考員，將你的試卷和簡(jiǎn)歷倒扣在桌面上，并攜帶所有帶來(lái)的物品，離開時(shí)請(qǐng)保持安靜；1

6、0. 離開時(shí)不準(zhǔn)攜帶任何的紙張，包括考卷與草稿紙，否則，你將會(huì)被取消資格；11. 考試結(jié)束后，筆試通過(guò)的同學(xué)，在兩個(gè)星期之內(nèi)，會(huì)收到我們的電話通知及安排面試，請(qǐng)留意電話來(lái)電；12. 考生必須嚴(yán)格遵守考試紀(jì)律，請(qǐng)一定誠(chéng)實(shí)作答，不準(zhǔn)交頭接耳或左顧右盼，不準(zhǔn)向其他考生作暗示，不準(zhǔn)偷看、夾帶、代考，不準(zhǔn)抄襲他人答案或有意將自己的答案讓他人抄襲，不準(zhǔn)接傳答案或交換試卷或任何紙張；13. 考卷是NVIDIA的專利財(cái)產(chǎn)之一， 考生嚴(yán)禁在考試后泄露試題。1. Use basic logic gates to implement below RTL code.Available gates: AND/DFF/N

7、OT/ORModule test_logic_1 (A,B,rst_n,clk,Y);input A;input B;input clk;input rst_n;output Y;reg Y;wire gate_en;assigngate_en = A * B;always (posedge clk or negedge rst_n)if (!rst_n)beginY<=1b0;endelse if (gate_en)beginY <= A;endendmodule2. Suppose you have a file, named "vio.txt", that

8、 list 100 timing violations after running STA,  those violations have different attributes, like corners(PVT) and type(setup, hold).  The file format see below, you need to write scripts to analysis the violations status from "vio.txt". <<vio.txt>>: #VioID:  

9、;        corner                    type               slack  Vio1:    

10、          ssg_0c_0p6v        setup              -0.01 Vio2:              ffg_105c_0p72v

11、60; hold                -0.2 Vio100:          ffg_0c_0p99v      setup             -0.04A) 

12、  Get the total setup and hold violation numbers.B)   Get the worst slack of hold violation in each corner.   3. List some methods to decrease power in physical design.4. Please describe the cause reason of metastability in digital circuit design, and how to reduce the possi

13、bility of failure due to metastability.5. Please respectively sort according to the cell delay and leakage power for cell HVT(high vt), SVT (standard vt), LVT (low vt). And whats the problem if we use too many LVT cells in a small area?6. Decide which one is the correct expression for the following

14、pic. a) Y = (!(A1|(!A2)|(!B1)&&B2);b) Y = (!(A1&&(!A2)|(!B1)&&B2);c) Y = (!(A1&&(!A2)&&(!B1)&&B2);d) Y = (!(A1&&(!A2)&&(!B1)|B2);7. There is one path as below:The clock definition is as below:create_clock period 2 name CLK get_ports CLK

15、 waveform 0 1create_generated_clock -name CLKP -edges 2 3 4 -source CLK get_pins CLKPcreate_generated_clock -name CLKM -edges 2 6 10 -source CLK get_pins CLKMPlease draw the waveform picture to show the setup and hold timing check before and after add below exception:set_multicycle_path 2 -setup -fr

16、om get_clocks CLKP -to get_clocks CLKM -startset_multicycle_path 1 -hold -from get_clocks CLKP -to get_clocks CLKM -start8. Please take a look with below path.a) Is it setup violation path or hold violation path? How to identify with it?b) How to fix such violations? (please list 3 ways )Startpoint:

17、 r_nv_ram_rw_18x39_fifola/Ra_reg_r0_reg/Q_reg_2_ (rising edge-triggered flip-flop clocked by xclk)Endpoint: pior1_in_orpix_pd_reg_31_dff_11_ (rising edge-triggered flip-flop clocked by xclk)Path Group: xclkPath Type: maxPoint Fanout Cap DTrans Trans Delta Incr Path-clock xclk (rise edge) 0.000 0.000

18、clock network delay (propagated) 0.636 0.636r_nv_ram_rw_18x39_fifola/Ra_reg_r0_reg/Q_reg_2_/CP (SDFQD1PO3) 0.025 0.000 0.636 rr_nv_ram_rw_18x39_fifola/Ra_reg_r0_reg/Q_reg_2_/Q (SDFQD1PO3) 0.146 0.193 & 0.829 fr_nv_ram_rw_18x39_fifola/Ra_reg_r02 (net) 6 0.021 r_nv_ram_rw_18x39_fifola/U297/A2 (NR2

19、D1) 0.040 0.147 0.014 0.021 & 0.851 fr_nv_ram_rw_18x39_fifola/U297/ZN (NR2D1) 0.083 0.104 & 0.955 rr_nv_ram_rw_18x39_fifola/n209 (net) 2 0.004 r_nv_ram_rw_18x39_fifola/U155/A2 (ND3D1) 0.004 0.083 0.002 0.002 & 0.957 rr_nv_ram_rw_18x39_fifola/U155/ZN (ND3D1) 0.119 0.096 & 1.052 fr_nv_

20、ram_rw_18x39_fifola/n210 (net) 4 0.005 r_nv_ram_rw_18x39_fifola/U702/A2 (NR2D2) 0.013 0.119 0.005 0.005 & 1.057 fr_nv_ram_rw_18x39_fifola/U702/ZN (NR2D2) 0.364 0.245 & 1.302 rr_nv_ram_rw_18x39_fifola/n663 (net) 32 0.052 r_nv_ram_rw_18x39_fifola/U775/A1 (AOI22D0P5HVT) 0.020 0.366 0.008 0.020

21、& 1.322 rr_nv_ram_rw_18x39_fifola/U775/ZN (AOI22D0P5HVT) 0.206 0.275 & 1.597 fr_nv_ram_rw_18x39_fifola/n235 (net) 1 0.003 r_nv_ram_rw_18x39_fifola/U774/A4 (ND4D1) 0.103 0.206 0.037 0.038 & 1.635 fr_nv_ram_rw_18x39_fifola/U774/ZN (ND4D1) 0.062 0.088 & 1.722 rr_nv_ram_rw_18x39_fifola/n

22、239 (net) 1 0.002 r_nv_ram_rw_18x39_fifola/U773/C (AOI211D1) 0.007 0.062 0.003 0.003 & 1.725 rr_nv_ram_rw_18x39_fifola/U773/ZN (AOI211D1) 0.177 0.074 & 1.799 fr_nv_ram_rw_18x39_fifola/n241 (net) 1 0.010 r_nv_ram_rw_18x39_fifola/U123/A3 (CKND3D1) 0.046 0.177 0.017 0.019 & 1.818 fr_nv_ram_

23、rw_18x39_fifola/U123/ZN (CKND3D1) 0.263 0.232 & 2.051 rpior1_in_h1_fifo_rd_data_d11 (net) 2 0.014 U9855/B2 (AO2222D2) 0.174 0.263 0.061 0.064 & 2.114 rU9855/Z (AO2222D2) 0.035 0.156 & 2.270 rpior1_in_N13 (net) 1 0.002 pior1_in_orpix_pd_reg_31_dff_11_/D (SDFQSC2D1HVT) 0.004 0.035 0.002 0.002 & 2.271 rdata arrival time 2.271clock xclk (rise edge) 1.680 1.680clock network delay (propagated) 0.628 2.308clock reconvergence pessimism 0.024 2.331clock uncertainty -0.010 2.321pior1_in_orpix_pd_reg_31_dff_11_/CP (SDFQSC2D1HVT) 2.321 rlibrary setup time