MSP430寄存器詳解

1、/*中斷使能1*/#defi ne IE1_0x0000sfrb IE1=IE1_;#defi ne WDTIE0x01/*看門狗中斷使能*/#defi ne OFIE0x02/*外部晶振故障中斷使能*/#defi ne NMIIE0x10/*非屏敝中斷使能*/#defi ne ACCVIE0x20/*可屏蔽中斷使能/flash 寫中斷錯誤*/#defi ne URXIE00x40/*串口 0接收中斷使能*/#defi ne UTXIE00x80/*串口 0發(fā)送中斷使能*/*劉中斷使能IE1中斷使能IE1UTXIE0URXIE0ACCVIENMIIEOFIEWDTIE/*中斷標志1*/#def

2、i ne IFG1_ sfrb IFG1#defi ne WDTIFG#defi ne OFIFG#defi ne NMIIFG0x0002=IFG1_;0x01/*0x02/*0x10/*看門狗中斷標志*/外部晶振故障中斷標志*/非屏蔽中斷標志*/#defi ne URXIFG00x40/*串口 0接收中斷標志*/#defi ne UTXIFG00x80/*串口 0發(fā)送中斷標志*/中斷標志IFG1UTXIFG0 URXIFG0NMIIFGOFIFG WDTIFG#define ME1_0x0004sfrb ME1=ME1_;#defi ne URXE00x40/*串口 0接收中斷模式使能*/

3、#defi ne USPIE00x40/*同步中斷模式使能*/#defi ne UTXE00x80/*串口 0發(fā)送中斷模式使能*/*中斷模式使能1 */中斷模式使能 ME1中斷模式使能 ME1UTXE0URXE0USPIE0/*中斷使能2 */#defi ne IE2_0x0001sfrb IE2=IE2_;#defi ne URXIE10x10/*串口1接收中斷使能*/#defi ne UTXIE10x20/*串口1發(fā)送中斷使能*/中斷使能IE2中斷使能IE2UTXIE1URXIE1/*中斷標志2 */#defi ne IFG2_ sfrb IFG2#defi ne URXIFG10x000

4、3=IFG2_;0x10/*串口 1接收中斷標志*/中斷標志IFG2UTXIFG1URXIFG1#defi ne UTXIFG10x20/*串口 1發(fā)送中斷標志*/2 */串口 1接收中斷模式使能*/同步中斷模式使能*/串口 1發(fā)送中斷模式使能*/*中斷模式使能#defi ne ME2_sfrb ME2#defi ne URXE1#defi ne USPIE1#defi ne UTXE10x0005=ME2_;0x10/*0x10/*0x20/*中斷模式使UTXE1URXE1USPIE1使能 ME20x5A00/*/*門狗*/#defi ne WDTCTL_0x0120P145sfrw WDT

5、CTL=#defi ne WDTIS0=WDTCTL_;0x0001/*選擇 WDTCN的四個輸出端之一 */#defi neWDTIS10x0002/*選擇 WDTCN的四個輸出端之一 */#defi neWDTSSEL0x0004/*選擇WDTCN的時鐘源*/#defi neWDTCNTCL0x0008/*去除WDTCN端:為1時從0開始計數(shù)*/#defi neWDTTMSEL0x0010/*選擇模式0：看門狗模式；1：定時器模式*/#defi neWDTNMI0x0020/*選擇NMI/RST引腳功能0:為RST; 1:為NMI*/#defi neWDTNMIES0x0040/*WDTN

6、MI=1時.選擇觸發(fā)延0:為上升延1:為下降延*/#defi neWDTHOLD0x0080/*停止看門狗定時器工作0:啟動;1:停止*/看門狗控制存放器WDTCTL口令WDTHOLI)WDTNMIES> WDTNMIWDTTMSEL WDTCNTCL WDTSSE_ WDTIS1WDTIS0寫密碼：高八位*/注：口令15-8:讀取為69H 寫為5AH#defi ne WDTPW/* SMCLK= 1MHz定時器模式*/#defi ne WDT_MDLY_32 WDTPW+WDTTMSEL+WDTCNTCL/* TSMCLK*2POWER15=32m復(fù)位狀態(tài) */#defi ne WDT

7、_MDLY_8 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0/* TSMCLK*2POWER13=8.192ms */#defi ne WDT_MDLY_0_5 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1/* TSMCLK*2POWER9=0.512ms */#defi ne WDT_MDLY_0_064 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0/* TSMCLK*2POWER6=0.512ms */* ACLK=32.768KHz 定時器模式 */#defi ne WDT_ADLY_1000WDTPW+WDTTMSEL+WD

8、TCNTCL+WDTSSEL/* TACLK*2P0WER15=1000ms */#defi ne WDT_ADLY_250WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0/* TACLK*2POWER13=250ms */ #defi ne WDT_ADLY_16 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1/* TACLK*2POWER9=16ms */#defi ne WDT_ADLY_1_9 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0/* TACLK*2POWER6=1.9ms

9、*/* SMCLK=1MHz看門狗模式*/#defi ne WDT_MRST_32 WDTPW+WDTCNTCL/* TSMCLK*2POWER15=32m復(fù)位狀態(tài) */#defi ne WDT_MRST_8 WDTPW+WDTCNTCL+WDTISO/* TSMCLK*2POWER13=8.192ms */#defi ne WDT_MRST_0_5 WDTPW+WDTCNTCL+WDTIS1/* TSMCLK*2POWER9=0.512ms */#defi ne WDT_MRST_0_064 WDTPW+WDTCNTCL+WDTIS1+WDTISO/* TSMCLK*2POWER6=0.51

10、2ms */ /* ACLK=32.768KHz 看門狗模式 */#defi ne WDT_ARST_1OOOWDTPW+WDTCNTCL+WDTSSEL/* TACLK*2POWER15=1000ms */#defi ne WDT_ARST_250WDTPW+WDTCNTCL+WDTSSEL+WDTISO/* TACLK*2POWER13=250ms */#defi ne WDT_ARST_16WDTPW+WDTCNTCL+WDTSSEL+WDTIS1/* TACLK*2POWER9=16ms */#defi ne WDT_ARST_1_9WDTPW+WDTCNTCL+WDTSSEL+WDT

11、IS1+WDTISO根本計時器控制存放器BTSSELBTHOLDBTDIVBTFRFQ1BTFRFQ0BTIP2BTIP1BTIP0/* TACLK*2POWER6=1.9ms */*本定時*/#defi ne BTCTL_(0x0040)/*控制存放器*/MSP430F4X)系列(P148)#defi ne BTIP0(0x01)#defi ne BTIP1(0x02)#defi ne BTIP2(0x04)/*BTIP2-0:定時中斷頻率*/#defi ne BTFRFQ0(0x08)#defi ne BTFRFQ1(0x10)/*輸出fLCD 信號*/#defi ne BTDIV(0x2

12、0)/* fCLK2 :=ACLK:256 */#defi ne BTHOLD(0x40)/* 0:啟動；1:停止*/#defi ne BTSSEL(0x80)/* fBT =fMCLK (mai n clock) */根本計時器控制存放器#defi ne BTCNT1#defi ne BTCNT2_(0x0046)/* Basic Timer Cou nt 1 */(0x0047)/* Basic Timer Cou nt 2 */分頻*/很少使用吧*/* Freque ncy of the BTCNT2 coded with Bit 5 and 7 in BTCTL */ #defi ne

13、 BT_fCLK2_ACLK(0x00)#defi ne BT_fCLK2_ACLK_DIV256(BTDIV) /*256#defi ne BT_fCLK2_MCLK(BTSSEL)#defi ne BT_fCLK2_ACLK_DIV256(BTSSEL+BTDIV) /*/* Freque ncy of LCD coded with Bits 3-4 */ #define BT fLCD DIV32(0x00)/*fLCD = fACLK:32 (default)*/#define BT fLCD DIV64/* fLCD = fACLK:64 */#define BT fLCD DIV1

14、28#define BT fLCD DIV256(BTFRFQ0)(BTFRFQ1)(BTFRFQ1+BTFRFQ0) /* fLCD = fACLK:256 */* fLCD = fACLK:128 */* LCD freque ncy values with fBT=fACLK */ #define BT fLCD 1K(0x00)/* fACLK:32 (default) */#define BT fLCD 512#define BT fLCD 256#define BT fLCD 128(BTFRFQ0)(BTFRFQ1) (BTFRFQ1+BTFRFQ0)/* fACLK:64 */

15、* fACLK:128 */* fACLK:256 */* LCD freque ncy values with fBT=fMCLK */ #define BT fLCD 31K(BTSSEL)/* fMCLK:32 還是 fMCLK?*/#define BT fLCD 15 5K/* fMCLK:64 */(BTSSEL+BTFRFQ0)(BTSSEL+BTFRFQ1+BTFRFQ0) /* fMCLK:256 */* with assumed vlues of fACLK=32KHz, fMCLK=1MHz */#define BT fLCD 7 8K/* In terrupt in te

16、rval time fINT coded with Bits 0-2 in BTCTL */#defi ne BT_fCLK2_DIV2(0x00)/*fINT = fCLK2:2 (default) */#defi ne BT_fCLK2_DIV4(BTIP0)/* fINT =:fCLK2:4 */#defi ne BT_fCLK2_DIV8(BTIP1)/* fINT =:fCLK2:8 */#defi ne BT_fCLK2_DIV16(BTIP1+BTIP0)/* fINT = fCLK2:16 */#defi ne BT_fCLK2_DIV32(BTIP2)/* fINT :=fC

17、LK2:32 */#defi ne BT_fCLK2_DIV64(BTIP2+BTIP0)/* fINT = fCLK2:64 */#defi ne BT_fCLK2_DIV128(BTIP2+BTIP1)/* fINT = fCLK2:128 */#defi ne BT_fCLK2_DIV256(BTIP2+BTIP1+BTIP0) /* fINT = fCLK2:256 */* fBT=fACLK is thought for Ion ger in terval times */#define BT ADLY 0 064#define BT ADLY 0 125(0x00)(BTIP0)/

18、*/* 0.125ms"*/#define BT ADLY 0 25(BTIP1)/* 0.25ms"*/#define BT ADLY 0 5#define BT ADLY 1(BTIP1+BTIP0)(BTIP2)/* 1ms/* 0.5ms"*/#define BT ADLY 2#define BT ADLY 4(BTIP2+BTIP0)(BTIP2+BTIP1)/* 2ms/* 4ms#define BT ADLY 8#define BT ADLY 16#define BT ADLY 320.064ms in terval (default)*/"

19、;*/"*/"*/(BTIP2+BTIP1+BTIP0) /* 8ms(BTDIV)/* 16ms " */"*/(BTDIV+BTIP0)/* 32ms"*/#defi ne BT_ADLY_64(BTDIV+BTIP1)/* 64ms" */#defi ne BT_ADLY_125(BTDIV+BTIP1+BTIP0)/* 125ms"*/#defi ne BT_ADLY_250(BTDIV+BTIP2)/* 250ms" */#defi ne BT_ADLY_500(BTDIV+BTIP2+BTIP0)/*

20、500ms"*/#defi ne BT_ADLY_1000(BTDIV+BTIP2+BTIP1)/* 1000ms"*/#defi ne BT_ADLY_2000(BTDIV+BTIP2+BTIP1+BTIP0) /* 2000ms" */* fCLK2=fMCLK (1MHz) is thought for short interval times */* the timing for short intervals is more precise than ACLK */ /* Be sure that the SCFQCTL-Register is set

21、to 01Fh so that fMCLK=1MHz */* Too low interval time results in interrupts too frequent for the processor to han dle! */#defi ne BT_MDLY_0_002 #defi ne BT_MDLY_0_004 #defi ne BT_MDLY_0_008 #defi ne BT_MDLY_0_016 #defi ne BT_MDLY_0_032 #defi ne BT_MDLY_0_064 #defi ne BT_MDLY_0_125 #defi ne BT_MDLY_0_

22、25(BTSSEL) /* 0.002ms in terval * i nterval times */ (BTSSEL+BTIPO) /* 0.004ms * too short for */ (BTSSEL+BTIP1) /* 0.008ms * i nterrupt */ (BTSSEL+BTIP1+BTIP0) /* 0.016ms * handling */ (BTSSEL+BTIP2) /* 0.032ms " */ (BTSSEL+BTIP2+BTIP0)/* 0.064ms " */(BTSSEL+BTIP2+BTIP1)/* 0.125ms "

23、*/(BTSSEL+BTIP2+BTIP1+BTIP0)/* 0.25ms" */ /* Reset/Hold coded with Bits 6-7 in BT(1)CTL */set */while/* this is for BT */#define BTRESET_CNT1 (BTRESET) /* BTCNTIis reset while BTRESETis /#define BTRESET_CNT1_2 (BTRESET+BTDIV) /* BTCNT1.AND. BTCNT2are reset is set */* this is for BT1 */while#def

24、i ne BTHOLD_CNT1 (BTHOLD) /* BTCNT1 is held while BTHOLD is set */#defi ne BTHOLD_CNT1_2 (BTHOLD+BTDIV) /* BT1CNT1.AND. BT1CNT2are held is set */* INTERRUPT CONTROL BITS */* #defi ne BTIE0x80 */* #defi ne BTIFG0x80 */*定時器A3*/#defi ne TACTL_ DEFW( TACTL#defi ne TACCTL0_DEFW( TACCTL0 #defi ne TACCTL1_

25、 DEFW( TACCTL1#defi ne TAIV_(0x012E) /* Timer A In terrupt Vector Word */READ_ONLY DEFW( TAIV , TAIV_)(0x0160) /* Timer A Con trol */,TACTL_)(0x0162) /* Timer A Capture/Compare Con trol 0 */,TACCTL0_)(0x0164) /* Timer A Capture/Compare Control 1 */,TACCTL1_)#defi ne TACCTL2_DEFW( TACCTL2(0x0166) /*

26、Timer A Capture/Compare Control 2 */,TACCTL2_)#defi ne TAR_ DEFW( TAR#defi ne TACCR0_ DEFW( TACCR0 #defi ne TACCR1_ DEFW( TACCR1 #defi ne TACCR2_ DEFW( TACCR2(0x0170) /* Timer A */,tar_)(0x0172) /* Timer A Cap ture/Compare 0 */,TACCR0_)(0x0174) /* Timer A Cap ture/Compare 1 */,TACCR1_)(0x0176) /* Ti

27、mer A Cap ture/Compare 2 */,TACCR2_)#defi ne CCTL0TACCTL0#defi ne CCTL1TACCTL1#defi ne CCTL2TACCTL2#defi ne CCR0TACCR0#defi ne CCR1TACCR1#defi ne CCR2TACCR2/* Alternate register n ames */#defi ne CCTL0_/* Timer A Capture/Compare Con trol 0 */ /* Timer A Capture/Compare Con trol 1 */ /* Timer A Captu

28、re/Compare Con trol 2 */ /* Timer A Capture/Compare 0 */* Timer A Capture/Compare 1 */ /* Timer A Capture/Compare 2 */TACCTL0_ /* Timer A Capture/Compare Control 0 */#defi ne CCTL1_#defi ne CCTL2_#defi ne CCR0_TACCTL1_ /* Timer A Capture/Compare Control 1 */TACCTL2_ /* Timer A Capture/Compare Contro

29、l 2 */TACCR0_ /* Timer A Capture/Compare 0 */#defi ne CCR1_#defi ne CCR2_TACCR1_ /* Timer A Capture/Compare 1 */TACCR2_ /* Timer A Capture/Compare 2 */#defi ne TASSEL1(0x0200) /* Timer A clock source select 0 */#defi ne TASSEL0(0x0100) /* Timer A clock source select 1 */#defi ne ID1(0x0080) /* Timer

30、 A clock in put divider 1 */#defi ne ID0(0x0040) /* Timer A clock in put divider 0 */#defi ne MC1(0x0020) /* Timer A mode control 1 */#defi ne MC0(0x0010) /* Timer A mode control 0 */*TACTL:定時器A控制存放器J */15-109876543210XTASSEL1TASSEL0ID1ID0MC1MC0XTACLRTAIETAIFG#defi ne TACLR(0x0004) /* Timer A cou nt

31、er clear */#defi ne TAIE(0x0002) /* Timer A counter in terrupt en able */#defi ne TAIFG(0x0001) /* Timer A cou nter in terrupt flag */#defi ne MC_0(0*0x10u) /* 00停止模式*/#defi ne MC_1(1*0x10u) /* 01增計數(shù)模式*/#defi ne MC_2(2*0x10u) /* 10連續(xù)計數(shù)模式*/#defi ne MC_3(3*0x10u) /* 11增減計數(shù)模式*/*ID1.ID0:輸入分頻選擇*/#defi ne

32、 ID_0(0*0x40u) /* 00:不分頻*/*MC1.MC0計數(shù)模式控制位*/#define ID_1#define ID 2(1*0x40u) /* 01(2*0x40u) /* 10#defi ne ID_3(3*0x40u) /* 11/*SSEL1.SSEL0輸入分頻器的時鐘源選擇*/#define TASSEL 0#define TASSEL_1#define TASSEL 2#define TASSEL 3(0*0x100u) /* 00(1*0x100u)/* 01(2*0x100u) /* 10(3*0x100u) /* 11/*TACCTLx:捕獲/比擬控制存放器J

33、*/#defi ne CM1#defi ne CM0#define CCIS1#defi ne CCIS0#defi ne SCS#defi ne SCCI#define CAP#defi ne OUTMOD2#defi ne OUTMOD1#defi ne OUTMOD0#defi ne CCIE#defi ne CCI#defi ne OUT#defi ne COV2分頻4分頻8分頻*/*/*/TACLK見具體器件說明ACLK */SMCLK */INCLK見具體器件說明*/*/(0x8000) /* Capture mode 1 */(0x4000) /* Capture mode 0

34、*/(0x2000) /* Capture in put select 1 */(0x1000) /* Capture in put select 0 */(0x0800) /* 0:異步捕獲；(0x0400) /* Latched capture sig nal (read) */(0x0100) /* 0:比擬模式；(0x0080) /* Output mode 2 */(0x0040) /* Output mode 1 */(0x0020) /* Output mode 0 */(0x0010) /* 0:禁止中斷；(0x0008) /* Capture in put sig nal (

35、read) */(0x0004) /* PWM Output signal if output mode 0 */(0x0002) /*捕獲溢出標志(1為溢出)(0x0001) /* Capture/compare in terrupt flag */1：同步捕獲1 ：捕獲模式1:允許中斷*/*/*/*/15.1413.1211109843210CM1.0CCIS1.0SCSSCCICAPCCIECCIOUTCOVCCIFG#defi ne CCIFG/*OUTMOD輸出模式選擇*/#define OUTMOD 0#defi ne OUTMOD 1#define OUTMOD 2#defi n

36、e OUTMOD_3#defi ne OUTMOD_4#define OUTMOD 5(0*0x20u)(1*0x20u)(2*0x20u)(3*0x20u)(4*0x20u)(5*0x20u)(6*0x20u)(7*0x20u)#defi ne OUTMOD_6#defi ne OUTMOD_7/*CCIS1.CCIS0:捕獲事件的輸入源/* PWM output mode: 0/* PWM output mode: 1/* PWM output mode: 2 - PWM /* PWM output mode: 3 - PWM /* PWM output mode: 4/* PWM out

37、put mode: 5/* PWM output mode: 6 - PWM /* PWM output mode: 7 - PWM */-輸出*/置位*/翻轉(zhuǎn)/復(fù)位 置位/復(fù)位 -翻轉(zhuǎn)*/ 復(fù)位*/翻轉(zhuǎn)/置位 復(fù)位/置位*/*/*/*/#defi ne CCIS_0#defi ne CCIS_1#defi ne CCIS_2#defi ne CCIS_3(0*0x1000u) /* Capture in put select: 0 - CCIxA */ (1*0x1000u) /* Capture input select: 1 - CCIxB */ (2*0x1000u) /* Captu

38、re in put select: 2 - GND */ (3*0x1000u) /* Capture in put select: 3 - Vcc */* CM1.CM0:捕獲模式選擇*/#defi ne CM_0(0*0x4000u) /* Capture mode: 0#defi ne CM_1(1*0x4000u) /* Capture mode: 1-禁止捕獲模式*/-上升沿捕獲*/#defi ne CM_2#defi ne CM_3-下降沿捕獲*/-上升下降沿捕獲*/(2*0x4000u) /* Capture mode: 1(3*0x4000u) /* Capture mode:

39、 1/*硬件乘法器的存放器定義*/無符號乘法*/有符號乘法*/無符號乘加*/有符號乘加*/第二乘數(shù)*/低6位結(jié)果存放器*/高6位結(jié)果存放器*/結(jié)果擴展存放器*/#defi ne MPY_ sfrw MPY#defi ne MPYS_ sfrw MPYS#defi ne MAC_ sfrw MAC#defi ne MACS_ sfrw MACS#defi ne OP2_sfrw OP2#defi ne RESLO_ sfrw RESLO #defi ne RESHI_ sfrw RESHI #defi ne SUMEXT_0x0130 /*=MPY_;0x0132 /*=MPYS_;0x0134

40、 /*=MAC_;0x0136 /*=MACS_;0x0138 /*=OP2_;0x013A /*=RESLO_;0x013C /*=RESHI_;0x013E /*const sfrw SUMEXT = SUMEXT*LCD *#defi ne LCDCTLDEFC( LCDCTL(0x0090) /* LCD Control */,LCDCTL_)/* the names of the mode bits are different from the spec */ #defi ne LCDON#defi ne LCDLOWR(0x01)(0x02)/*u nused*/#defi ne

41、LCDSON#defi ne LCDMX0(0x04)(0x08)/*段輸出控制：0禁止；1允許*/#defi ne LCDMX1#defi ne LCDP0(0x10)(0x20)(0x40)/*輸出模式選擇*/#defi ne LCDP2(0x80) /*輸出端或端口信息組合*/LCDCTLLCDP2LCDP1LCDP0LCDMX1LCDMX0LCDSONLCDLOWRLCDON#defi ne LCDP1/*輸出模式選擇*/#defi ne LCDSTATIC#defi ne LCD2MUX#defi ne LCD3MUX#defi ne LCD4MUX/*輸出端或端口信息組合(LCDS

42、ON)(LCDMX0+LCDSON)(LCDMX1+LCDSON) (LCDMX1+LCDMX0+LCDSON)*/#defi ne LCDSG0#define LCDSG0 1#define LCDSG0 2(0x00)(LCDP0)(LCDP1)/* Port On ly (default) */* S0 - S15 see Datasheet */* S0 - S19 see Datasheet */#defi ne LCDSG0_3#defi ne LCDSG0_4#defi ne LCDSG0_5#defi ne LCDSG0_6#defi ne LCDSG0_7(LCDP1+LCD

43、P0) /* S0 - S23 see Datasheet */(LCDP2) /* S0 - S27 see Datasheet */(LCDP2+LCDP0) /* S0 - S31 see Datasheet */(LCDP2+LCDP1) /* S0 - S35 see Datasheet */ (LCDP2+LCDP1+LCDP0) /* S0 - S39 see Datasheet */#defi ne LCDOG1_7#defi ne LCDOG2_7#defi ne LCDOG3_7#defi ne LCDOG4_7#defi ne LCDOG5_7#defi ne LCDOG

44、6_7#defi ne LCDOG7#defi ne LCDOGOFF(0x00)/* PortOnly(LCDP0)/* S0 - S15 see Datasheet */(LCDP1)/* S0 - S19 see Datasheet */(LCDP1+LCDP0) /* S0 - S23 see Datasheet */(LCDP2) /* S0 - S27 see Datasheet */(LCDP2+LCDP0) /* S0 - S31 see Datasheet */(LCDP2+LCDP1) /* S0 - S35 see Datasheet */(LCDP2+LCDP1+LCD

45、P0) /* S0 - S39 see(default) */Datasheet */#defi ne LCDMEM #en dif#defi ne LCDM1_ DEFC( LCDM1 #defi ne LCDM2_ DEFC( LCDM2 #defi ne LCDM3_ DEFC( LCDM3 #defi ne LCDM4_ DEFC( LCDM4 #defi ne LCDM5_ DEFC( LCDM5 #defi ne LCDM6_ DEFC( LCDM6 #defi ne LCDM7_ DEFC( LCDM7 #defi ne LCDM8_ DEFC( LCDM8 #defi ne L

46、CDM9_ DEFC( LCDM9 #defi ne LCDM10_ DEFC( LCDM10 #defi ne LCDM11_ DEFC( LCDM11 #defi ne LCDM12_#defi ne LCDMEM_(0x0091) /* LCD Memory */ #ifndef _IAR_SYSTEMS_ICC#defi ne LCDMEM(LCDMEM_) /* LCD Memory (for assembler) */#else(char*) LCDMEM_) /* LCD Memory (for C) */(0x0091) /* LCD Memory 1 */,LCDM1(0x0

47、092) /* LCD Memory 2 */,LCDM2_)(0x0093) /* LCD Memory 3 */,LCDM3_)(0x0094) /* LCD Memory 4 */,LCDM4_)(0x0095) /* LCD Memory 5 */,LCDM5_)(0x0096) /* LCD Memory 6 */,LCDM6_)(0x0097) /* LCD Memory 7 */,LCDM7_)(0x0098) /* LCD Memory 8 */,LCDM8_)(0x0099) /* LCD Memory 9 */,LCDM9_)(0x009A) /* LCD Memory 1

48、0 */,LCDM10_)(0x009B) /* LCD Memory 11 */,LCDM11(0x009C) /* LCD Memory 12 */DEFC( LCDM12,LCDM12_)#defi ne LCDM13_(0x009D) /* LCD Memory 13 */DEFC( LCDM13,LCDM13_)#defi ne LCDM14_(0x009E) /* LCD Memory 14 */DEFC( LCDM14,LCDM14_)#defi ne LCDM15_(0x009F) /* LCD Memory 15 */DEFC( LCDM15,LCDM15_)#defi ne

49、 LCDM16_(0x00A0) /* LCD Memory 16 */DEFC( LCDM16,LCDM16_)#defi ne LCDM17_(0x00A1) /* LCD Memory 17 */DEFC( LCDM17,LCDM17_)#defi ne LCDM18_(0x00A2) /* LCD Memory 18 */DEFC( LCDM18,LCDM18_)#defi ne LCDM19_(0x00A3) /* LCD Memory 19 */DEFC( LCDM19,LCDM19_)#defi ne LCDM20_(0x00A4) /* LCD Memory 20 */DEFC

50、( LCDM20,LCDM20_)#defi ne LCDMA(LCDM10) /* LCD Memory A */#defi ne LCDMB(LCDM11) /* LCD Memory B */#defi ne LCDMC(LCDM12) /* LCD Memory C */#defi ne LCDMD(LCDM13) /* LCD Memory D */#defi ne LCDME(LCDM14) /* LCD Memory E */#defi ne LCDMF(LCDM15) /* LCD Memory F */*Flash存儲器暑 */#defi ne FCTL1_(0x0128)

51、/* FLASH Control 1 */DEFW( FCTL1#define FCTL2_,FCTL1_)(0x012A) /* FLASH Con trol 2 */DEFW( FCTL2 #defi ne FCTL3_,FCTL2_)(0x012C) /* FLASH Control 3 */DEFW( FCTL3,FCTL3_)I*控制存放器1:FCTL1*/#defi ne FRKEY(0x9600) /*#defi ne FWKEY(0xA500) /*口令碼：讀出為 96H */ 口令碼：寫入為 5AH */#defi ne FXKEY(0x3300) /* for use with XOR instruction */15-8765-3210口令碼BLKWRTWRTXMERASERASEX#defi ne ERASE#defi ne MERAS#defi ne WRT#defi ne BLKWRT#defi ne SEGWRT(0x0002) /*(0x0004) /*(0x0040) /*(0x0080) /*(0x0080