串入并出轉(zhuǎn)換器verilog

1、設(shè)計一個申入并出轉(zhuǎn)換器。輸入是8bit數(shù)據(jù)，輸出是32bit數(shù)據(jù)。給出AMSD圖和HDL設(shè)計描述。提交紙質(zhì)文檔。DataP37:O|TMr*8?2p：o)1rPl7;0)ffl(7:0T'i*11!-R7:0；P2|7：GPlp：O)；P0(7；0制、ASMD圖、RTL代碼/*程序名稱：申入并出轉(zhuǎn)換器簡要說明：申行輸入8bit數(shù)據(jù)，并行輸出32bit數(shù)據(jù)。編寫：武書肖最后更新：2015年3月28日星期六*/moduleser_to_par(clk,rst_n,en,data_in,data_out,en_out);inputclk,rst_n,en;input7:0data_in;/8

2、位申行輸入output31:0data_out;/32位并行輸出outputen_out;/輸出有效標志位reg7:0p0,p1,p2,p3;/4個8位寄存器reg31:0data_reg;/32位輸出寄存器reg4:0state,next_state;/FSM狀態(tài)regen_out;parameters_idle=5'b00001,/狀態(tài)獨熱編碼s_in_1=5'b00010,s_in_2=5'b00100,s_in_3=5'b01000,s_full=5'b10000;assigndata_out=en_out?data_reg:32'dz;

3、always(posedgeclk)/同步時序描述狀態(tài)轉(zhuǎn)移beginif(rst_n=0)state<=s_idle;elsestate<=next_state;end/組合邏輯描述狀態(tài)轉(zhuǎn)移條件判斷next_state=s_in_1;next_state=s_idle;next_state=s_in_2;next_state=s_in_3;next_state=s_full;next_state=s_in_1;next_state=s_idle;always(stateoren)beginnext_state=state;case(state)s_idle:if(en=1)else

4、s_in_1:s_in_2:s_in_3:s_full:if(en=1)elseendcaseendalways(posedgeclk)/同步時序描述次態(tài)寄存器的輸出beginif(rst_n=0)en_out<=0;elsecase(next_state)s_idle:en_out<=0;s_in_1,s_in_2,s_in_3:beginen_out<=0;p3<=data_in;p2<=p3;-p1<=p2;p0<=p1;ends_full:begindata_reg<=p3,p2,p1,p0;en_out<=1;if(en=1)p3

5、<=data_in;endendcaseendendmodule/*不使用狀態(tài)機的RTLK碼*/moduleser_to_par(clk,rst_n,en,data_in,data_out,en_out);inputclk,rst_n,en;input7:0data_in;/8位申行輸入output31:0data_out;/32位并行輸出outputen_out;輸出有效標志位reg7:0p0,p1,p2,p3;/4個8位寄存器reg31:0data_reg;/32位輸出寄存器regen_out;integerin_counter;/輸入數(shù)據(jù)計數(shù)assigndata_out=en_ou

6、t?data_reg:32'dz;always(posedgeclk)beginif(!rst_n)beginin_counter<=0;en_out<=0;endelseif(en)beginin_counter<=in_counter+1;en_out<=0;p3<=data_in;p2<=p3;p1<=p2;p0<=p1;data_reg<=p3,p2,p1,p0;if(in_counter=3)beginen_out<=1;in_counter<=0;endendendendmodule三、TestBench&#

7、39;timescale1ns/1psmoduleseri_to_para_vlg_tst();regclk;reg7:0data_in;regen;regrst_n;wire31:0data_out;wireen_out;seri_to_parai1(/portmap-connectionbetweenmasterportsandsignals/registers.clk(clk),.data_in(data_in),.data_out(data_out),.en(en),.en_out(en_out),.rst_n(rst_n);initialbeginclk=0;rst_n=1;en=0;#10rst_n=0;#100rst_n=1;#100en=1;#10000$stop;endalways#50clk=clk;always(negedgeclk)begindata_in<=$random%256;endendmodule四、仿真結(jié)果Mjartojpar_MigJsl/dt?tnJntQjpar_vtaJsl/enIsjsarvlglsljSratjito