數(shù)字頻率計的介紹外文翻譯

1、譯文：數(shù)字頻率計的介紹譯自文斯凱赫爾著的VHDL邏輯設(shè)計76-88頁數(shù)字頻率計是通信設(shè)備、音、視頻等科研生產(chǎn)領(lǐng)域不可缺少的測量儀器。采用Verilog HDL編程設(shè)計實現(xiàn)的數(shù)字頻率計，除被測信號的整形部分、鍵輸入部分和數(shù)碼顯示部分外，其余全部在一片F(xiàn)PGA芯片上實現(xiàn)。整個系統(tǒng)非常精簡，且具有靈活的現(xiàn)場可更改性。1 等精度測頻原理頻率的測量方法主要分為2 種方法:(1) 直接測量法, 即在一定的閘門時間內(nèi)測量被測信號的脈沖個數(shù)。(2) 間接測量法, 例如周期測頻法、V F 轉(zhuǎn)換法等。間接測頻法僅適用測量低頻信號。 基于傳統(tǒng)測頻原理的頻率計的測量精度將隨被測信號頻率的下降而降低, 在實用中有較大的

2、局限性, 而等精度頻率計不但具有較高的測量精度, 而且在整個頻率區(qū)域能保持恒定的測試精度。頻率測量方法的主要測量預(yù)置門控信號GATE是由單片機發(fā)出，GATE的時間寬度對測頻精度影響較少，可以在較大的范圍內(nèi)選擇，只要FPGA中32 b計數(shù)器在計100 M信號不溢出都行，根據(jù)理論計算GATE的時間寬度Tc可以大于4294 s，但是由于單片機的數(shù)據(jù)處理能力限制，實際的時間寬度較少，一般可在1001 s間選擇，即在高頻段時，閘門時間較短；低頻時閘門時間較長。這樣閘門時間寬度Tc依據(jù)被測頻率的大小自動調(diào)整測頻，從而實現(xiàn)量程的自動轉(zhuǎn)換，擴大了測頻的量程范圍；實現(xiàn)了全范圍等精度測量，減少了低頻測量的誤差。本

3、設(shè)計頻率測量方法的主要測量控制框圖如圖1 所示。圖1 中預(yù)置門控信號GA TE 是由單片機發(fā)出, GA TE的時間寬度對測頻精度影響較少, 可以在較大的范圍內(nèi)選擇, 只要FPGA 中32 b 計數(shù)器在計100M 信號不溢出都行, 根據(jù)理論計算GA TE 的時間寬度T c 可以大于42194s, 但是由于單片機的數(shù)據(jù)處理能力限制, 實際的時間寬度較少, 一般可在10 011 s 間選擇, 即在高頻段時, 閘門時間較短; 低頻時閘門時間較長。這樣閘門時間寬度T c 依據(jù)被測頻率的大小自動調(diào)整測頻, 從而實現(xiàn)量程的自動轉(zhuǎn)換, 擴大了測頻的量程范圍; 實現(xiàn)了全范圍等精度測量, 減少了低頻測量的誤差。2

4、 頻率計的實現(xiàn)等精度測頻的實現(xiàn)方法 ?？珊喕癁镃NT1和CNT2是兩個可控計數(shù)器，標(biāo)準(zhǔn)頻率(f )信號從CN F1的時鐘輸入端cI K輸入，經(jīng)整形后的被測信號(f )從CNT2的時鐘輸入端cI K輸入。每個計數(shù)器中的CEN輸入端為使能端，用來控制計數(shù)器計數(shù)。當(dāng)預(yù)置閘門信號為高電平(預(yù)置時間開始)時。被測信號的上升沿通過D觸發(fā)器的輸入端，同時啟動兩個汁數(shù)器計數(shù)；同樣，當(dāng)預(yù)置閘門信號為低電平(預(yù)置時間結(jié)束)時，被測信號的上升沿通過D觸發(fā)器的輸出端，使計數(shù)器停止計數(shù)。3 頻率計的位數(shù)及相關(guān)指標(biāo)位數(shù)：同時最多能顯示的數(shù)字位數(shù)。平常計數(shù)式的8位頻率計只有幾百元就可買到。對于高精度的測量，9位剛剛開始，1

5、1位算中等，13位才能算比較高級。 溢出位：把溢出位算進去的總等效位。有些頻率計帶有溢出功能，即把最高位溢出不顯示而只顯示后面的位，以便達到提高位數(shù)的目的。這里個別指標(biāo)是估計值。 速度：即每秒能出多少位。有了高位數(shù)的但測量特別慢也失去了意義。平常計數(shù)式的8位頻率計，測量10MHz信號、1秒閘門能得到10,000,000Hz，這實際上才是7位（位數(shù)等于取常用對數(shù)后的值），要想得到8位，需要10秒閘門；要想得到9位，需要100秒閘門，依次類推，即便顯示允許，11位需要10000秒的測量時間了。但無論如何，還是每秒7位。因此，要想快速得到高位數(shù)則必須高速度。 分辨：這就像一個電壓表最小可以分辨出多大

6、的電壓的指標(biāo)是類似的，越小越好，單位ps（皮秒）。1000ps=1ns。假設(shè)你用1ns的頻率計要分辨出1e-12的誤差，就需要1ns/1e-12=1000秒的時間。而假設(shè)你有另外一個頻率計的分辨是100ps，那么測量時間就可以縮短10倍為100秒，或者可以在相同的1000秒下測量出1e-14的誤差。4 時間頻率測量相比傳統(tǒng)的電路系統(tǒng)設(shè)計方法，EDA技術(shù)采用VHDL語言描述電路系統(tǒng)，包括電路的結(jié)構(gòu)、行為方式、邏輯功能及接口。Verilog HDL具有多層次描述系統(tǒng)硬件功能的能力，支持自頂向下的設(shè)計特點。設(shè)計者可不必了解硬件結(jié)構(gòu)。從系統(tǒng)設(shè)計入手，在頂層進行系統(tǒng)方框圖的劃分和結(jié)構(gòu)設(shè)計，在方框圖一級用

7、Ver-ilog HDL對電路的行為進行描述，并進行仿真和糾錯，然后在系統(tǒng)一級進行驗證，最后再用邏輯綜合優(yōu)化工具生成具體的門級邏輯電路的網(wǎng)表，下載到具體的FPGA器件中去，從而實現(xiàn)FPGA的設(shè)計。時間頻率測量是電子測量的重要領(lǐng)域。頻率和時間的測量已越來越受到重視，長度、電壓等參數(shù)也可以轉(zhuǎn)化為與頻率測量有關(guān)的技術(shù)來確定。本文通過對傳統(tǒng)的多周期同步法進行探討，提出了多周期同步法與量化時延法相結(jié)合的測頻方法。 最簡單的測量頻率的方法是直接測頻法。直接測頻法就是在給定的閘門信號中填入脈沖，通過必要的計數(shù)電路，得到填充脈沖的個數(shù)，從而算出待測信號的頻率或周期。在直接測頻的基礎(chǔ)上發(fā)展的多周期同步測量方法，

8、在目前的測頻系統(tǒng)中得到越來越廣泛的應(yīng)用。多周期同步法測頻技術(shù)的實際閘門時間不是固定的值，而是被測信號的整周期倍，即與被測信號同步，因此消除了對被測信號計數(shù)時產(chǎn)生的±1個字誤差，測量精度大大提高，而且達到了在整個測量頻段的等精度測量，在時頻測量方法中，多周期同步法是精度較高的一種，但仍然未解決±1個字的誤差，主要是因為實際閘門邊沿與標(biāo)頻填充脈沖邊沿并不同步Tx=N0T0-t2+t1，如果能準(zhǔn)確測量出短時間間隔t1和t2，也就能夠準(zhǔn)確測量出時間間隔Tx，消除±1個字的計數(shù)誤差，從而進一步提高精度。 為了測量短時間間隔t1和t2，通常使用模擬內(nèi)插法或游標(biāo)法與多周期同步法

9、結(jié)合使用，雖然精度有很大提高，但終未能解決±1個字的誤差這個根本問題，而且這些方法設(shè)備復(fù)雜，不利于推廣。 要得到精度高，時間響應(yīng)快，結(jié)構(gòu)簡單的頻率和時間測量方法是比較困難的。從結(jié)構(gòu)盡量簡單同時兼顧精度的角度出發(fā)，將多周期同步法與基于量化時延的短時間間隔測量方法結(jié)合，實現(xiàn)了寬頻范圍內(nèi)的等精度高分辨率測量。量化時延法測短時間間隔 光電信號可以在一定的介質(zhì)中快速穩(wěn)定的傳播，且在不同的介質(zhì)中有不同的延時。通過將信號所產(chǎn)生的延時進行量化，實現(xiàn)了對短時間間隔的測量。 其基本原理是“串行延遲，并行計數(shù)”，而不同于傳統(tǒng)計數(shù)器的串行計數(shù)方法，即讓信號通過一系列的延時單元，依靠延時單元的延時穩(wěn)定性，在計

10、算機的控制下對延時狀態(tài)進行高速采集與數(shù)據(jù)處理，從而實現(xiàn)了對短時間間隔的精確測量。 量化時延思想的實現(xiàn)依賴于延時單元的延時穩(wěn)定性，其分辨率取決于單位延時單元的延遲時間。 作為延時單元的器件可以是無源導(dǎo)線，有源門器件或其他電路。其中，導(dǎo)線的延遲時間較短(接近光速傳播的延遲)，門電路的延遲時間相對較長?？紤]到延遲可預(yù)測能力，最終選擇了CPLD器件，實現(xiàn)對短時間間隔的測量。 將短時間間隔的開始信號送入延時鏈中傳播，當(dāng)結(jié)束信號到來時，將此信號在延時鏈中的延時狀態(tài)進行鎖存，通過CPU讀取，判斷信號經(jīng)過的延時單元個數(shù)就可以得到短時時間間隔的大小，分辨率決定于單位延時單元的延時時間。 一般來講，為了測量兩個短

11、時間間隔，使用兩組延時和鎖存模塊，但實際上，給定的軟件閘門時間足夠大，允許CPU完成取數(shù)的操作，即能夠在待測時間間隔結(jié)束之前取走短時間隔t1對應(yīng)的延時單元的個數(shù)，通過一定的控制信號，可以只用一組延時和鎖存單元，這樣可以節(jié)省CPLD內(nèi)部的資源。利用多周期同步與量化時延相結(jié)合的方法，計算公式為： T=n0t0+n1t1-n2t1 上式中，n0為對填充脈沖的計數(shù)值；t0為填充脈沖的周期，即100ns；n1為短時間隔t1對應(yīng)的延時單元的個數(shù)；n2為短時間隔t2對應(yīng)的延時單元的個數(shù)；t1為量化延遲器件延時單元的延遲量(4.3ns)。 這樣，利用多周期同步法，實現(xiàn)了閘門和被測信號同步；利用量化時延法，測量

12、了原來測不出來的兩個短時間間隔，從而準(zhǔn)確地測量了實際閘門的大小，也就提高了測頻的精度。 由于頻率合成器輸出的頻率信號最小只能調(diào)到10Hz，把XDU-17的測量值作為標(biāo)準(zhǔn)，可以計算出樣機測頻的精度。 例如，被測信號為15.000010MHz時被測信號為5.00001002MHz時，從上面的計算可以看出，樣機的分辨率已達ns量級，下面從理論分析的角度來說明這一點。 前面已經(jīng)分析過，多周期同步法測頻時，它的測量不確定度為： 當(dāng)輸入f0為10MHz，閘門時間為1s時，測量的不確定度為±1×10-7/s。當(dāng)與量化延時測量與短時間間隔電路相結(jié)合時，測量的不確定度可以從下述推導(dǎo)出來。 在

13、采用多周期同步法時，Tx為待測的多周期值，T0為采用的時基周期。Tx= NT0+t1-t2 與量化延時電路相結(jié)合后有：Tx= NT0+(N1-N2)td±Tx 這里，Tx為測量的不準(zhǔn)確度。 對上式微分得： Tx±2td 由上式可知，此方法的測量精度取決于td，它的穩(wěn)定性與大小直接影響測量值的不確定度。所以采用各種方法，計數(shù)器可在整個頻率量程內(nèi)實現(xiàn)等精度的測量，而且測量精度有顯著提高，測量分辨率提高到4.3ns，且消除了±1個字的理論誤差，精度提高了20多倍。結(jié)束語 本文將給出了一種新的測頻方法?；诖朔椒ǖ念l率計的數(shù)字電路部分集成在一片CPLD中，大大減小了整個儀

14、器的體積，提高了可靠性，且達到了很高的測量分辨率。5 頻率計的VHDL 設(shè)計利用ALTERA公司的FPGA芯片EPF10K10，使用VHDL編程語言設(shè)計等精度頻率計，給出核心程序，經(jīng)過ISPEXPER仿真后，驗證設(shè)計是成功的，達到預(yù)期結(jié)果。傳統(tǒng)的頻率計相比，F(xiàn)PGA的頻率計簡化了電路板的設(shè)計，提高了系統(tǒng)設(shè)計的實現(xiàn)性和可靠性，測頻范圍達到100 MHz，實現(xiàn)了數(shù)字系統(tǒng)硬件的軟件化，這是數(shù)字邏輯設(shè)計的新趨勢。本設(shè)計采用AL TERA 公司的FPGA 芯片EPF10K10, 該芯片管腳間的延遲為5 ns, 即頻率為200MHz, 應(yīng)用標(biāo)準(zhǔn)化的硬件描述語言VHDL 有非常豐富的數(shù)據(jù)類型, 他的結(jié)構(gòu)模型

15、是層次化的, 利用這些豐富的數(shù)據(jù)類型和層次化的結(jié)構(gòu)模型, 對復(fù)雜的數(shù)字系統(tǒng)進行邏輯設(shè)計并用計算機仿真, 逐步完善后進行自動綜合生成符合要求的、在電路結(jié)構(gòu)上可實現(xiàn)的數(shù)字邏輯, 再下載到可編程邏輯器件中, 即可完成設(shè)計任務(wù)。原文：Introduction of digital frequency meterfrom Vin Skahill.VHDL for Programmable Logic page76-88Digital Frequency of communications equipment, audio and video, and other areas of scientific

16、research and production of an indispensable instrument. Programming using Verilog HDL Design and Implementation of the digital frequency, in addition to the plastic part of the measured signal, and digital key for a part of the show, all in an FPGA chip to achieve. The entire system is very lean, fl

17、exible and have a modification of the scene.1. And other precision measuring frequency PrincipleFrequency measurement methods can be divided into two kinds: (1) direct measurement method, that is, at a certain time measurement gate measured pulse signal number. (2) indirect measurements, such as the

18、 cycle frequency measurement, VF conversion law. Frequency Measurement indirect measurement method applies only to low-frequency signals.Based on the principles of traditional frequency measurement of the frequency of measurement accuracy will be measured with the decline in signal frequency decreas

19、es in the more practical limitations, such as the accuracy and frequency of measurement not only has high accuracy, but also in the whole frequency region to maintain constant test accuracy. The main method of measurement frequency measurement Preferences gated signal GATE issued by the MCU, GATE ti

20、me width on the frequency measurement accuracy of less impact, in the larger context of choice, as long as the FPGA in 32 of 100 in the counter b M Signals are not overflow line, in accordance with the theoretical calculation GATE time can be greater than the width Tc 42.94 s, but due to the single-

21、chip microcomputer data processing capacity constraints, the actual width of less time, generally in the range of between 0.1 s choice, that is, high-frequency, shorter gate;, low gate longer. This time gate width Tc based on the size of the measured frequency automatically adjust frequency measurem

22、ent in order to achieve the automatic conversion range, and expanded the range of frequency measurement; realization of the entire scope of measurement accuracy, reduce the low-frequency measurement error.     The design of the main methods of measuring the frequency measurement

23、and control block diagram as shown in Figure 1. Figure 1 Preferences gated signal GA TE issued by the MCU, GA TE time width of less frequency measurement accuracy, in the larger context of choice, as long as the FPGA in 32 of 100 in the counter b M signal Overflow will do, according to theoretical c

24、alculations GA TE time width T c can be greater than 42194 s, but due to the single-chip microcomputer data processing capacity constraints, the actual width of less time, generally 10 to 011 s in the inter-choice, that is, high - band, the gate time shorter, low gate longer. This time gate width ba

25、sed on the measured T c automatically adjust the size of frequency measurement frequency range to achieve the automatic conversion, and expanded the range of frequency measurement; realization of the entire scope of measurement accuracy, reduce the low-frequency measurement error.2 .Frequency of ach

26、ievingFrequency Measurement accuracy of such method. Can be simplified as shown in the diagram. Map CNT1 and CNT2 two controllable counter, standard frequency (f) signal from the CN F1 clock input cI K input, the signal measured after the plastic (f) CNT2 clock input cI K input. Each counter in the

27、CEN input as enable end, used to control the counter count. When the gate signal is HIGH Preferences (Preferences start time). Signal measured by the rising edge of the D flip-flop input, launched at the same time with two counts of juice; Similarly, when preferences for low gate signal (the end of

28、Preferences time), the rising edge of the measured signals through D Trigger output end of the counter to stop counting.3.And the median frequency of relevant indicatorsMedian: At the same time the figures show that up to the median. The usual eight-count frequency of only several hundred yuan can b

29、uy. For high precision measurements, nine just beginning, the middle is 11, 13 can be relatively high.      Overflow of:-the ability to promote itself to overflow the equivalent of the total. Some of the frequency with overflow function, which is the highest overflow does not dis

30、play only shows that the bit behind, in order to achieve the purpose of the median. Here is the estimated value of individual indicators.      Speed: namely, the number of per second. With the high number of measurement particularly slow but also lose its significance. Counting o

31、f the usual eight frequency measurement 10 MHz signals, one second gate will be 10000000 Hz, which is actually seven (equivalent to the median number of common admission after the value), to obtain eight needed 10 seconds gate ; to obtain nine needed 100 seconds gate, followed by analogy, shows that

32、 even the permission of 11 need 10,000 second measurement time. But in any case, or seven per second. Therefore, to fast must be a few high speed.   Distinction: it is like a minimum voltage meter can tell how much voltage indicators are similar, the smaller the better, unit ps (picoseconds). 1

33、000ps = 1ns. Suppose you use the frequency of 1 ns to differentiate between an e-12 error, we need a ns/1e-12 = 1000 seconds. Also assume that you have a frequency resolution of 100 ps, the measurement time can be shortened by 10 times for 100 seconds, or can be in the same 1000 second measured unde

34、r an e-14 Error.4. Time and Frequency MeasurementCompared to traditional methods of circuit design, EDA technology uses VHDL language to describe circuit system, including circuit structure, behavior, function and interface logic. Verilog HDL description of a multi-level system hardware functions, a

35、nd support top-down design features. Designers can not understand the hardware structure. Start from the system design, on the top floor of a system block diagram of the structure and design, in a diagram with Ver-ilog HDL acts on the circuit description and simulation and error correction, and then

36、 the system level verification, and finally use logic synthesis optimization tool to create specific gate-level logic circuit netlist, download to the specific FPGA device to in order to achieve FPGA design. Time and frequency measurement is an important area of electronic measurement. Frequency and

37、 time measurement has been receiving increasing attention, length, voltage, and other parameters can be transformed into a frequency measurement and related technologies to determine. Based on the more traditional method of synchronization cycle, and has proposed a multi-cycle synchronization and qu

38、antitative method of measuring delay frequency method. The most simple method of measuring the frequency of direct frequency measurement method. Direct Frequency Measurement is scheduled to enter the gate signal pulse, the adoption of the necessary counting circuit, the number of pulses are filled t

39、o calculate the frequency or analyte signal cycle. In the direct frequency measurement on the basis of the development of multi-cycle synchronous measurement method, in the current frequency monitoring system to be more widely used. Multi-cycle synchronization frequency measurement technology actual

40、 gate time is not fixed value, but the measured signals in the whole cycle times, and the measured signal synchronization, thereby removing the measured signal count on when the word ± 1 error, measurement accuracy greatly improved, and reached in the entire spectrum of measurement, such as pre

41、cision measurement.In the time-frequency measurement method, the multi-cycle synchronization is a high precision, but still unresolved ± a word error, mainly because of the actual gate edge and standard frequency synchronization is not filling pulse edge Tx=N0T0-t2+t1, if accurately measured sh

42、ort interval t1 and t2, will be able to accurately measure time intervals Tx, eliminating ± a word counting error, so as to further enhance accuracy.      To measure a short time interval t1 and t2, commonly used analog interpolation method with the cursor or more combined c

43、ycle synchronization, although accuracy is greatly improved, but eventually failed to resolve ± a word error this fundamental issue, but these methods equipment complex and not conducive to the promotion.      To obtain high precision, fast response time, simple structure an

44、d the frequency and time measurement method is relatively difficult. Judging from the structure as simple as possible at the same time take into account the point of view of accuracy, multi-cycle synchronization and delay based on the quantitative methods in a short period of time interval measureme

45、nt, achieved within the scope of broadband, such as high-resolution measurement accuracy. Quantified by measuring short time intervals Delay      Photoelectric signal can be in a certain stability in the medium of rapid spread, and in different media have different delay. By sign

46、als generated by the delay to quantify, and gave a short period of time interval measurement.      The basic principle is that "delay serial, parallel count", and different from the traditional counter serial number, that is, to signal through a series of delay unit, th

47、e delay unit on the delay stability, under the control of the computer Delay on the state of high-speed acquisition and data processing, for a short period of time to achieve accurate measurement interval.Delay quantitative thinking depend on the realization of the delay stability delay unit, the un

48、it depends on the resolution of the delay time delay element.      Delay device as a unit can be passive conduit, or other active devices gate circuit. Among them, Traverse shorter delay time (nearly the speed of light transmission delay), the gate delay time longer. Taking into

49、account delays can be predictive ability final choice of the CPLD devices, the realization of the short time interval measurement.      Will be the beginning of a short time interval signal sent delay in the transmission chain, when the advent of the end of signal, this signal de

50、lay in the delay in the chain latch state, read through the CPU, the judge signal a delay unit on the few short-term time interval can be the size of the unit decided to delay resolution of the unit delay time.      Generally speaking, in order to measure both short interval, the

51、 use of two modules delay and latches, but in reality, given the time software gate large enough to allow completion from the number of CPU operation, which can be measured in the time interval taken before the end of a short period of time at t1 corresponding delay the number of units through the c

52、ontrol signals must be used only a delay and latches units, it saves CPLD internal resources. Synchronization and multi-cycle latency to quantify the method of combining The formula is:     T=n0t0+n1t1-n2t1    On, n0 for the filling pulse of value; t0 for fill

53、ing pulse cycle, that is 100 ns; n1 for a short period of time at t1 corresponding delay the number of modules; n2 for a short period of time at t2 corresponding delay unit Number; t1 quantify delay devices for the delay delay unit volume (4.3 ns). In this way, using multi-cycle synchronization and

54、realized the gate and measured signal synchronization; Delay of using quantitative measurement of the original measured not by the two short intervals, to accurately measure the size of the actual gate, it raised frequency measurement accuracy.    The frequency synthesizer output frequency

55、 signal can only be transferred to the minimum 10 Hz, XDU-17 as a standard of measurement can be calculated prototype frequency measurement accuracy.      For example, the measured signal is measured at 15.000010 MHz signal to 5.00001002, from the calculation can be seen above, t

56、he resolution of the prototype has reached ns order of magnitude below from the perspective of theoretical analysis to illustrate this point.It has been anal yzed,multi-cycle synchronization frequency measurement, the measurement uncertainty:      When the input f0 10 MHz, 1 s ga

57、te time, the uncertainty of measurement of ±1×10-7/s. When the measurement and quantification of delay circuit with short intervals combined, the uncertainty of measurement can be derived from the following.     In the use of cycle synchronization, multi-analyte Tx for the cycle value of T0 time base for the introduction of the cycle. Tx= NT0+t1-t2    Delay circuit and quantitative combined: Tx= NT0+(N1-N2)td±Tx     Here, Tx not for the accuracy of the measurement.     On the decline of the share: T