微電子工藝習(xí)題參考解答

1、CRYSTAL GROWTH AND EXPITAXY1畫出一50cm長的單晶硅錠距離籽晶10cm、20cm、30cm、40cm、45cm時砷的摻雜分布。（單晶硅錠從融體中拉出時，初始的摻雜濃度為1017cm-3）2硅的晶格常數(shù)為5.43Å假設(shè)為一硬球模型： (a)計算硅原子的半徑。 (b)確定硅原子的濃度為多少(單位為cm-3)? (c)利用阿伏伽德羅(Avogadro)常數(shù)求出硅的密度。3假設(shè)有一l0kg的純硅融體，當(dāng)硼摻雜的單晶硅錠生長到一半時，希望得到0.01 ·cm的電阻率，則需要加總量是多少的硼去摻雜?4一直徑200mm、厚1mm的硅晶片，含有5.41mg的硼均

2、勻分布在替代位置上，求： (a)硼的濃度為多少? (b)硼原子間的平均距離。5用于柴可拉斯基法的籽晶，通常先拉成一小直徑(5.5mm)的狹窄頸以作為無位錯生長的開始。如果硅的臨界屈服強(qiáng)度為2×106g/cm2，試計算此籽晶可以支撐的200mm直徑單晶硅錠的最大長度。6在利用柴可拉斯基法所生長的晶體中摻入硼原子，為何在尾端的硼原子濃度會比籽晶端的濃度高? 7為何晶片中心的雜質(zhì)濃度會比晶片周圍的大?8對柴可拉斯基技術(shù)，在k0=0.05時，畫出Cs/C0值的曲線。9利用懸浮區(qū)熔工藝來提純一含有鎵且濃度為5×1016cm-3的單晶硅錠。一次懸浮區(qū)熔通過，熔融帶長度為2cm，則在離多

3、遠(yuǎn)處鎵的濃度會低于5×1015cm-3？10從式，假設(shè)ke=0.3，求在x/L=1和2時，Cs/C0的值。11如果用如右圖所示的硅材料制造p+-n突變結(jié)二極管，試求用傳統(tǒng)的方法摻雜和用中子輻照硅的擊穿電壓改變的百分比。12由圖10.10，若Cm=20，在Tb時，還剩下多少比例的液體?13用圖10.11解釋為何砷化鎵液體總會變成含鎵比較多?14空隙ns的平衡濃度為Nexp-Es/(kT)，N為半導(dǎo)體原子的濃度，而Es為形成能量。計算硅在27、900和1 200的ns (假設(shè)Es=2.3eV)15假設(shè)弗蘭克爾缺陷的形成能量(Ef)為1.1eV，計算在27、900時的缺陷密度弗蘭克爾缺陷的

4、平衡密度是，其中N為硅原子的濃度(cm-3)，N為可用的間隙位置濃度(cm-3)，可表示為N=1×1027cm-316在直徑為300mm的晶片上，可以放多少面積為400mm2的芯片？解釋你對芯片形狀和在周圍有多少閑置面積的假設(shè)17求在300K時，空氣分子的平均速率(空氣相對分子質(zhì)量為29)圖 10.10. Phase diagram for the gallium- 圖 10.11. Partial pressure of gallium and arsenic arsenic system. over gallium arsenide as a function of temper

5、ature. Also shown is the partial pressure of silicon.18淀積腔中蒸發(fā)源和晶片的距離為15cm，估算當(dāng)此距離為蒸發(fā)源分子的平均自由程的10時系統(tǒng)的氣壓為多少?19求在緊密堆積下(即每個原子和其他六個鄰近原子相接)，形成單原子層所需的每單位面積原子數(shù)Ns假設(shè)原子直徑d為4.68Å20假設(shè)一噴射爐幾何尺寸為A=5cm2及L=12cm (a)計算在970下裝滿砷化鎵的噴射爐中，鎵的到達(dá)速率和MBE的生長速率； (b)利用同樣形狀大小且工作在700，用錫做的噴射爐來生長，試計算錫在如前述砷化鎵生長速率下的摻雜濃度(假設(shè)錫會完全進(jìn)入前述速率生

6、長的砷化鎵中，錫的摩爾質(zhì)量為118.69；在700時，錫的壓強(qiáng)為2.66×10-6Pa)21求銦原子的最大比例，即生長在砷化鎵襯底上而且并無任何錯配的位錯的GaxIn1-xAs薄膜的x值，假定薄膜的厚度是10nm22薄膜晶格的錯配f定義為，f=a0(s)-a0(f)/a0(f)a0/a0。a0(s)和a0(f)分別為襯底和薄膜在未形變時的晶格常數(shù)，求出InAs-GaAs和Ge-Si系統(tǒng)的f值Solution1. C0 = 1017 cm-3k0(As in Si) = 0.3CS= k0C0(1 - M/M0)k0-1 = 0.3´1017(1- x)-0.7 = 3

7、80;1016/(1 - l/50)0.7x00.20.40.60.80.9l (cm)01020304045CS (cm-3)3´10163.5´10164.28´10165.68´10161.07´10171.5´10172. (a) The radius of a silicon atom can be expressed as (b) The numbers of Si atom in its diamond structure are 8.So the density of silicon atoms is(c) The d

8、ensity of Si is = 2.33 g / cm3. 3. k0 = 0.8 for boron in siliconM / M0 = 0.5The density of Si is 2.33 g / cm3.The acceptor concentration for r = 0.01 Wcm is 9´1018 cm-3.The doping concentration CS is given byTherefore The amount of boron required for a 10 kg charge is boron atomsSo that.4. (a)

9、The molecular weight of boron is 10.81. The boron concentration can be given as(b) The average occupied volume of everyone boron atoms in the wafer is We assume the volume is a sphere, so the radius of the sphere ( r ) is the average distance between two boron atoms. Then .5. The cross-sectional are

10、a of the seed isThe maximum weight that can be supported by the seed equals the product of the critical yield strength and the seeds cross-sectional area:The corresponding weight of a 200-mm-diameter ingot with length l is6. The segregation coefficient of boron in silicon is 0.72. It is smaller than

11、 unity, so the solubility of B in Si under solid phase is smaller than that of the melt. Therefore, the excess B atoms will be thrown-off into the melt, then the concentration of B in the melt will be increased. The tail-end of the crystal is the last to solidify. Therefore, the concentration of B i

12、n the tail-end of grown crystal will be higher than that of seed-end.7. The reason is that the solubility in the melt is proportional to the temperature, and the temperature is higher in the center part than at the perimeter. Therefore, the solubility is higher in the center part, causing a higher i

13、mpurity concentration there.8.We haveFractional 0 0.2 0.4 0.6 0.8 1.0solidified 0.05 0.06 0.08 0.12 0.23 ¥ 9. The segregation coefficient of Ga in Si is 8 ´10-3From Eq. 18We have10. We have from Eq.18 So the ratio = = at x/L = 2.11. For the conventionally-doped silicon, the resistivity var

14、ies from 120 W-cm to 155 W-cm. The corresponding doping concentration varies from 2.5´1013 to 4´1013 cm-3. Therefore the range of breakdown voltages of p+ - n junctions is given byFor the neutron irradiated silicon, r = 148 ± 1.5 W-cm. The doping concentration is 3´1013 (±1%

15、). The range of breakdown voltage is.12. We have Therefore, the fraction of liquid remained f can be obtained as following.13. From the Fig.11, we find the vapor pressure of As is much higher than that of the Ga. Therefore, the As content will be lost when the temperature is increased. Thus the comp

16、osition of liquid GaAs always becomes gallium rich.14. = = = .15. = =at 27oC = 300 K =2.14´1014 at 900oC = 1173 K.16. 37 ´ 4 = 148 chipsIn terms of litho-stepper considerations, there are 500 mm space tolerance between the mask boundary of two dice. We divide the wafer into four symmetrica

17、l parts for convenient dicing, and discard the perimeter parts of the wafer. Usually the quality of the perimeter parts is the worst due to the edge effects.17. Where M: Molecular mass k: Boltzmann constant = 1.38´10-23 J/k T: The absolute temperature n: Speed of molecular So that.d18. .19.For

18、close-packing arrange, there are 3 pie shaped sections in the equilateral triangle. Each section corresponds to 1/6 of an atom. Therefore = =.20. (a) The pressure at 970°C (=1243K) is 2.9´10-1 Pa for Ga and 13 Pa for As2. The arrival rate is given by the product of the impringement rate an

19、d A/pL2 : Arrival rate = 2.64´1020 = 2.64´1020 = 2.9´1015 Ga molecules/cm2 s The growth rate is determined by the Ga arrival rate and is given by (2.9´1015)´2.8/(6´1014) = 13.5 Å/s = 810 Å/min .(b) The pressure at 700ºC for tin is 2.66´10-6 Pa. The m

20、olecular weight is 118.69. Therefore the arrival rate is If Sn atoms are fully incorporated and active in the Ga sublattice of GaAs, we have an electron concentration of21. The x value is about 0.25, which is obtained from Fig. 26.22. The lattice constants for InAs, GaAs, Si and Ge are 6.05, 5.65,5.

21、43, and 5.65 Å, respectively (Appendix F). Therefore, the f value for InAs-GaAs system is And for Ge-Si system is3244THERMAL OXIDATION AND FILM DEPOSITION1一p型摻雜、方向?yàn)?lt;100>的硅晶片，其電阻率為10·cm，置于濕法氧化的系統(tǒng)中，其生長厚度為0.45m，溫度為1 050試決定氧化的時間2習(xí)題1中第一次氧化后，在氧化膜上定義一個區(qū)域生長柵極氧化膜，其生長條件為1000，20 min試計算柵極氧化膜的厚度及

22、場氧化膜的總厚度3試推導(dǎo)方程式(11)當(dāng)時間較長時，可化簡為x2=Bt；時間較短時·可化簡為x=4試計算在方向?yàn)?lt;100>的硅晶片上，溫度980及l(fā)atm下進(jìn)行干法氧化的擴(kuò)散系數(shù)D5(a)在等離子體式淀積氮化硅的系統(tǒng)中，有20的氫氣，且硅與氮的比值為1.2，試計算淀積SiNxHy，中的x及y (b)假設(shè)淀積薄膜的電阻率隨5×1028exp(-33.3)而改變(當(dāng)2>>0·8)，其中為與氮的比值試計算(a)中薄膜的電阻率6SiO2、Si3N4及Ta2O5的介電常數(shù)約為3.9、7.6及25試計算以Ta2O5與SiO2：Si3N4：SiO2作為介

23、質(zhì)的電容的比值其中介質(zhì)厚度均相等，且SiO2：Si3N4：SiO2的比例亦為1：1：17續(xù)習(xí)題6，若選擇介電常數(shù)為500的BST來取代Ta2O5。試計算欲維持相等的電容值，面積所減少的比例假設(shè)兩薄膜厚度相等8續(xù)習(xí)題6，試以SiO2的厚度來計算Ta2O5的等效厚度假設(shè)兩者有相同的電容值。9在硅烷與氧氣的環(huán)境下，淀積未摻雜的氧化膜當(dāng)溫度為425時，淀積速率為15nm/min在多少溫度時，淀積速率可提高一倍?10磷硅玻璃回流的工藝需高與1000在ULSI中，當(dāng)器件的尺寸縮小時，必須降低工藝溫度試建議一些方法，可在溫度小于900的情形下，淀積表面平坦的二氧化硅絕緣層來作為金屬層間介質(zhì)11為何在淀積多晶

24、硅時，通常以硅烷為氣體源，而不以硅氯化物為氣體源?12解釋為何一般淀積多晶硅薄膜的溫度普遍較低，大約在600650之間。13一電子束蒸發(fā)系統(tǒng)淀積鋁以完成MOS電容的制作若電容的平帶電壓因電子束輻射而變動0.5V，試計算有多少固定氧化電荷(氧化膜厚度為50nm)?試問如何將這些電荷去除?14一金屬線長20m，寬0.25m，薄層電阻值為5/請計算此線的電阻值15計算TiSi2與CoSi2的厚度，其中Ti與Co的初始厚度為30nm16比較TiSi2與CoSi2在自對準(zhǔn)金屬硅化物應(yīng)用方面的優(yōu)、缺點(diǎn)17一介質(zhì)置于兩平行金屬線間其長度L=lcm，寬度W=0.28m，厚度T=0.3m兩金屬間距s為0.36m

25、. (a)計算RC時間延遲。假設(shè)金屬材料為鋁，其電阻率為2.67·cm，介質(zhì)為氧化膜，其介電常數(shù)為3.9 (b)計算RC時間延遲。假設(shè)金屬材料為銅，其電阻率為1.7·cm，介質(zhì)為有機(jī)聚合物，其介電常數(shù)為2.8 (c)比較(a)、(b)中結(jié)果，我們可以減少多少RC時間延遲?18重復(fù)計算習(xí)題17(a)及(b)假設(shè)電容的邊緣因子(fringing factor)為3，邊緣因子是由于電場線分布超出金屬線的長度與寬度的區(qū)域19為避免電遷移的問題，最大鋁導(dǎo)線的電流密度不得超過5×105 A/cm2假設(shè)導(dǎo)線長為2mm,寬為1m，最小厚度為1m，此外有20的線在臺階上，該處厚度為

26、0.5m試計算此線的電阻值假設(shè)電阻率為3×10-6·cm并計算鋁線兩端可承受的最大電壓20在布局金屬線時若要使用銅，必須克服以下幾點(diǎn)困難：銅通過二氧化硅層而擴(kuò)散；銅與二氧化硅層的附著性；銅的腐蝕性有一種解決的方法是使用具有包覆性、附著性的薄膜來保護(hù)銅導(dǎo)線考慮一被包覆的銅導(dǎo)線，其橫截面積為0.5m×0.5m與相同尺寸大小的TiN/Al/TiN導(dǎo)線相比(其中上層TiN厚度為40 nm，下層為60 nm)，其最大包覆層的厚度為多少?(假設(shè)被包覆的銅線與TiN/A1/TiN線的電阻相等)1. From Eq. 11 (with =0)x2+Ax = BtFrom Figs

27、. 6 and 7, we obtain B/A =1.5 µm /hr, B=0.47 µm 2/hr, therefore A= 0.31 µm. The time required to grow 0.45µm oxide is .2. After a window is opened in the oxide for a second oxidation, the rate constants are B = 0.01 µm 2/hr, A= 0.116 µm (B/A = 6 ×10-2 µm /hr).

28、 If the initial oxide thickness is 20 nm = 0.02 µm for dry oxidation, the value ofcan be obtained as followed: (0.02)2 + 0.166(0.02) = 0.01 (0 +)or= 0.372 hr.For an oxidation time of 20 min (=1/3 hr), the oxide thickness in the window area is x2+ 0.166x = 0.01(0.333+0.372) = 0.007or x = 0.0350

29、µm = 35 nm (gate oxide).For the field oxide with an original thickness 0.45 µm, the effectiveis given by=x2+ 0.166x = 0.01(0.333+27.72) = 0.28053or x = 0.4530 µm (an increase of 0.003µm only for the field oxide).3. x2 + Ax = B when t >> , t >> ,then, x2 = Btsimilarly,

30、when t >> , t >> , then, x = 4. At 980(=1253K) and 1 atm, B = 8.5×10-3 µm 2/hr, B/A = 4×10-2 µm /hr (from Figs. 6 and 7). Since A 2D/k , B/A = kC0/C1, C0 = 5.2×1016 molecules/cm3 and C1 = 2.2×1022 cm-3 , the diffusion coefficient is given by 5. (a) For SiNxH

31、y x = 0.83 atomic % y = 0.46The empirical formula is SiN0.83H0.46. (b) = 5× 1028e-33.3×1.2 = 2× 1011 -cmAs the Si/N ratio increases, the resistivity decreases exponentially. 6.Set Ta2O5 thickness = 3t, e1 = 25 SiO2 thickness = t, e2 = 3.9 Si3N4 thickness = t, e3 = 7.6, area = A then .

32、7. Set BST thickness = 3t, e1 = 500, area = A1 SiO2 thickness = t, e2 = 3.9, area = A2 Si3N4 thickness = t, e3 = 7.6, area = A2 then 8. Let Ta2O5 thickness = 3t, e1 = 25 SiO2 thickness = t, e2 = 3.9 Si3N4 thickness = t, e3 = 7.6 area = A then9. The deposition rate can be expressed as r = r0 exp (-Ea

33、/kT) where Ea = 0.6 eV for silane-oxygen reaction. Therefore for T1 = 698 K ln 2 = T2 =1030 K= 757 .10. We can use energy-enhanced CVD methods such as using a focused energy source or UV lamp. Another method is to use boron doped P-glass which will reflow at temperatures less than 900. 11. Moderatel

34、y low temperatures are usually used for polysilicon deposition, and silane decomposition occurs at lower temperatures than that for chloride reactions. In addition, silane is used for better coverage over amorphous materials such SiO2.12. There are two reasons. One is to minimize the thermal budget

35、of the wafer, reducing dopant diffusion and material degradation. In addition, fewer gas phase reactions occur at lower temperatures, resulting in smoother and better adhering films. Another reason is that the polysilicon will have small grains. The finer grains are easier to mask and etch to give s

36、mooth and uniform edges. However, for temperatures less than 575 ºC the deposition rate is too low.有兩個原因。一是減少硅片的熱預(yù)算，降低摻雜劑擴(kuò)散和材料的降解。此外，少氣相反應(yīng)在較低的溫度下發(fā)生，導(dǎo)致更順暢，更好的粘合膜。另一個原因是，多晶硅將有小顆粒。細(xì)顆粒容易掩模蝕刻給光滑和均勻的邊緣。然而，溫度低于575ºC沉積速率太低。13. The flat-band voltage shift is = 0.5 V . Number of fixed oxide charge i

37、s To remove these charges, a 450 heat treatment in hydrogen for about 30 minutes is required. 14.20/0.25 = 80 sqs.Therefore, the resistance of the metal line is 5´50 = 400 W .15. For TiSi2 30 ´ 2.37 = 71.1nm For CoSi2 30 ´ 3.56 = 106.8nm.16. For TiSi2: Advantage:low resistivityIt can

38、reduce native-oxide layersTiSi2 on the gate electrode is more resistant to high-field-induced hot-electron degradation. Disadvantage: bridging effect occurs.Larger Si consumption during formation of TiSi2Less thermal stabilityFor CoSi2:Advantage:low resistivityHigh temperature stabilityNo bridging e

39、ffectA selective chemical etch exitsLow shear forcesDisadvantage:not a good candidate for polycides17. (a) (b) (c) We can decrease the RC delay by 55%. Ratio = = 0.45. 18. (a) RC = 3.2 ×103 ×8.7 × 10-13 = 2.8 ns.(b) 19. (a) The aluminum runner can be considered as two segments connect

40、ed in series: 20% (or 0.4 mm) of the length is half thickness (0.5 µm) and the remaining 1.6 mm is full thickness (1µm). The total resistance is = 72 . The limiting current I is given by the maximum allowed current density times cross-sectional area of the thinner conductor sections: I = 5

41、×105 A/cm2× (10-4×0.5×10-4) = 2.5×10-3 A = 2.5 mA. The voltage drop across the whole conductor is then = 0.18V.Cu0.5 mm0.5 mm20.40 nm60 nm Al = h: height , W : width , t : thickness, assume that the resistivities of the cladding layer and TiN are much larger than When Then &

42、#222; t = 0.073 mm = 73 nm .LITHOGRAPHY AND ETHING1·對等級為100的潔凈室，試依粒子大小計算每單位立方米中塵埃粒子總數(shù) (a)0.5m到1m； (b)1m到2m； (c)比2m大 2試計算一有9道掩模版工藝的最后成品率其中有4道平均致命缺陷密度為0.1/cm2，4道為0.25cm2。，1道為1.0/cm2芯片面積為50 mm2 3一個光學(xué)光刻系統(tǒng)，其曝光功率為0.3mW/cm2。正性光刻膠要求的曝光能量為140mJ/cm2。，負(fù)性光刻膠為9mJ/cm2。假設(shè)忽略裝載與卸載晶片的時間，試比較正性光刻膠與負(fù)性光刻膠的產(chǎn)率 4(a)對波長

43、為193nm的ArF-準(zhǔn)分子激光光學(xué)光刻系統(tǒng)，其DNA=0.65，k1=0.60，k2=0.50此光刻機(jī)理論的分辨率與聚焦深度為多少? (b)實(shí)際上我們可以如何修正DNA、k1與k2參數(shù)來改善分辨率? (c)相移掩模版(PSM)技術(shù)改變哪一個參數(shù)可改善分辨率? 5右圖為光刻系統(tǒng)的反應(yīng)曲線(response curves)： (a)使用較大值的光刻膠有何優(yōu)缺點(diǎn)? (b)傳統(tǒng)的光刻膠為何不能用于248nm或193rim光刻系統(tǒng)? 6(a)解釋在電子束光刻中為何可變形狀電子束比高斯電子束擁有較高的產(chǎn)率? (h)電子束光刻圖案如何對準(zhǔn)?為何X射線光刻的圖案對準(zhǔn)如此困難? (c)X射線光刻比電子束光刻的

44、潛在優(yōu)點(diǎn)有哪些? 7·(a)為何光學(xué)光刻系統(tǒng)的工作模式由鄰近影印法進(jìn)化到投影，最后進(jìn)化到5：1的步進(jìn)重復(fù)投影法? (b)X射線光刻系統(tǒng)是否可能使用重復(fù)掃描系統(tǒng)?并說明原因 8如果掩蔽層與襯底不能被某一腐蝕劑腐蝕，試畫出下列幾種情形薄膜厚度為hf的各向異性腐蝕圖案的側(cè)邊輪廓； (a)剛好完全腐蝕； (b)100過度腐蝕； (c)200過度腐蝕 9一個<100>晶向硅晶片，利用KOH溶液腐蝕一個利用二氧化硅當(dāng)掩蔽層的1.5m×l.5m窗，垂直于<100>晶面的腐蝕速率為0.6m/min而<100>：<110>：<111>

45、;晶面的腐蝕速率比為100：16：1畫出20s、40s與60s的腐蝕輪廓10續(xù)上題，一個<10>晶向硅晶片利用薄的SiO2當(dāng)掩蔽層，在KOH溶液中藕蝕畫出<10>硅的腐蝕輪廓11一個直徑150mm<100>晶向硅晶片厚度為625m晶片上有1 000m×1 000m的IC這些IC是利用各向異性腐蝕的方式來隔開試用兩種方法來完成此工藝，并計算使用這兩種工藝方法損失的面積所占的比例 12粒子碰撞平均移動的距離稱為平均自由程，5×1 0-3/p(cm)，其中P為壓強(qiáng)，單位為Torr一般常用的等離子體，其反應(yīng)腔壓強(qiáng)范圍為1Pa150Pa其相關(guān)的氣體

46、濃度(cm-3)與平均自由程是多少? 13氟原子(F)刻蝕硅的刻蝕速率為： 刻蝕速率(nm/min)=2.86×10-13×nF×T1/2exp(-Ea/RT)其中nF為氟原子的濃度(cm-3)，T為絕對溫度(K)，Ea與R分別為激活能(10.416kJ/mol)與氣體常數(shù)(8.345JK)如果nF為3×l015cm-3，試計算室溫時硅的刻蝕速率1 4續(xù)上題，利用氟原子一樣可以刻蝕SiO2，刻蝕速率可表示為 刻蝕速率(nm/min)=0.614×10-13×nF×T1/2exp(-Ea/RT)其中nF為3×1015

47、cm-3，Ea為15.12kJ/mol計算室溫時SiO2的刻蝕速率及SiO2對Si的刻蝕選擇比1 5可以用多重步驟的刻蝕工藝來刻蝕薄柵極氧化層上的多晶硅柵極如何設(shè)計一個刻蝕工藝使之滿足：沒有做掩蔽效應(yīng)(micrornasking)、各向異性刻蝕、對薄的柵極氧化層有適合的選擇比?16刻蝕400 nm多晶硅而不會移去1 nm厚的底部柵氧化層，試找出所需的刻蝕選擇比?假設(shè)多晶硅的刻蝕工藝有10的刻蝕速率均勻度171 um厚的A1薄膜淀積在平坦的場氧化層區(qū)域上并且利用光刻膠來定義圖案接著金屬層利用Helicon刻蝕機(jī)，混合BCI3/Cl2氣體。在溫度為70 ºC來刻蝕A1與光刻膠的刻蝕選擇比

48、維持在3假設(shè)有30的過度刻蝕，試問為確保頂部的金屬不被侵蝕·所需光刻膠的最薄厚度為多少?18在ECR等離子體中，一個靜磁場B驅(qū)使電子沿著磁場隨一個角頻率做圓周運(yùn)動e=qB/me，其中q為電荷、me為電子質(zhì)量如果微波的頻率為2.45GHz，試問所需的磁場太小為多少?19傳統(tǒng)的反應(yīng)離子刻蝕與高密度等離子體(ECR，ICP等)相比，最大的區(qū)別是什么?20敘述如何消除Al金屬線在氯化物等離子體刻蝕后所造成的腐蝕1. With reference to Fig. 2 for class 100 clean room we have a total of 3500 particles/m3 wi

49、th particle sizes 0.5 µm = 735 particles/m2 with particle sizes 1.0 µm= 157 particles/m2 with particle sizes 2.0 µmTherefore, (a) 3500-735 = 2765 particles/m3 between 0.5 and 1 µm(b) 735-157 = 578 particles/m3 between 1 and 2 µm(c) 157 particles/m3 above 2 µm.2.A = 50 m

50、m2 = 0.5 cm2 . 3. The available exposure energy in an hour is 0.3 mW2/cm2 × 3600 s =1080 mJ/cm2For positive resist, the throughput isFor negative resist, the throughput is .4. (a) The resolution of a projection system is given by µm= 0.228 µm(b) We can increase NA to improve the resol

51、ution. We can adopt resolution enhancement techniques (RET) such as optical proximity correction (OPC) and phase-shifting Masks (PSM). We can also develop new resists that provide lower k1 and higher k2 for better resolution and depth of focus.(c) PSM technique changes k1 to improve resolution.5. (a

52、) Using resists with high value can result in a more vertical profile but throughput decreases.(b) Conventional resists can not be used in deep UV lithography process because these resists have high absorption and require high dose to be exposed in deep UV. This raises the concern of damage to stepp

53、er lens, lower exposure speed and reduced throughput.6. (a)A shaped beam system enables the size and shape of the beam to be varied, thereby minimizing the number of flashes required for exposing a given area to be patterned. Therefore, a shaped beam can save time and increase throughput compared to

54、 a Gaussian beam. (b) We can make alignment marks on wafers using e-beam and etch the exposed marks. We can then use them to do alignment with e-beam radiation and obtain the signal from these marks for wafer alignment.X-ray lithography is a proximity printing lithography. Its accuracy requirement i

55、s very high, therefore alignment is difficult.(c)X-ray lithography using synchrotron radiation has a high exposure flux so X-ray has better throughput than e-beam.7. (a) To avoid the mask damage problem associated with shadow printing, projection printing exposure tools have been developed to projec

56、t an image from the mask. With a 1:1 projection printing system is much more difficult to produce defect-free masks than it is with a 5:1 reduction step-and-repeat system.(b) It is not possible. The main reason is that X-rays cannot be focused by an optical lens. When it is through the reticle. So we can not build a step-and-scan X-ray lithography system.8. As shown in the figure, the profile for each case is a segment of a circle with origin at the initial