chapter6數(shù)字IC后端流程課件

1、CMOS集成電路版圖鄧軍概念、方法與工具第6章 數(shù)字IC后端流程2022/7/231數(shù)字IC后端流程 PlacementDesign planningCTS RouteDFM & Chip Finishing Data Setup2022/7/232基于ICC的數(shù)字IC后端設(shè)計(jì)流程Use IC Compiler to perform placement, DFT, CTS, routing and optimization, achieving timing closure for designs with moderate to high design chall

2、enges.2022/7/233基于ICC的數(shù)字IC后端設(shè)計(jì)流程There is no “golden script” for physical design2022/7/234Data Setup布局布線(xiàn)的準(zhǔn)備工作，讀入網(wǎng)表，跟Foundry提供的STD Cell、Pad庫(kù)以及Macro庫(kù)進(jìn)行映射。2022/7/235Data Setup后端設(shè)計(jì)數(shù)據(jù)準(zhǔn)備設(shè)計(jì)網(wǎng)表 gate-level netlist設(shè)計(jì)約束文件 SDC file物理庫(kù)文件 sc.lef/io.lef/macro.lef時(shí)序庫(kù)文件 sc.lib/io.lib/macro.libI/O文件 I/O constraints fil

3、e（.tdf）工藝文件 technology file（.tf）RC模型文件 TLU+2022/7/236Data SetupLogical LibrariesProvide timing and functionality information for all standard cells (and, or, flipflop, )Provide timing information for hard macros (IP, ROM, RAM, )Define drive/load design rules: Max fanout Max transition Max/Min capaci

4、tanceAre usually the same ones used by Design Compiler during synthesisAre specified with variables: target_library link_library2022/7/237Data Setup邏輯單元庫(kù)：一個(gè)完整的單元庫(kù)由不同的功能電路所組成，種類(lèi)和數(shù)量很多，根據(jù)其應(yīng)用可分為三類(lèi)：標(biāo)準(zhǔn)單元（standard cells）組合邏輯時(shí)序邏輯模塊宏單元（macro block）ROMRAM專(zhuān)用模塊（如ASSP、DSP等）Black box商業(yè)IP（如ARM、標(biāo)準(zhǔn)單元等）模擬模塊（如PLL、振蕩器等

5、）輸入輸出單元（I/O pad cell）輸入輸出三態(tài)雙向考慮ESD2022/7/238Data SetupPhysical Reference Libraries2022/7/239Data Setup物理單元庫(kù)：和邏輯單元庫(kù)分類(lèi)相同，但也包括一些特殊單元，在后端物理實(shí)現(xiàn)中的作用有別于其他邏輯電路填充單元（filler/spacer）I/O spacer用于填充I/O單元之間的空隙以形成power ring標(biāo)準(zhǔn)單元filler cell與邏輯無(wú)關(guān)，用于把擴(kuò)散層連接起來(lái)滿(mǎn)足DRC規(guī)則和設(shè)計(jì)需求，并形成power rails電壓鉗位單元（tie-high/tie-low）二極管單元（diode）

6、，對(duì)違反天線(xiàn)規(guī)則的柵輸入端加入反偏二極管，避免天線(xiàn)效應(yīng)將柵氧擊穿時(shí)鐘緩沖單元（clock buffer/clock inverter）：為最小化時(shí)鐘偏差（skew），插入時(shí)鐘緩沖單元來(lái)減小負(fù)載和平衡延時(shí)延時(shí)緩沖單元（delay buffer）：用于調(diào)節(jié)時(shí)序阱連接單元（well-tap cell）：主要用于限制電源或地與襯底之間的 電阻大小，減小latch-up效應(yīng)電壓轉(zhuǎn)換單元（level-shifter）：多用于低功耗設(shè)計(jì)2022/7/2310Data Setup庫(kù)文件時(shí)序庫(kù)：描述單元庫(kù)中各個(gè)單元時(shí)序信息的文件。（.lib庫(kù)）單元延時(shí)互連線(xiàn)延時(shí)物理庫(kù)：是對(duì)版圖的抽象描述，她使自動(dòng)布局布線(xiàn)成為可

7、能且提高了工具效率（.lef庫(kù)），包含兩部分技術(shù)LEF：定義布局布線(xiàn)的設(shè)計(jì)規(guī)則和foundry的工藝信息單元LEF：定義sc、macro、I/O和各種特殊單元的物理信息，如對(duì)稱(chēng)性、面積大小、布線(xiàn)層、不可布線(xiàn)區(qū)域、天線(xiàn)效應(yīng)參數(shù)等2022/7/2311Data SetupThe Technology File (.tf file)：The technology file is unique to each technology；Contains metal layer technology parameters: Number and name designations for each laye

8、r/via Physical and electrical characteristics of each layer/via Design rules for each layer/Via (Minimum wire widthsand wire-to-wire spacing, etc.) Units and precision for electrical units Colors and patterns of layers for display 2022/7/23121. Specify the Logical Libraries2022/7/23132. Define logic

9、0 and logic12022/7/23143. Create a “Container”: The Design Library2022/7/23154. Specify TLU+ Parasitic RC Model FilesTLU+ is a binary table format that stores the RC coefficients2022/7/2316Timing is Based on Cell and Net Delays2022/7/23175. Create Design CEL2022/7/23186. Verify Logical Libraries Are

10、 Loaded2022/7/23197. Define Logical Power/Ground Connections2022/7/23208. Apply and Check Timing Constraints2022/7/23219. Remove Unwanted “Ideal Net/Networks”2022/7/232210. Save the DesignIts good practice to save the design after each key design phase, for example: data setup, design planning, plac

11、ement, CTS and routing: Note: The open cell is still the original ORCA cell !save_mw_cel as ORCA_data_setup2022/7/2323數(shù)字IC后端流程 PlacementDesign planningCTS RouteDFM & Chip Finishing Data Setup2022/7/2324Design Planning芯片設(shè)計(jì)的物理實(shí)施通常被簡(jiǎn)稱(chēng)為布局布線(xiàn)（P&R，Place-and-Route），而P&R之前的大量工作，包括Data Setup、Floor-plan、power-

12、plan亦非常關(guān)鍵。布圖規(guī)劃的主要內(nèi)容包括芯片大?。╠ie size）的規(guī)劃、I/O規(guī)劃、大量硬核或模塊（hard core、block）的規(guī)劃等，是對(duì)芯片內(nèi)部結(jié)構(gòu)的完整規(guī)劃和設(shè)計(jì)。布圖規(guī)劃的合理與否直接關(guān)系到芯片的時(shí)序收斂、布線(xiàn)通暢（timing and routability）。Create a floorplan that is likely to be routable and achieve timing closure2022/7/2325ICC TerminologyDesign planning is the iterative process of creating a fl

13、oorplan。A chip-level floorplan entails defining: Core size, shape and placement rows Periphery: IO, power, corner and filler pad cell locations Macro cell placement Power grid (rings, straps, rails)A physical design, or layout, is the result of a synthesized netlist that has been placed and routed20

14、22/7/2326Create Physical-only Pad CellsPhysical-only pad cells (VDD/GND, corner cells) are not part of the synthesized netlist Must be created prior to specifying the pad cell locationsopen_mw_cel DESIGN_data_setupcreate_cell vss_l vss_r vss_t vss_b pv0icreate_cell vdd_l vdd_r vdd_t vdd_b pvdicreate

15、_cell CornerLL CornerLR CornerTR CornerTL pfrelr2022/7/2327Specify Pad Cell Locations2022/7/2328Initialize the Floorplan2022/7/2329Core Area Parameters2022/7/2330Floorplan After Initialization2022/7/2331Insert Pad Filler Cellsinsert_pad_filler cell “fill5000 fill2000 fill1000 . 2022/7/2332Constraini

16、ng Macros：Manually2022/7/2333Macro Constraints: Anchor Bound Option2022/7/2334Macro Constraints: Side Channel OptionSide channels are regions along the core edges where placement of macros is not allowed.set_fp_macro_array name ARRAY_A elements get_cells “A1 A2 A3” set_fp_macro_options ARRAY_A side_

17、channel “0 80 30 40”2022/7/2335電源規(guī)劃電源規(guī)劃是給整個(gè)芯片的供電設(shè)計(jì)出一個(gè)均勻的網(wǎng)絡(luò)。電源預(yù)算（power budgeting），商用慣例為誤差在5%，包括從電源網(wǎng)絡(luò)和PCB板級(jí)到封裝bonding之間的波動(dòng)（1%）電源I/O單元和電源環(huán)之間的波動(dòng)（1%）最終到sc之間的電壓降（3%）2022/7/2336電源網(wǎng)絡(luò)設(shè)計(jì)全局電源電源環(huán)線(xiàn)（power ring）指為了均勻供電，包圍在sc周?chē)沫h(huán)形供電金屬，用于連接電源I/O單元和sc的followingpins電源條線(xiàn)（power strips）指芯片內(nèi)部縱橫交錯(cuò)的電源網(wǎng)格（power grid）2022/7/23

18、37Power plan2022/7/2338Write Out Floorplan and DEF Files設(shè)計(jì)交換格式DEF（design exchange format）文件是由Cadence公司開(kāi)發(fā)的用于描述文件物理設(shè)計(jì)信息的一種文件格式。DEF描述了芯片的die area、row、tracks、components、nets等對(duì)于設(shè)計(jì)者而言，有了LEF和DEF文件就可以完整的了解一個(gè)設(shè)計(jì)2022/7/2339數(shù)字IC后端流程 PlacementDesign planningCTS RouteDFM & Chip Finishing Data Setup2022/7/2340Plac

19、ement布局的主要任務(wù)是sc的擺放和優(yōu)化布局算法一直是EDA設(shè)計(jì)中的研究重點(diǎn)，目前仍在發(fā)展。 In most situations macro cell placement is determined during design planning and their placement is “fixed” It is a good practice to fix all macro placements again, just in case.2022/7/2341Placement2022/7/2342數(shù)字IC后端流程 PlacementDesign planningCTS RouteData Setup2022/7/2343芯片中的時(shí)鐘網(wǎng)絡(luò)要驅(qū)動(dòng)電路中所有的時(shí)序單元，所以時(shí)鐘負(fù)載延時(shí)很大并且不平衡，需要插入緩沖器減小負(fù)載和平衡延時(shí)。時(shí)鐘網(wǎng)絡(luò)及其上的緩沖器構(gòu)成了時(shí)鐘樹(shù)。CTS的目的是為了減小時(shí)鐘偏差（clock skew）時(shí)鐘信號(hào)定義SDCCTS策略時(shí)鐘樹(shù)分析 Clock Tree Synthesis2022/7/2344Starting Point before CTSA