教程-專(zhuān)業(yè)英語(yǔ)計(jì)算機(jī)

1、計(jì)算機(jī)時(shí)讀(967)PCI Express pumps up performancehe past decade, PCI has served as the dominant I/O PCs and servers, carrying data generated by micropro adapters, graphics cards and other subsystems to whicharchitecture for sors, networkit is connected.However, as the speed and capabilities of computing co

2、mponents increase,PCIs bandwidth limiions andthe inefficiencies of its parallelarchitecture increasingly havee bottlenecks to systembus architecture in whiperformance. ultipleperformance ofPCI is aadapters the PCIunidirectional parallelmust contend for availabus bandwidth. Althougherface has been im

3、proved over the years, problems with signalskew (when bits of data arrive at their destination too late), routing and the inability to lower the voltage or increase the strongly indicate t the architecture is running out ofAdditional attempts to improve its performance would be costlysignal frequenc

4、y,.andimpractical. In response, agroup of vendors, including some of thelargest and most I/O architecture I/O, or 3GIO).PCI Express is asucsfulsystem developershe industry, unveiled andubbed PCIExpress (initially called Third Generationpo-to-poswitching architecturet createsI/O (the switch links can

5、high-speed, bidirectional links betn a Cnd systemis connected to the CPU by a host bridge). Each of thesepass one or more “l(fā)anes”comprising four wirestwo for transmittingdata and two for receiving data. The design of these lanables the useof lower voltages (resulting in lowower usage), redusignal sk

6、ew, lowers costs through performance.electromagnetic emiss, eliminatessimpler design and generally improvesIn its initial implemenion, PCI Express can yield transfer speedsofof2.5G bit/sec in each direction, on each lane. By contrast, the verthe Prchitecturet is most commontoday, PCI-X 1.0, offers 1

7、Gare available in four- or x8). An x4 PCI Express cardbit/sec eight-laneprovide ashroughput. PCI Express cardsconfigurations (called x4 andcanmuch as 20G bit/sechroughput, while an x8 PCI Express cardhroughput.can offer up to 40G bit/secEarr attempts to create a new Prchitecture failed in part becau

8、se they required so many changes to the system and application software.Drivers, utilities and management applications all would have to berewritten. PCI Express developers removed the dependency on new operatingsystem support, lettingpatible drivers and applications rununchanged oI Express hardware

9、.A bus for the futureDevelopers are current servergraphics cardsworking on increasing the scalability of PCI Express. Whileand desktop systempport PCI Express adapters andwith up to eight lanes (x8), the architecture will supportas many as 32 lanes (x32)hefuture.adapters were designed to support fou

10、r part because server developers hadTheFibre Channel host buslanes instead of eight designed their systemsrequired, implementinglanes, inwith four-lane slots. As even more bandwidth isan eight-lane design potentially could double theperformance, provided there were no other bottleneckshe system.This

11、 scalability, along with the expected doubling of the speed of eachlane to 5G bit/sec, should keep PCI Express adesigners for the foreseeable future.viable solution forPCI Expressis a significant improvement ovthe new standard for PCs, serversnd is well on its wayand more. Not only can ittoinglower

12、costsand improve reliability, but it also significantly can improveperformance. Applicationch as music andstreaming,ondemand, VoIP and data storage will benefit from these improvements.PCI Express 總線(xiàn)性能在過(guò)去十，PCI 總線(xiàn)一直是 PC 機(jī)和服務(wù)器上的主流 I/O 架構(gòu)，它負(fù)責(zé)將微處理器、網(wǎng)卡、圖形卡和其他子系統(tǒng)生成的數(shù)據(jù)送到與它相連的。然而，隨著計(jì)算的速度和能力的提高，PCI 并行架構(gòu)的帶寬局限

13、性和低效率越來(lái)越成為系統(tǒng)性能的瓶頸。PCI 是一個(gè)單向的并行總線(xiàn)架構(gòu)，其中多個(gè)適配器必須爭(zhēng)奪可用的總線(xiàn)帶寬。雖然 PCI 接口的性能幾年來(lái)不斷得到改進(jìn)，但信號(hào)偏離（數(shù)據(jù)位到達(dá)目的地太晚）、信號(hào)路由、以及電壓無(wú)法降低或頻率更高時(shí)就不能正常工作等問(wèn)題，無(wú)不表明該架構(gòu)走到了盡頭。改進(jìn)其性能的設(shè)想代價(jià)很高，也不實(shí)際。針對(duì)此問(wèn)題，一些廠(chǎng)商（包括最大的和最成功的系統(tǒng)開(kāi)發(fā)商）了一個(gè)叫 PCIExpress（最初叫第三代 I/O，縮寫(xiě)為 3GIO）的 I/O 架構(gòu)。PCIExpress 是一個(gè)點(diǎn)對(duì)點(diǎn)的交換架構(gòu)，在 CPU 和系統(tǒng) I/O 之間建立高速的雙向鏈路（交換機(jī)由主橋接到 CPU）。每一個(gè)鏈路可以包含一

14、個(gè)或多個(gè)由四條電線(xiàn)組成的“通道”，其中兩條線(xiàn)發(fā)送數(shù)據(jù)，兩條線(xiàn)接收數(shù)據(jù)。這些通道的設(shè)計(jì)能允許在低壓下使用（這樣功率消耗較少）、降低電磁輻射、消除信號(hào)偏離、以及簡(jiǎn)化設(shè)計(jì)帶來(lái)的成本降低，總的來(lái)說(shuō)改進(jìn)了性能。在其最初的實(shí)現(xiàn)中，PCI Express 就能保證在每個(gè)通道上雙向的傳輸速度達(dá)到2.5G位/秒。而目前最常見(jiàn)的 PCI 架構(gòu)版本PCI-X1.0 提供的吞吐量為 1G 位/秒。目前能得到的 PCI Express 卡為 4 通道或 8 通道的配置（叫 x4 和x8）。x4 PCIExpress 卡能提供的吞吐量達(dá)到 20G 位/秒，而 x8 PCI Express 卡能提供的吞吐量則高達(dá) 40G 位/秒。早期創(chuàng)建新的 PCI 架構(gòu)的設(shè)想之所以失敗了，是因?yàn)橐笙到y(tǒng)和應(yīng)用的修改，驅(qū)動(dòng)程序、例行程序和管理應(yīng)用程序全都必須重寫(xiě)。PCI做太多Express 開(kāi)發(fā)者消除了對(duì)新操作系統(tǒng)支持的依賴(lài)，讓與 PCI 兼容的驅(qū)動(dòng)程序和應(yīng)用程序無(wú)需更改就能在 PCI Express 硬件上運(yùn)行。未來(lái)的總線(xiàn)目前，開(kāi)發(fā)者正在研究如何提高 PCI Express 的可擴(kuò)展性。現(xiàn)在的服務(wù)器和臺(tái)式系統(tǒng)支持多達(dá) 8 通道（x8）的 PCIExpress 卡和圖形卡，而將來(lái)該架構(gòu)能支持多達(dá) 32 通道（x32）。第一個(gè)光纖通道的主總線(xiàn)適配器設(shè)計(jì)成支持 4 通道，不是 8 通道，部分原因是由于服務(wù)