基于51單片機(jī)的寬帶放大器vca810翻譯

1、VCA810 翻譯FEATURES_ HIGH GAIN ADJUST RANGE: _40dB_ DIFFERENTIAL IN/SINGLE-ENDED OUT_ LOW INPUT NOISE VOLTAGE: 2.4nV/_Hz_ CONSTANT BANDWIDTH vs GAIN: 35MHz_ HIGH dB/V GAIN LINEARITY: _0.3dB_ GAIN CONTROL BANDWIDTH: 25MHz_ LOW OUTPUT DC ERROR: 80dB. Signal bandwidndslew rate remain constant over the en

2、tire gain adjust range. This 40dB/V gain control is accurate within 1.5dB (0.9dB for High Grade), allowing the gain control voltage in an AGC application to be used as a Received Signal Strength Indicator (RSSI) with 1.5dB accuracy.Excellent common-mode rejection and common-mode input range at the t

3、wo high-impedance inputs allow the VCA810 to provide a differential receiver operation with gain adjust. Theoutput signal is referenced to ground. Zero differential inputvoltage gives a 0V output wismall DC offset error. Lowinput noise voltage ensures good output SNR at the highest gain settings.In

4、applications where pulse edge information is critical, andthe VCA810 is being used to equalize varying channel loss,minimal change in group delay over gain setting will retain excellent pulse edge information.An improved output stage provides adequate outpurrentto drive the most demanding loads. Whi

5、le principallyendedto driveog-to-digital converters (A) or 2nd-stagelifiers, the 60mA outp doubly-terminated 50 lines orover the 1.7V output voltage range.urrent will easily drivesivet filter stageThe VCA810 is a high gain adjust range, wideband,voltagelifier wivoltage-controlled gain, as shownin Fi

6、gure 1. The circuits basic voltagelifier respondslifier. At itsto the control of aninput, the voltageernal gain-controllifiresents the high impedance ofa differential stage, permitting flexible input impedancematching. To preserve termination options, noernalcircuitry connects to the input bases of

7、this differential stage. For this reason, the user must provide DC paths for the input base currents from a signal source, either through a grounded termination resistor or by a direct connectionto ground. The differential input stage also permitsrejection of common-mode signals. At its output, thev

8、oltagelifiresents a low impedance, simplifyingimpedance matching. An open-loop design produwidebandwidt all gain settings. A ground-referenceddifferential to single-ended converthe low output offset voltage.at the output retainsA gain control voltage, VC, controls thelifier gainmagnitude through a h

9、igh-speed control circuit. Gainpolarity can be either inverting or non-inverting, dependingupon thelifier input driven by the input signal. The gaincontrol circuit presents the high-input impedance of anon-inverting opconnection. The control voltagnis referred to ground as shown in Figure 1. The con

10、trolvoltage VC varies thelifier gain according to theexponential relationship G_V_V_ _ 10_2(VC_1).This translates to the log gain relationshipG(dB) 40 _ _VC_1_ dB. Thus, G(dB) varies linearlyover the specified 40dB to +40dB range as VC varies from0V to 2V. Optionally, making VC slightlyitive (+0.15V

11、) effectively disables thelifier, giving 80dB ofsignal pattenuationow frequencies.ernally, the gain-control circuit varies thelifier gainby varying the transconductance, gm, of aolartransistor using the transistor bias current. Varying the bias currents of differential stages varies gm to control th

12、e voltage gain of the VCA810. A gm-based gain adjust normally suffers poor thermal stability. The VCA810 includes circuitry to minimize this effect.Figure 2 shows the circuit configuration used as the basisof the Electrical Characteristics and TypicalCharacteristics. Voltage swings reportedhespecifi

13、cations are taken directly at the input and outputpins. For test pures, the input impedance is set to 50to ground. A 25wi(RT) isincluded on the V input to get bias current cancellation. Proper supply bypassing is shown in Figure 2, andconsists of two capacitors on each supply pin: one largeelectroly

14、tic capacitor (2.2F to 6.8F), effectiveowerfrequencies, and one small ceramic capacitor (0.1F) forhigh frequency decoupling. For more information ondecoupling, refer to thLayout section.The voltage-controlled gain feature of the VCA810 makesthislifier ideal for preciAGC applications withcontrol rang

15、es as large as 60dB. The AGC circuit ofFigure 4 adds an opand diode forlitudedetection, a hold capacitor to store the control voltage andresistors R1 through R3t determine attack and releasetimes. Resistor R4 and capacitor the AGC feedback loop. The opitive peaks of output VO wihase compensate compa

16、res theDC reference voltage,VR. Whenever a VO peak exceeds VR, the OPA820 outputswingsitive, forward-biasing the diode and chargingthe holding capacitor. This charge drives the capacitorvoltage in aitive direction, reducing thelifier gain.R3 and the CH largely determine the attack time of this AGC c

17、orrection.特點(diǎn):高增益的調(diào)整范圍: 40dB差分輸入/單端輸出輸入噪聲電壓:2.4nV/_Hz穩(wěn)定的增益帶寬：35MHz高分貝增益線性: 0.3dB / V增益控制帶寬: 25MHz低產(chǎn)出的直流誤差: 80dB。信號帶寬和壓擺率保持在整個增益調(diào)節(jié)范圍內(nèi)保持恒定。這 40db/ V 增益控制在1.5 db（最高誤差范圍0.9 db），讓應(yīng)用程序在一個 AGC 增益控制電壓精確到作為接收信號強(qiáng)度指示器（RSSI）的使用精度為1.5 db。出色的共模抑制和兩個高阻抗輸入的共模輸入范圍允許 VCA810 提供一個增益調(diào)節(jié)差分接收器的操作。輸出信號是相對于地面。零差分輸入電壓提供了一個帶有小的

18、直流偏移誤差 0V 輸出。低輸入噪聲電壓，確保在最高增益設(shè)置好輸出信噪比。在應(yīng)用脈沖邊緣信息是 的，正在使用的 VCA810 變信道損失，以平衡，最小增益設(shè)置的變動將在留住優(yōu)秀延遲脈沖的邊緣信息。一種改進(jìn)的輸出級提供了足夠的輸出電流來驅(qū)動最苛刻的負(fù)載。而主要用于驅(qū)動模擬到數(shù)字轉(zhuǎn)換器（ADC）或第二級放大器， 60mA 的輸出電流將輕松驅(qū)動雙端 50 或 后在 1.7V的輸出電壓范圍篩選階段。電源 6.5VDC功耗見熱分析組差分輸入電壓Vs輸入共模電壓范圍Vs溫度范圍.-40 C 至+125 C引線溫度（焊接，10 秒）+300 C結(jié)溫+150的額定 ESD（ 模型）V（電荷器件模型）V（機(jī)器模

19、型）V以上這些等級，就可能造成性。長時間在絕對最大條件可能會降低器件的可靠性。這些僅僅是極限參數(shù)，以及設(shè)備的功能操作在這些或超出規(guī)定的，并不意味著在任何其他條件者。靜電放電敏感度這可能會損壞集成電路的靜電放電。德州儀器建議所有集成電路用適當(dāng)?shù)念A(yù)防措施處理。如果正確的搬運(yùn)和安裝程序，可以造成損壞。ESD 損害的范圍可以從細(xì)微的性能下降，完成設(shè)備故障。精密集成電路可能更容易受到，因?yàn)楹苄〉膮?shù)變化可能導(dǎo)致設(shè)備不能滿足其的規(guī)格。應(yīng)用信息電路描述該 VCA810 是一種高增益調(diào)整了電壓控制增益，如圖 1 所示，范圍，寬帶，電壓放大器。該電路的基本電壓放大器響應(yīng)了增益控制放大器控制。在它的輸入，電壓放大

20、器介紹了高阻抗的差分階段，允許靈活的輸入阻抗匹配。為了終端的選擇，沒有電路連接到這個階段的差分輸入。出于這個原因，用戶必須為從信號源輸入基本直流電流路徑，通過一個終端電阻接地或直接連接到地。差分輸入級也允許共模信號的抑制。在其輸出端，電壓放大器提出一個低阻抗，從而簡化了阻抗匹配。開環(huán)設(shè)計(jì)生產(chǎn)在所有增益設(shè)置寬的帶寬。以地為參考的差分至單端輸出的轉(zhuǎn)換會保留在低輸出失調(diào)電壓。一個增益控制電壓 VC，控制通過一個高速控制電路放大器增益的大小。增益可以是極性反相或非反相，經(jīng)輸入信號驅(qū)動放大器的輸入而定。增益控制電路提出了一個非反相運(yùn)算放大器連接高輸入阻抗?？刂齐妷阂_被稱為接地。這關(guān)系到增益與 db 的關(guān)系式： Gdb=-40（Vg+1）db。因此，db 線性變化在指定的- 40dB至+40 dB