3,4,5分頻電路設計并仿真

1,使用原理圖文件設計三分頻電路:仿真需要設置function功能，然后生成網(wǎng)表(processing)^HieiaiEhj.1@|Filf±|rf?DesignIooIefzinxiwUd.p￡cTi?r-itcFiin■:tiflDi-ilSinraldtao?Wtllist祖PnDjertNa','iaatnrSluil「MEiilMi口dl-uuiSjffliilitiwiChl+jbjft+Ji囪UWi^HieiaiEhj.1@|Filf±|rf?DesignIooIefzinxiwUd.p￡cTi?r-itcFiin■:tiflDi-ilSinraldtao?Wtllist祖PnDjertNa','iaatnrSluil「MEiilMi口dl-uuiSjffliilitiwiChl+jbjft+Ji囪UWiII：EFKWTIOTSHo%-.|Tt]11Iiftsip.Cwj-i1-irlaalS^rvnlitarTa-alF'習口“Ha:liaiufAatl^-￡?rToni0Tdvk-FIF-3H?rAnil^tHrTddIttrl4：LMrCHI工￡]MTjteCurr.aiPil.眈Stnar?:Sii'il-iti-jciSlrinl-itidCLH?bii4SlrmL-itianBl^partCtrl和Ctfl+SbJfHEM-snar^-IillLLbIixataanFa!■Ce?^i1LLiaa.I;Ctrl+：BQuastasII-P±/Pomloa(i/FP*&&/e：onEc/0i8S?：Vfsiniii- -[SisiiLlationReport\□g舄n峽。cm?gtojPffl■:?3in4 Ctrl+5bifHC|尊t業(yè)6fvErC-jiCt仿真結果:1Ejmla.lL仿真結果:1Ejmla.lLSeVLL&csaliVivi-fcaHi.J:ilHOl航i.?nCi?<iCQ2,使用Verilog程序設計三分頻，四分頻，五分頻設計三分頻：modulesanfp(clkin,clkout);inputclkin;outputclkout;reg[1:0]step1,step;always@(posedgeclkin)begincase(step)2'b00:step<=2'b01;2'b01:step<=2'b10;2'b10:step<=2'b00;default:step<=2'b00;endcaseendalways@(negedgeclkin)begincase(step1)2'b00:step1<=2'b01;2'b01:step1<=2'b10;2'b10:step1<=2'b00;default:step1<=2'b00;endcaseendassignclkout=~(step1[1]|step[1]);endmodule5hM?ld41*k.■?TtTHmSettincsSljr<il4,Usn.HfiiSimliliinCivir■￡?curUem-5hM?ld41*k.■?TtTHmSettincsSljr<il4,Usn.HfiiSimliliinCivir■￡?curUem-SlriOl^UibtideFiuwU￡<1*1厚MwJffTneBu: U.5Sits*|fe|Pania: 153.73niHsi由|-3ftZ1ra EE:snGrvrwk^B2nztMr/jiircici- -[siiMiAii?n-5iaMlh1i?k? 選出氏導S土u|妙SkiktaUAtMIt岬oil?SliinhUlonWwd謝it惜S1JFK114.USDEiJ'SirtL?E<-?taciPit*Sumktj?Fit/^etUl^S四分頻:modulesifenp(clkin,clkout);inputclkin;outputclkout;reg[1:0]countl;always@(posedgeclkin)begincase(count1)2'b00:count1<=2'b01;2'b01:count1<=2'b10;2'b10:count1<=2'b11;2'b11:count1<=2'b00;defaultcount1<=2'b00;endcaseendassignclkout=count1[1];endmodule五分頻:modulefivefp(clkin,clkout,clkout1,clkout2);inputclkin;outputclkout,clkout1,clkout2;reg[2:0]cntl,cnt2;always@(posedgeclkin)begincase(cnt1)3'b000:cnt1<=3'b001;3'b001:cnt1<=3'b010;3'b010:cnt1<=3'b100;3'b100:cnt1<=3'b101;3'b101:cnt1<=3'b000;defaultcnt1<=3'b000;endcaseendalways@(negedgeclkin)begincase(cnt2)3'b000:cnt2<=3'b001;3'b001:cnt2<=3'b010;3'b010:cnt2<=3'b100;3'b100:cnt2<=3'b101;3'b101:cnt2<=3'b000;defaultcnt2<=3'b000;endcaseendassignclkout=cnt1[2]|cnt2[2];assignclkout1=cnt1[2];assignclkout2=cnt2[2];endmodule采用2個計數(shù)器cnt1和cnt2Cnt1需要在第3個clk上升沿時翻轉(zhuǎn)，而且計數(shù)最高位要為1,即100.而后面計數(shù)需要保持2個周期的高，這樣總共五個周期，只是占空比不為50%。Cnt2在第4個clk下降沿)時翻轉(zhuǎn)，相對于cnt1延遲半個周期翻轉(zhuǎn)。仿真圖如下圖免?”.SSHuiE母國Ucw5nmrr點ji畦]jlovd饑山中E1SiBula-lrr邕耳5?*-wym齊.；*ianoSiwtJ