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Improvingyourprocessforhigh-speedPCBdesign“Closingtheloopbetweentiminganalysisandsignalintegrity”APCBKnowledgeSetOnlineSeminarfromCadencepresentedbyToddWesterhoffSystemTimingSignalIntegrity1第1頁AgendaBasicsofsystemtiminganalysisBasicsofsignalintegrityanalysisFlighttime,bufferdelay,standardloadsandTcoKeyprocessassumptionsCheckingandverifyingmodeldataTechniquesforclosingtheloopSummary2第2頁StaticTimingAnalysisSystematicanalysisofasynchronousASIC,PCBorSystemdesign,thatidentifies:LogichazardsClockedtimingpathsTimingerrorsRequiredinputsFunctionaldescriptionofcircuit(netlist)Component-leveltimingdataCircuitoperating(clock)speeds3第3頁Whatisa“ClockedTimingPath”?AtimingpathconsistsofallofthelogicbetweentwoclockedelementsthatoperateoffthesameclocksignalThetimingpathisanalyzedtoensurethatsetupandholdrequirementsaremetattheinputofeachclockedelementTheslack(delaymargin)inthepathcanbeusedtoderiveSIflighttimeconstraints4第4頁ModernSystemDesignModernsystemsaredominatedbyhighspeedbusinterconnectionsCombinationallogichasbeen“absorbed”intootherchipsTiminganalysisfordatabusescanbeperformedusingasimplified“bus-level”timingmodelCPUAGPDIMMPCI5第5頁StandardSynchronousDataTransfer6第6頁FlightTimeAccountsfortheelectricaldelayofinterconnect(PCBetch)betweenthedrivingdeviceandreceiversCanbeestimatedforslowspeedcircuits;mustbesimulated(signalintegrity)forhighspeeddesigns7第7頁IssuesinSynchronousDesignClockJitterincreases/decreasestheindividualclockcycle,decreasingthetimeleftfordatatransfer

ClockSkewchangestheeffectiveclockperioddependingonwhichdevicesaredriving/receivingD0D1D2ClockDriverD0D1D2t=0t=1t=28第8頁Crosstalk-ImpactonBusTimingCrosstalkbetweenadjacentbusbitsaffectsedgespeed(andthereforeflighttime)Denserroutingmakesbetteruseofboardspace,butattheexpenseoflargervariationsinflighttimePre-layoutcrosstalkanalysishelpsthedesignermakethebesttradeoffbetweenroutingdensityandsignalintegrityEvenModeReferenceOddModeD0D1D2D0D1D2D0D1D2D0D1D29第9頁Bus-LevelTimingBudgetForeachindependentDriverReceiverpath:Tflightmax<ClockPeriod-Driver(Tcomax)-Skew-Jitter-Crosstalk-Receiver(Setup)Tflightmin>Receiver(Hold)-Driver(Tcomin)+Skew+CrosstalkDriver(Tcomax)Tflightmax+/-Jitter+/-SkewReceiver(Setup)<ClockPeriodDriver(Tcomin)Tflightmin+/-Skew>Receiver(Hold)+/-Crosstalk+/-Crosstalk10第10頁DeterminingDeviceTimingTimingstakenfrom“AC(dynamic)Specifications”sectionsofdatasheetsManydatasheetsavailableon-lineviaWWWImportantparametersClock

DataValidConditionsunderwhichthisismeasuredSetup/HoldrequirementsPLLJitter(ifspec’d)Example-PentiumPro11第11頁DeterminingFlightTimes:ExampleTflightmax=4.55nsTflightmin=0.05ns12第12頁WhatIsSignalIntegrityAnalysis?AnaloganalysisofdigitalswitchingbehaviorExtractsroutinginformationfromPCBdatabaseUsespecialanalogmodelsfordeviceinputs/outputsIBISmodelingstandard13第13頁TheSignalIntegrityModelSImodelsrepresentonlythebehaviorofthedeviceoutputandinputbuffers

InternalcomponentfunctionsandassociatedtimingarenotmodeledDrivingReceivingt=0Internal

LogicnotmodeledInternal

Logicnotmodeled14第14頁MeasuringInterconnectDelayAccountsforelectricaldelaycausedbyinterconnect(PCBetch)betweenthedrivingdeviceandeachreceiveronthenetUsuallydifferentforeachdriver–receivercombinationCanbedeterminedusingsignalintegrityanalysis15第15頁MinimumandMaximumDelaysThereceiver’sinputthresholdsareusedtodeterminetheearliestandlatesttimesthattheinputchangemaybedetectedThisinformationisthenusedtodetermineminimum&maximumflighttimedataforeachdriver/receivercombinationEarliestSwitchLatestSwitchInputThresholds16第16頁ACloserLookAtTcoDinClockOutput

BufferInternal

LogicRL=50WClocktriggersatt=0VmeasTcoLoadforTcomeasurement(fromdatabook)Tco=timefromclockrisetoVmeasintotestload17第17頁ComponentsofTcoDinClockOutput

BufferInternal

LogicRL=50WClocktriggersatt=0VmeasTcoInternaldelay=fromclock

triggertothetimewhentheoutputbufferistriggeredExternal(buffer)delay=how

longthebuffertakestodrivethe

referenceloadtoVmeas18第18頁TheDouble-CountingProblemWewanttoknowatwhatpointintheclockperiodsignalsarriveandstabilizeatthereceiverinputThisiscomparedtosetup/holdconstraintsThisisfoundbycombiningcomponenttimingdata(TCO)withflighttimedatafromsignalintegrityanalysis19第19頁But,IfWeSimplyAdd…TCO(fromDatabook)

+SimulatedDelay

+TheexternalbufferdelayportionofTcogetsdouble-counted!!

20第20頁Because,WhatWeReallyWantedWas…InternalDelay

+SimulatedDelay

+21第21頁MakingThePiecesFitTogetherTherearetwowaystosolvethisdiscrepancy:AdjustthevalueofTCOusedfortiminganalysisbysubtractingoutthetimeattributedtoTCObufferdelaySubtractthetimeattributedtotheTCObufferdelayfromtheinputreceiverswitchingtimespredictedbysimulationByconvention,thelattermethodisused.22第22頁DeterminingTheBufferDelay...TheoutputbuffermodelusedforsignalintegrityanalysisisconnectedtotheTCO“testload”andsimulatedThedelayismeasuredatthepointwheretheoutputpincrossesVmeasThecorrespondingdelayissavedandusedinflighttimecomputations23第23頁MeasuringFlightTimeFlighttimeisthereforealwaysmeasuredwithrespecttothedelayintothestandardloadThisisaccomplishedbydeterminingtheTCObufferdelay,andsubtractingthatvaluefromsimulationresultsBufferdelayintoStandardLoad

880.55ps,2.5V3.0V=VIH2.0V=VIL2.5V=VmeasMaxFlight

608.71psMinFlight

476.32ps24第24頁ImplicationsTheoutput-to-inputdelay,asapparentfromwaveformdatacannotbedirectlymeasuredtodetermineflighttimeTheloadingconditionusedtocomputebufferdelayandtheconditionsunderwhichTcoismeasuredmustbeidentical25第25頁FundamentalAssumptionsTimingequationsarevalidforbustimingAssumescommonclock,synchronousdesignInter-symbolinterference(ISI)caninvalidateequationsSImodelsprovidegoodpredictionofsystembehaviorLoadingconditionforTcois“representative”ofactualsystemloadingconditionsTheTcoloadisusertocalculatebufferdelaySimulationresultsarecorrectlyadjustedtomeetthedefinitionforflighttime(eitherbythetoolormanually)26第26頁AFewWordsonDeviceModeling…QualityproblemsarenotunusualinSImodels(unfortunately)Checkmodelquality!CheckbufferdelayinformationDifferentmodelssupportdifferentpurposesPre-layoutmodels(min/maxpackageparasiticsonly)Post-layoutmodels(detailedper-pinparasiticdata)DatafromIBISmodelwithper-pinlumpedparasitics27第27頁VerifyingStandardLoadingConditions...Model_typeI/O_open_drainPolarity Non-InvertingEnableActive-LowVinl=0.8Vinh=1.2Vmeas=1.00Cref=0.00pRref=25.00Vref=1.50...IBISprovidesspecifickeywordstodefinetheconditionsunderwhichbufferdelaysshouldbesimulatedandmeasuredThemeasurement/loadingconditionsintheIBISfileshouldbethesameastheconditionsunderwhichTCOisspecifiedinthedevice’sdatasheetIBISModelFileVmeas=1.00Cref=0.00pRref=25.00Vref=1.5028第28頁ClosingTheLoopDifferentwaystointegratetiminganalysisandsignalintegrityresults:Manualapproach:determineallowablemin/maxflighttimesusingcomponenttimingdataandaspreadsheet.Usesignalintegrityanalysistoverifythatthedesignmeetsthecomputedflighttimerequirements.Generalapproach:usestatictiminganalysistoevaluatesystemtiming,andsignalintegrityanalysistocomputeflighttimes.Feedflighttimedatabackintothestatictimingtool.Bus-leveltimingapproach:usestandardtimingequationsandcomponenttimingdatatoperformspreadsheet-basedtiminganalysis.Feedflighttimesfromsignalintegrityanalysisbackintothespreadsheettocomputedesignmargins.29第29頁ManualApproachForcommon-clockbuses,allowablemin/maxflighttimescanbecomputedfrombusspeeds,systembudgetsandcomponenttimingdataTimingequationsareprogrammedintoaspreadsheetandallowableflighttimescomputedWhilenotelegant,thismethodisfast,flexibleandreliablewhenthetimingforasmallnumberofbusesneedstobedetermined30第30頁GeneralApproachTiminganalysis,layoutandSIanalysisarerunasseparateprocessesFlighttimedatafromsignalintegrityanalysisisfedbackintotiminganalysistocompletetheloopandintegratethetwosetsofdataChangingthedesignrequiresre-runningthecompleteloopSchematicCapturePCBLayoutStaticTimingAnalysisSignalIntegrityAnalysisNetlistRoutedDatabaseFlight

TimesConstraints31第31頁Bus-LevelApproachComponenttiming,busspeedsandclockjitter/skewbudgetsarecapturedaspartofthePCBdatabaseSignalintegrityanalysisisrunfromthePCBdatabaseAspreadsheetcontainingbus-leveltimingequationsisusedtocomputethedesignmarginsbasedonsimulationresultsSchematicCapturePCBLayoutTimingSpreadsheetSignalIntegrityAnalysisNetlistFlight

TimesComponentTimingDataComponent

TimingDataRouted

Database32第32頁SPECCTRAQuestTimingModelLoadedfromcomponenttimingdataSpecifiedintimingspreadsheetandsavedindatabaseDefinedaspropertyinAllegrodatabaseComputedusingSIanalysisDriver(Tcomax)Tflightmax+/-Jitter+/-SkewReceiver(Setup)<ClockPeriodDriver(Tcomin)Tflightmin+/-Skew>Receiver(Hold)33第33頁SPECCTRAQuestTimingFlowComponent

timingdataClockNetdeclarations,operatingspeeds,clockjitterClockjitterandskewbudgetsSimulated

flighttimesSP