EDA綜合課程設(shè)計(jì)報(bào)告

PAGE北華航天工業(yè)學(xué)院《EDA技術(shù)綜合設(shè)計(jì)》課程設(shè)計(jì)報(bào)告報(bào)告題目：數(shù)字秒表作者所在系部：電子工程系作者所在專業(yè)：通信工程作者所在班級(jí)：B11232作者姓名：院文樂(lè)(35),張濤(36)指導(dǎo)教師姓名：崔瑞雪完成時(shí)間：2013.12.92013.12.12內(nèi)容摘要秒表共有6個(gè)輸出顯示，分別為百分之一秒、十分之一秒、秒、十秒、分、十分，所以共有6個(gè)計(jì)數(shù)器與之相對(duì)應(yīng)，6個(gè)計(jì)數(shù)器的輸出全都為BCD碼輸出，這樣便于和顯示譯碼器的連接。當(dāng)計(jì)時(shí)達(dá)60分鐘后，蜂鳴器鳴響10聲。除此之外，整個(gè)秒表還需有一個(gè)啟動(dòng)信號(hào)和一個(gè)歸零信號(hào)，以便秒表能隨意停止及啟動(dòng)。秒表的邏輯結(jié)構(gòu)較簡(jiǎn)單，它主要由顯示譯碼器、分頻器、十進(jìn)制計(jì)數(shù)器、六進(jìn)制計(jì)數(shù)器和報(bào)警器組成。四個(gè)10進(jìn)制計(jì)數(shù)器：用來(lái)分別對(duì)百分之一秒、十分之一秒、秒和分進(jìn)行計(jì)數(shù)；兩個(gè)6進(jìn)制計(jì)數(shù)器：用來(lái)分別對(duì)十秒和十分進(jìn)行計(jì)數(shù)；分頻器：用來(lái)產(chǎn)生100HZ計(jì)時(shí)脈沖；顯示譯碼器：完成對(duì)顯示的控制。根據(jù)電路持點(diǎn)，用層次設(shè)計(jì)概念將此設(shè)計(jì)任務(wù)分成若干模塊，規(guī)定每一模塊的功能和各模塊之間的接口。按適配劃分后的管腳定位，同相關(guān)功能塊硬件電路接口連線。用VHDL語(yǔ)言描述所有底層模塊。清零信號(hào)為異步清零。當(dāng)最高位記到6時(shí)停止計(jì)數(shù)顯示譯碼器全部顯示零，并發(fā)出十聲警報(bào)聲。按下復(fù)位按鈕后繼續(xù)計(jì)數(shù)。

目錄系統(tǒng)組成框圖……………………5各模塊原理及其程序……………5六進(jìn)制計(jì)數(shù)器……………………6十進(jìn)制計(jì)數(shù)器…………………6蜂鳴器………7譯碼器…………7控制器…………8分頻器………9元件例化………9系統(tǒng)仿真………10六進(jìn)制計(jì)數(shù)器…………………10十進(jìn)制計(jì)數(shù)器…………………11蜂鳴器………11譯碼器………11控制器………11四、心得體會(huì)……………………11五、參考文獻(xiàn)……………………12 課程設(shè)計(jì)任務(wù)書(shū)課題名稱數(shù)字秒表完成時(shí)間指導(dǎo)教師職稱學(xué)生姓名班級(jí)總體設(shè)計(jì)要求和技術(shù)要點(diǎn)總體設(shè)計(jì)要求：通過(guò)本課程的學(xué)習(xí)使學(xué)生掌握可編程器件、EDA開(kāi)發(fā)系統(tǒng)軟件、硬件描述語(yǔ)言和電子線路設(shè)計(jì)與技能訓(xùn)練等各方面知識(shí)；提高工程實(shí)踐能力；學(xué)會(huì)應(yīng)用EDA技術(shù)解決一些簡(jiǎn)單的電子設(shè)計(jì)問(wèn)題。技術(shù)要點(diǎn)：1．秒表有共有6個(gè)輸出顯示，分別為百分之一秒、十分之一秒、秒、十秒、分、十分，所以共有6個(gè)計(jì)數(shù)器與之相對(duì)應(yīng)，6個(gè)計(jì)數(shù)器的輸出全都為BCD碼輸出，這樣便與同顯示譯碼器的連接。2．開(kāi)關(guān)設(shè)置秒表報(bào)警器，每10秒鐘，蜂鳴器鳴響1聲，發(fā)光二極管閃爍。當(dāng)計(jì)時(shí)達(dá)60分鐘后，蜂鳴器鳴響10聲。工作內(nèi)容及時(shí)間進(jìn)度安排工作內(nèi)容：在軟件上編輯、編譯程序，并仿真到達(dá)實(shí)驗(yàn)要求。進(jìn)度安排;課下編寫(xiě)程序，并要求程序能通過(guò)編譯仿真；第十六周的周三在實(shí)驗(yàn)板上下載調(diào)試程序；周四課設(shè)答辯。課程設(shè)計(jì)成果1．與設(shè)計(jì)內(nèi)容對(duì)應(yīng)的軟件程序2．課程設(shè)計(jì)報(bào)告書(shū)3．成果使用說(shuō)明書(shū)4．設(shè)計(jì)工作量要求設(shè)計(jì)過(guò)程一．系統(tǒng)組成框圖數(shù)字秒表數(shù)字秒表計(jì)時(shí)控制電路控制狀態(tài)機(jī)計(jì)時(shí)電路顯示電路分頻電路計(jì)數(shù)器六進(jìn)制計(jì)數(shù)器掃描電路七段譯碼器十進(jìn)制計(jì)數(shù)器系統(tǒng)組成框圖二．各模塊及的原理及其程序（1）六進(jìn)制計(jì)數(shù)器libraryieee;（1）六進(jìn)制計(jì)數(shù)器useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycount6isport(clk,clr,start:instd_logic;daout:outstd_logic_vector(3downto0);cout:outstd_logic);endcount6;architecturebehaveofcount6issignaltemp:std_logic_vector(3downto0);beginprocess(clk,clr)beginifclr='1'thentemp<="0000";cout<='0';elsifclk'eventandclk='1'thenifstart='1'theniftemp>="0101"thentemp<="0000";cout<='1';elsetemp<=temp+1;cout<='0';endif;endif;endif;endprocess;daout<=temp;endbehave;（2）十進(jìn)制計(jì)數(shù)器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entitycount10isport(clr,start,clk:instd_logic;cout:outstd_logic;daout:bufferstd_logic_vector(3downto0));endcount10;architecturebehaveofcount10isbeginprocess(clr,start,clk)beginifclr='1'thendaout<="0000";elsif(clk'eventandclk='1')thenifstart='1'thenifdaout="1001"thendaout<="0000";cout<='1';elsedaout<=daout+1;cout<='0';endif;endif;endif;endprocess;endbehave;（3）蜂鳴器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityalarmisport(clk,I:instd_logic;q:outstd_logic);endalarm;architecturearofalarmissignaln:integerrange0to20;signalq0:std_logic;beginprocess(clk)beginifclk'eventandclk='1'thenifi='0'thenq0<='0';n<=0;elsifn<=19andi='1'thenq0<=notq0;n<=n+1;elseq0<='0';endif;endif;endprocess;q<=q0;endar;（4）譯碼器libraryieee;useieee.std_logic_1164.all;entitydeledisport(num:instd_logic_vector(3downto0);led:outstd_logic_vector(6downto0));enddeled;architectureaofdeledisbeginprocess(num)begincasenumiswhen"0000"=>led<="0111111";when"0001"=>led<="0000110";when"0010"=>led<="1011011";when"0011"=>led<="1001111";when"0100"=>led<="1100110";when"0101"=>led<="1101101";when"0110"=>led<="1111101";when"0111"=>led<="0100111";when"1000"=>led<="1111111";when"1001"=>led<="1101111";whenothers=>led<="0000000";endcase;endprocess;enda;（5）控制器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityseltimeisport(clr,clk:inbit;dain0,dain1,dain2,dain3,dain4,dain5:instd_logic_vector(3downto0);sel:outstd_logic_vector(2downto0);daout:outstd_logic_vector(3downto0));endseltime;architectureaofseltimeissignaltemp:integerrange0to5;beginprocess(clk)beginif(clr='1')thendaout<="0000";sel<="000";temp<=0;elsif(clk='1'andclk'event)theniftemp=5thentemp<=0;elsetemp<=temp+1;endif;casetempiswhen0=>sel<="000";daout<=dain0;when1=>sel<="001";daout<=dain1;when2=>sel<="010";daout<=dain2;when3=>sel<="011";daout<=dain3;when4=>sel<="100";daout<=dain4;when5=>sel<="101";daout<=dain5;endcase;endif;endprocess;enda;（6）分頻器(10MHz的時(shí)鐘脈沖)libraryieee;useieee.std_logic_1164.all;entitydivisport(clr,clk:instd_logic;q:bufferstd_logic);enddiv;architectureaofdivissignalcount:integerrange0to99999;beginprocess(clr,clk)beginif(clk'eventandclk='1')thenclkclkclrqdivinst4ifclr='1'thencount<=0;elsifcount=99999thencount<=0;q<=notq;elsecount<=count+1;endif;endif;endprocess;end;（7）元原件例化libraryieee;useieee.std_logic_1164.all;entitymb_topisport(stop,start,clk:instd_logic;a,b,c,d,e,f,g,speaker:outstd_logic;sel:outstd_logic_vector(2downto0));endmb_top;architectureaofmb_topiscomponentdivport(clr,clk:instd_logic;q:bufferstd_logic);endcomponent;componentcount10port(clr,start,clk:instd_logic;cout:outstd_logic;daout:bufferstd_logic_vector(3downto0));endcomponent;componentcount6port(clr,start,clk:instd_logic;cout:outstd_logic;daout:bufferstd_logic_vector(3downto0));endcomponent;componentseltimeport(clr,clk:instd_logic;dain1:instd_logic_vector(3downto0);dain2:instd_logic_vector(3downto0);dain3:instd_logic_vector(3downto0);dain4:instd_logic_vector(3downto0);dain5:instd_logic_vector(3downto0);dain6:instd_logic_vector(3downto0);sel:outstd_logic_vector(2downto0);daout:outstd_logic_vector(3downto0));endcomponent;componentdeledport(num:instd_logic_vector(3downto0);led:outstd_logic_vector(6downto0));endcomponent;componentalarmport(clk,i:instd_logic;q:outstd_logic);endcomponent;signaldiv_q,b_cout,s_cout,m_cout,sm_cout,f_cout,sf_cout:std_logic;signalb_daout,s_daout,m_daout,sm_daout,f_daout,sf_daout,seltime_daout:std_logic_vector(3downto0);signalledout:std_logic_vector(6downto0);begina<=ledout(0);b<=ledout(1);c<=ledout(2);d<=ledout(3);e<=ledout(4);f<=ledout(5);g<=ledout(6);u1:divportmap(stop,clk,div_q);u2:count10portmap(stop,start,div_q,b_cout,b_daout);u3:count10portmap(stop,start,b_cout,s_cout,s_daout);u4:count10portmap(stop,start,s_cout,m_cout,m_daout);u5:count6portmap(stop,start,m_cout,sm_cout,sm_daout);u6:count10portmap(stop,start,sm_cout,f_cout,f_daout);u7:count6portmap(stop