BCD七段顯示譯碼器的設(shè)計(jì)報(bào)告

實(shí)驗(yàn)二、BCD七段顯示譯碼器的設(shè)計(jì)實(shí)驗(yàn)?zāi)康膶W(xué)習(xí)利用VHDL語(yǔ)言設(shè)計(jì)BCD七段顯示譯碼器的方法，掌握BCD七段顯示譯碼器的設(shè)計(jì)思路：掌握軟件工具的使用方法。實(shí)驗(yàn)原理bcd七段顯示譯碼器真值表SEQbcd七段顯示譯碼器真值表\*ARABIC1輸入輸出數(shù)字A3A2A1A0YaYbYcYdYeYfYg字形00000111111001000101100001200101101101230011111100134010001100114501011011011560110101111167011111100107810001111111891001111101191010101110111A1110110011111B1211001001110C1311010111101D1411101001111E1511111000111F實(shí)驗(yàn)內(nèi)容1.用VHDL語(yǔ)言設(shè)計(jì)BCD七段顯示譯碼器，進(jìn)行編譯、波形仿真及器件編程?！泊a一詳見(jiàn)附錄〕產(chǎn)生仿真波形如下：BCD七段顯示譯碼器仿真SEQBCD七段顯示譯碼器仿真\*ARABIC1分析：?jiǎn)枺航o定的代碼驅(qū)動(dòng)的是共陰極還是共陽(yáng)極的七段數(shù)碼管顯示器？由BCD七段顯示譯碼器真值表可知是共陰極七段數(shù)碼管顯示器。2.用VHDL語(yǔ)言設(shè)計(jì)3-8譯碼器，進(jìn)行編譯、波形仿真及器件編程?！泊a二詳見(jiàn)附錄〕產(chǎn)生仿真波形如下：3-8譯碼器仿真SEQ3-8譯碼器仿真\*ARABIC1四、實(shí)驗(yàn)心得在實(shí)驗(yàn)中，通過(guò)BCD七段顯示譯碼器真值表真值表得到BCD七段顯示譯碼器case代碼。同理通過(guò)8-3譯碼器真值表修改BCD七段顯示譯碼器case代碼得到8-3譯碼器case代碼。附錄代碼一〔BCD七段顯示譯碼器代碼〕：libraryieee;useieee.std_logic_1164.all;entitybcdymisport(a:instd_logic_vector(3downto0);y:outstd_logic_vector(6downto0));endbcdym;architecturezhangofbcdymisbeginprocess(a)begincaseaiswhen"0000"=>y<="0111111";when"0001"=>y<="0000110";when"0010"=>y<="1011011";when"0011"=>y<="1001111";when"0100"=>y<="1100110";when"0101"=>y<="1101101";when"0110"=>y<="1111101";when"0111"=>y<="0100111";when"1000"=>y<="1111111";when"1001"=>y<="1101111";when"1010"=>y<="1110111";when"1011"=>y<="1111100";when"1100"=>y<="0111001";when"1101"=>y<="1011110";when"1110"=>y<="1111001";whenothers=>y<="1110001";endcase;endprocess;endzhang;代碼二〔8-3譯碼器代碼〕：libraryieee;useieee.std_logic_1164.all;entitybm3_8isport(a:instd_logic_vector(0to2);b:outstd_logic_vector(0to7));endbm3_8;architecturezhangofbm3_8isbeginprocess(a)begincaseaiswhen"000"=>b<="00000001";when"001"=>b<="00000010";when"010"=>b<="00000100";when"011"=>b<="00001000";when"100"=>b<="00010000";when"101"=>b<="00100000";