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1、AN1709 APPLICATION NOTEEMC DESIGN GUIDE FOR ST MICROCONTROLLERSby Cyril Troise - Microcontroller Division ApplicationsINTRODUCTIONThe continuing demand for more performance, complexity and cost reduction require the sem- iconductor industry to develop Microcontrollers with both high density design t

2、echnology and higher clock frequencies. This has intrinsically increased the noise emission and noise sensi- tivity. Application developers therefore, must now apply EMC “hardening” techniques in the design of firmware, PCB layout and at system level. This note aims to explain ST Microcon- troller E

3、MC features and compliance standards to help application designers reach the op-timum level of EMC performance.1.0AN1709/10031/38Table of ContentsINTRODUCTION11 EMC DEFINITIONS41.1EMC41.2EMS41.3EMI42 EMC CHARACTERIZATION OF ST MICROCONTROLLERS52.1 ELECTROMAGNETIC SUSCEPTIBILITY (EMS)52.1.1Functional

4、 EMS test52.1.1.12.1.1.22.1.1.3Functional ElectroStatic Discharge Test (F_ESD Test)5Fast Transient Burst (FTB)7ST Severity Level & Behavior Class82.1.2Latch-Up (LU)102.1.2.1 Static Latch-Up (LU) test:102.1.2.2 Dynamic Latch-Up (DLU) test10Absolute Electrical Sensitivity112.1.3.1 Human Body Model Tes

5、t Sequence122.1.3.2 Machine Model Test Sequence122.1.32.2 ELECTROMAGNETIC INTERFERENCE (EMI)132.2.1 EMI radiated test132.2.2 EMI level classification163 ST MCU DESIGN STRATEGY & EMC SPECIFIC FEATURE173.1SUSCEPTIBILITY173.1.13.1.23.1.3Low Voltage Detector (LVD)17Auxiliary Voltage Detector (AVD)19I/O

6、Features & properties213.1.3.13.1.3.23.1.3.33.1.3.4Electrostatic Discharge and Latch-up21Protective Interface22Internal Circuitry: Digital I/O pin23Internal Circuitry: Analog Input pin253.1.4Multiple VDD & VSS.263.2EMISSION273.2.1 Internal PLL273.2.2 Global low power approach273.2.2.1 Low powered os

7、cillator273.2.2.2 Internal Voltage Regulators (for MCUs with low power core)292/38Table of Contents3.2.3 Output I/O Current limitation & edge timing control294 EMC GUIDELINES FOR MCU BASED APPLICATIONS304.1HARDWARE304.2HANDLING PRECAUTIONS FOR ESD PROTECTION344.3FIRMWARE364.4WEB LINKS TO EMC RELATED

8、 ORGANISATIONS365 CONCLUSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373/38EMC DESIGN GUIDE FOR ST MICROCONTROLLERS1 EMC DEFINITIONS1.1 EMCElectroMagnetic Compatibility (EMC) is the capability of a system to work properly, undis- tur

9、bed by the electromagnetic phenomena present in its normal environment, and not to createelectrical disturbances that would interfere with other equipment.1.2 EMSThe ElectroMagnetic Susceptibility (EMS) level of a device is the resistance to electrical dis- turbances and conducted electrical noise.

10、ElectroStatic Discharge (ESD) and Fast Transient Burst (FTB) tests determine the reliability level of a device operating in an undesirable electro-magnetic environment.1.3 EMIThe ElectroMagnetic Interference (EMI) is the level of conducted or radiated electrical noise sourced by the equipment. Condu

11、cted emission propagates along a cable or any interconnec-tion line. Radiated emission propagates through free space.4/38EMC DESIGN GUIDE FOR ST MICROCONTROLLERS2 EMC CHARACTERIZATION OF ST MICROCONTROLLERS2.1 ELECTROMAGNETIC SUSCEPTIBILITY (EMS)Two different type of tests are performed: Tests with

12、device power-supplied (Functional EMS tests & Latch-up): The device behaviour is monitored during the stress. One test with device not powered supplied (Absolute Electrical Sensitivity): The device functionality and integrity is checked on tester after stress.2.1.1 Functional EMS testFunctional Test

13、s are performed to measure the robustness of ST Microcontrollers running in an application. Based on a simple program (toggling 2 LEDs through I/O ports), the product is stressed by 2 different EMC events until a run-away condition (failure) occurs.2.1.1.1 Functional ElectroStatic Discharge Test (F_

14、ESD Test)This test is performed on any new microcontroller devices.Each pin is tested individually with a single positive or negative electrical discharge.This allows failures investigations inside the chip and further application recommendations to protect the concerned Microcontroller sensi- tive

15、pins against ESD.High static voltage has both natural and man made origins. Some specific equipment can re- produce this phenomenon in order to test the device under real conditions. Equipment, test sequence and standards are described here below.ST Microcontroller F_ESD qualification test uses stan

16、dards given in Table 1 as reference.Table 1. ESD standardsAEC-Q100-REUE is the Automotive controlling document.F_ESD tests uses a signal source and a power amplifier to generate a high level field into The Microcontroller. The insulator is using a conical tip. This tip is placed on the Device or Equ

17、ip-ment Under Test (DUT or EUT) and an electrostatic discharge is applied (see Figure 1.).5/38EUROPEAN NORMINTERNATIONAL NORMDESCRIPTIONEN 61000-4-2IEC 1000-4-2Conducted ESD testEMC DESIGN GUIDE FOR ST MICROCONTROLLERSFigure 1. ESD test equipmentThe equipment used to perform F_ESD test is a Generato

18、r NSG 435 (SCHAFFNER) com- pliant with the norm IEC 1000-4-2. The discharges are directly applied on each pin of the MCU.Figure 2. Typical ESD Current Waveform in Contact-mode discharge6/38(EN 61000-4-2)Current100%90% I(30ns)I(60ns)10%30ns60nstimetr=0.7 to 1.0 nsground planeinsulationESD generatorEU

19、TmainsconnectionsEMC DESIGN GUIDE FOR ST MICROCONTROLLERSFigure 3. Simplified diagram of the ESD generator(Rch = 50MW; Rd = 330W)2.1.1.2 Fast Transient Burst (FTB)More complex than functional ESD, this test which submits the device to a large quantity of emitted disturbances in a short time, is usef

20、ul for detecting infrequent and unrecoverable (Class B or C) Microcontroller states. FTB disturbances (see Figure 4.) are applied to the Mi- crocontroller power lines through a capacitive coupling network.ST Microcontroller FTB test correlates with the standards given in Table 2Table 2. FTB standard

21、sFigure 4. FTB WaveformDiagramThe spike frequency is 5 kHz. The generator produces bursts of spikes that last 15 ms every 300 ms (75 spikes).The fast transients are coupled to the device DUT with capacitors CC (See Figure 5.).7/38BurstVoltageVoltageVoltage BurstPulse0.9Vpk0.1VpkTimeTime5nsTimeBurst

22、LengthBurst Period50ns15ms300msRepetition Frequency: 5kHz; Bursts willRising and Duration time (30%) are re- be repeated for at least 1 minute.ferred to a 50W loadVpk0.5VpkEUROPEAN NORMINTERNATIONAL NORMDESCRIPTIONEN61000-4-4IEC 1000-4-4Fast Transient BurstRchRdDischarge tip ESDHV relaygeneratorCs =

23、 150 pFDischarge return connectionEMC DESIGN GUIDE FOR ST MICROCONTROLLERSFigure 5. Coupling NetworkMeasurements are performed on a ground plane. The generator is connected to ground plane by a short wire. The supply wires are 10 cm from the ground plane. The DUT is on the insu- lator 10 cm from the

24、 ground plane. The FTB voltage level is increased until the device failure.Severity Levels and Class help application designers to determine which ST microcontrollers are suitable for their target application, based on the susceptibility level (Severity level) and type of behavior (Class) indicated

25、in the datasheet.2.1.1.3 ST Severity Level & Behavior ClassThe 1000-4-2 and 1000-4-4 standards do not refer specifically to semiconductor components such as microcontrollers. Usually electromagnetic stress is applied on other parts of the system such as connectors, mains, supplies. The energy level

26、of the F_ESD and FTB test decreases before reaching the microcontroller, governed by the laws of physics. A large amount of statistical data collected by ST on the behaviour of MCUs in various application en- vironments has been used to develop a correlation chart between ST F_ESD or FTB test voltag

27、e and 1000-4-2/1000-4-4 severity levels (See Table 3).Table 3. ST ESD Severity levelsIn addition to this severity level, MCU behaviour under ESD stress can be grouped into dif-ferent Behaviour Classes (See Table 4) according to EN 50082-2 norm:8/38Severity LevelESD (1000-4-2)Equipment standard (kV)F

28、TB (1000-4-4)Equipment standard (kV)ST Testing VoltageST internal EMC test (kV)120.50-0.52410.5-13621-1.54841.5NSG 2025Cc +VD +VDLDDPOWERTO THE DEVICESUPPLY CcUNDER TESTGNDGNDEMC DESIGN GUIDE FOR ST MICROCONTROLLERSTable 4. ST Behavior ClassesAny ST Microcontroller under the “acceptance limits” is r

29、ejected as a fail. The “target level” is the level used by ST to define good EMS performance.Class B could be caused by: a parasitic reset correctly managed by the firmware (preferable case). deprogramming of a peripheral register or memory recovered by the application. a blocked status, recovered b

30、y a Watchdog or other firmware implementation.Class C could be caused by: deprogramming of a peripheral register or memory not recovered by the application. a blocked application status requiring an external user action.Table 5 shows ST target and acceptance limits.Table 5. F_ESD / FTB target level

31、& acceptance limitBetween “Acceptance limit” and “Target Level”, the device is relatively susceptible to noise.Special care during system design should be taken to avoid susceptibility issues.Table 6 shows how F_ESD / FTB test results are presented in STTable 6. Example of F_ESD / FTB test resultsda

32、tasheets.9/38SymbolRatingsConditionsSeverity/CriteriaVF_ESDVoltage limits to be applied on any I/O pin to induce a functional disturbanceTA=+25C2/A, 3/BVFTBFast transient voltage burst limits to be applied through 100pF on VSS and VDD pins to induce a functional distur- banceTA=+25C3/BAcceptance lim

33、itTarget LevelF_ESD0.5kV1kVFTB0.5kV1.5kVClass AClass BClass CClass DNo failure detectedFailure detected but self recovery after distur- banceNeeds an external user action to recover normal functionalityNormal functionality cannot be recoveredEMC DESIGN GUIDE FOR ST MICROCONTROLLERS2.1.2 Latch-Up (LU

34、)2.1.2.1 Static Latch-Up (LU) test:The Latch-up is a phenomenon which is defined by a high current consumption resulting from an overstress that triggers a parasitic thyristor structure and need a disconnection of the power supply to recover the initial state.NOTES1 The overstress can be a voltage o

35、r current surge, an excessive rate of change of current or voltage, or any other abnormal condition that causes the parasitic thyristor structure to be- come self-sustaining.2 Latch-up will not damage the device if the current through the low-impedance path is suffi- ciently limited in magnitude or

36、duration.This test conforms to the EIA/JESD 78 IC latch-up standard.True LU is self-sustaining and once triggered, the high current condition will remain until the power supply voltage is removed from the device. A temporary LU condition is considered to have been induced if the high current conditi

37、on stops when only the trigger voltage is re- moved.Two complementary static tests are required on 10 parts to assess the latch-up performance: Power supply overvoltage (applied to each power supply pin) simulates a user induced situation where a transient over-voltage is applied on the power supply

38、. Current injection (applied to each input, output and configurable I/O pin) simulates an application induced situation where the applied voltage to a pin is greater than the maximumrated conditions, such as severe overshoot above VDD or undershoot below ground on an input due to ringing.Table 7 sho

39、ws how LU test result is presented in ST datasheets.Table 7. Example of the LU test result on ST72F5211.Class description: “A” class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JE

40、DEC standard. “B” Class strictly covers all the JEDEC criteria (international standard).2.1.2.2 Dynamic Latch-Up (DLU) test:The product is evaluated for its LU susceptibility to ESD discharges when the microcontroller is “running.”10/38SymbolParameterConditionsClass1)LUStatic latch-up classTA=+25CTA

41、=+85C, TA=+125C (de-pending on the temperature range of the device)AEMC DESIGN GUIDE FOR ST MICROCONTROLLERSIncreasing electrostatic discharges are supplied to every pin of the component until a Latch-up occurs. Result is the maximum tolerated voltage without Latch-up.DLU Test methodology and charac

42、terization: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the microcontroller is running to as- sess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to

43、the pins of the microcontroller and the com- ponent is put in reset mode.Table 8 shows how the DLU test result is presented in ST datasheets.Table 8. Example of DLU test Result on ST72F5211.Class description: “A” class is an STMicroelectronics internal specification. All its limits are higher than t

44、he JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. “B” Class strictly covers all the JEDEC criteria (international standard).LU/DLU test equipment is same as the one used for the functional EMS (see Figure 1.).2.1.3 Absolute Electrical SensitivityThis

45、 test is performed to assess the components immunity against destruction caused by ESD. Any devices that fails this electrical test program is classified as a failure.Using automatic ESD tester, Electro-Static Discharges (a positive then a negative pulse sep- arated by 1 second) are applied to the p

46、ins of each sample according to each pin combination. The sample size depends of the number of supply pins of the device (3 parts*(n+1): n= supply pins). Two models are usually simulated: Human Body Model (HBM) and Machine Model (MM). All parts are re-tested on the production tester to verify the st

47、atic and dynamic parame- ters still comply with the device datasheet (See Figure 6.).This test conforms to the JESD22-A114A/A115A standard. See Figure 6. and the following test sequences.11/38SymbolParameterConditionsClass1)DLUDynamic latch-up classVDD =5VfOSC=4MHz, TA=+25CAEMC DESIGN GUIDE FOR ST M

48、ICROCONTROLLERSFigure 6. Absolute Electrical Sensitivity test models2.1.3.1 Human Body Model Test SequenceThe HBM ESD pulse simulates the direct transfer of electrostatic charge, from the Human Body, to a test device. A 100pF capacitor is discharged through a switching component and a1.5 Kohm series

49、 resistor. This is currently the most requested industry model, for classifying device sensitivity to ESD. CL is loaded through S1 by the HV pulse generator. S1 switches position from generator to R. A discharge from CL through R (body resistance) to the C occurs. S2 must be closed 10 to 100ms after

50、 the pulse delivery period to ensure the C is not left in charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse.2.1.3.2 Machine Model Test SequenceThe MM ESD pulse emulates the rapid direct transfer of electrostatic charge, from a charged conductive object, such as a

51、metallic tool or fixture, to a test device. This model consists of a discharged 200pF capacitor, with no series resistor. The demand for MM ESD testing has in- creased, with the replacement of individual packaging by automated systems. CL is loaded through S1 by the HV pulse generator. S1 switches p

52、osition from generator to the C. A discharge from CL to the C occurs. S2 must be closed 10 to 100ms after the pulse delivery period to ensure the C is not left in charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse.R (machine resistance), in series with S2, ensures

53、a slow discharge of the C.Table 9 shows how HBM/MM ESD test results are presented in ST datasheets.12/38R=10k10MWS1R=1500WS1HIGH VOLTAGEHIGH VOLTAGEPULSECL=100pFS2PULSE GENERATORGENERATORCL=200pFS2HUMAN BODY MODELMACHINE MODELEMC DESIGN GUIDE FOR ST MICROCONTROLLERSTable 9. Example of HBM/MM ESD tes

54、t results on ST72F521Notes:1. Data based on characterization results, not tested in production.2.2 ELECTROMAGNETIC INTERFERENCE (EMI)2.2.1 EMI radiated testThis test correlates with the SAE J1752/3 standard.This test gives a good evaluation of the contribution of the microcontroller to radiated noise in an application environment. It takes into account the MCU chip and also the package which has a major influence on the noise radiated by the device.Below is the package EMI contribution from the highest to the lowest: SDIP/DI