基于單片機的智能晾衣架控制系統(tǒng)的設計與實現(xiàn)外文文獻原稿和譯文.docx

燕京理工學院畢業(yè)設計（論文）外文文獻原稿和譯文外文文獻原稿和譯文原稿The Description of AT89S511 General DescriptionThe AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.2 PortsPort 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port PinAlternate FunctionsP1.5MOSI (used for In-System Programming)P1.6MOSO (used for In-System Programming)P1.7 SCK(used for In-System Programming)Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table.Port PinAlternate FunctionsP3.0RXD(serial input port)P3.1TXD(serial output port)P3.2INT0(external interrupt 0)P3.3INT1(external interrupt 1)P3.4T0(timer 0 external input)P3.5T1(timer 1 external input)P3.6WR(external data memory write strobe)P3.7RD(external data memory read strobe)3 Special Function RegistersA map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 3-1. Table 3-1. AT89S51 SFR Map and Reset Values0F8H 0FFH 0F0H B 00000000 0F7H 0E8H 0EFH 0E0H ACC 00000000 0E7H 0D8H 0DFH 0D0H PSW 00000000 0D7H 0C8H 0CFH 0C0H 0C7H 0B8H IP XX000000 0BFH 0B0H P3 11111111 0B7H 0A8H IE 0X000000 0AFH 0A0H P2 11111111 AUXR1 XXXXXXX0 WDTRST XXXXXXXX 0A7H 98H SCON 00000000 SBUF XXXXXXXX 9FH 90H P1 11111111 97H 88H TCON 00000000 TMOD 00000000 TL0 00000000 TL1 00000000 TH0 00000000 TH1 00000000 AUXR XXX00XX 8FH 80H P0 11111111 SP 00000111 DP0L 00000000 DP0H 00000000 DP1L 00000000 DP1H 00000000 PCON 0XXX0000 87H Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register.Table 3-2. AUXR:Auxiliary RegisterAUXR Address=8EH Reset Value=XXX00XX0b Not Bit Addressable WDIDLE DISRTO DISALEBit 7 6 5 4 3 2 1 0 Reserved for future expansionDISALE Disable/Enable ALE DISALE Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency 1 ALE is active only during a MOVX or MOVC instruction DISRTO Disable/Enable Reset-out DISRTO 0 Reset pin is driven High after WDT times out 1 Reset pin is input only WDIDLE Disable/Enable WDT in IDLE modeWDIDLE0 WDT continues to count in IDLE mode 1 WDT halts counting in IDLE mode Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.4 Memory OrganizationMCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.4.1 Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.4.2 Data MemoryThe AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.5 Watchdog Timer (One-time Enabled with Reset-out) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.5.1 Using the WDTTo enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.5.2 WDT DURING Power-down and IdleIn Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt, which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode.With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.6.InterruptsThe AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in Figure 6-1. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.Note that Table 6-1 shows that bit positions IE.6 and IE.5 are unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. Figure 6-1 Interrupt Sources7 Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 7-1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 7-2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Figure 7-1 Oscillator ConnectionsNote: for Crystals for Ceramic ResonatorsFigure 7-2 External Clock Drive Configuration8 Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special function registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.9 Power-down Mode In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Table 9-1 Status of External Pins During Idle and Power-down ModesModeProgram MemoryALEPSENPORT0PORT1PORT2PORT3IdleInternal 1 1DataDataDataDataIdleExternal 1 1FloatDataAddressDataPower-downInternal 0 0DataDataDataDataPower-downExternal 0 0FloatDataDataData 10譯文AT89S51概述1 一般概述 該AT89S51是一個低功耗，高性能CMOS 8位微控制器,可在4K字節(jié)的系統(tǒng)內編程的閃存存儲器。該設備是采用Atmel的高密度、非易失性存儲器技術和符合工業(yè)標準的80C51指令集和引腳。芯片上的Flash程序存儲器在系統(tǒng)中可重新編程或常規(guī)非易失性內存編程 。通過結合通用8位中央處理器的系統(tǒng)內可編程閃存的單芯片， AT89S51是一個功能強大的微控制器提供了高度靈活的和具有成本效益的解決辦法，可在許多嵌入式控制中應用。 在AT89S51提供以下標準功能： 4K字節(jié)的Flash閃存 ， 128字節(jié)的RAM ， 32個 I / O線，看門狗定時器，兩個數(shù)據(jù)指針，兩個16位定時器/計數(shù)器， 5向量兩級中斷結構，全雙工串行端口，片上振蕩器和時鐘電路。此外， AT89S51設計了可降至零頻率的靜態(tài)邏輯操作和支持兩種軟件可選的節(jié)電工作模式。在空閑模式下停止CPU的工作，但允許RAM 、定時器/計數(shù)器、串行接口和中斷系統(tǒng)繼續(xù)運行。掉電模式保存RAM中的內容，停止振蕩器工作并禁止其它所有部件工作，直到下一個外部中斷或硬件復位。 2 端口P0端口是一個8位漏極開路雙向I / O端口。作為一個輸出端口，每個引腳可驅動8個TTL輸入。對端口寫“1”可作為高阻抗輸入端用。在訪問外部程序和數(shù)據(jù)存儲器時，P0端口也可以配置為復低階地址/數(shù)據(jù)總線。在訪問期間激活內部上拉電阻。在Flash編程時，PO端口接收指令字節(jié)，而在程序校驗時，輸出指令字節(jié)，同時要求外接上拉電阻。 P1端口是一個帶內部上拉電阻的8位雙向I /O端口。P1端口的輸出緩沖級可以驅動四個TTL輸入。對端口寫“1”，通過內部的上拉電阻把端口拉到高電平，此時可作為輸入口。作為輸入口時，因為內部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（IIL），F(xiàn)lash編程和程序校驗期間，P1接收低8位地址。端口引腳 第二功能P1.5MOSI(用于ISP編程)P1.6MISO（用于ISP編程）P1.7SCK(用于ISP編程) P2端口是一個帶有內部上拉電阻的8位雙向I/O端口。P2端口的輸出緩沖級可驅動（吸收或輸出電流）4個TTL輸入。對端口寫“1”，通過內部的上拉電阻把端口拉到高電平，此時可作輸入口。當作輸入口使用時，因為內部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流（IIL）。在訪問外部程序存儲器或16位地址的外部數(shù)據(jù)存儲器（例如執(zhí)行 MOVX DPTR指令 ）時，P2端口送出高8位地址數(shù)據(jù)。 在訪問8位地址的外部數(shù)據(jù)存儲器（例如執(zhí)行MOVXRi指令）時，P2端口上的內容（即特殊功能寄存器（SFR)區(qū)中P2寄存器的內容），在整個訪問期間不變。Flash編程或校驗時，P2也可接收高位地址和其它控制信號。P3端口是一組帶有內部上拉電阻的8位雙向I/O端口。P3端口輸出緩沖級可驅動（吸收或輸出電流）4個TTL邏輯門電路。對P3端口寫入“1”時，他們被內部上拉電阻拉高并作為輸入端口。當作輸入端時，被外部拉低的P2端口將用上拉電阻輸出電流（IIL）端口還接收一些用于Flash閃存編程和程序校驗的控制信號。P3端口可以采用AT89S51的各種特殊功能，如下表所示。端口引腳 第二功能P3.0RXD(串行輸入端口)P3.1 TXD(串行輸出端口)P3.2 INT0(外部中斷0)P3.3 INT1（外部中斷1）P3.4 T0(定時/計數(shù)器0外部輸入）P3.5 T1（定時/計數(shù)器1外部輸入）P3.6 WR（外部數(shù)據(jù)存儲器寫選通）P3.7 RD（外部數(shù)據(jù)存儲器讀選通）3 特殊功能寄存器 特殊功能寄存器（SFR）的片內空間分布如表3-1所示。表3-1 AT89S51特殊功能寄存器分布圖及復位值0F8H 0FFH 0F0H B 00000000 0F7H 0E8H 0EFH 0E0H ACC 00000000 0E7H 0D8H 0DFH 0D0H PSW 00000000 0D7H 0C8H 0CFH 0C0H 0C7H 0B8H IP XX000000 0BFH 0B0H P3 11111111 0B7H 0A8H IE 0X000000 0AFH 0A0H P2 11111111 AUXR1 XXXXXXX0 WDTRST XXXXXXXX 0A7H 98H SCON 00000000 SBUF XXXXXXXX 9FH 90H P1 11111111 97H 88H TCON 00000000 TMOD 00000000 TL0 00000000 TL1 00000000 TH0 00000000 TH1 00000000 AUXR XXX00XX 8FH 80H P0 11111111 SP 00000111 DP0L 00000000 DP0H 00000000 DP1L 00000000 DP1H 00000000 PCON 0XXX0000 87H 值得注意的是，這些地址并沒有全部占用，沒有占用的地址也不可使用，讀這些地址將得到一個隨意的數(shù)值。而寫這些地址單元不能得到預期的結果。 不要用軟件訪問這些未定義的單元，這些單元是留作以后產(chǎn)品擴展用途的，復位后這些新的位將為0。 中斷寄存器：各個中斷控制位于IE寄存器，5個中斷源的中斷優(yōu)先級控制位于IP寄存器。表3-2 AUXR輔助寄存器AUXR 地址=8EH 復位狀態(tài)=XXX00XX0B 不可尋址位 WDIDLE DISRTO DISABLEBit 7 6 5 4 3 2 1 0 為將來擴展用途保留位DISALE ALE禁止/使能 DISALE 操作模式 0 ALE 輸出1/6振蕩時鐘頻率脈沖 1 ALE 僅在執(zhí)行MOVX或MOVC指令期間輸出脈沖DISRTO 禁止/使能復位輸出 DISRTO 0 復位引腳在WDT溢出時變高 1 復位引腳僅為輸入W