Testing in the Fouth Dimension ECE測(cè)試在第四維度的ECE

1、332:578 deep submicronvlsi designlecture 3deep sub-micron mos transistor theorymichael l. bushnell - caip center and winlabece dept., rutgers u., piscataway, njmaterial from: low-power cmos vlsi circuit designby kaushik roy and sharat c. prasadoutlinedeep sub-micron threshold equationsmotivation for

2、 transistor reviewreformulate mosfet models and equations to: obtain better vt computation obtain critical subthreshold current obtain critical subthreshold swing calculate drain induced barrier lowering (dibl)allows correct estimation and understanding of low-power currentsdefinitionsideal mis diod

3、etype semiconductorat , = energy difference between metal & semiconductor = semiconductor flat-band condition usually have to apply (flat-band voltage) to cause this to happeneg2qdefinitionsaccumulationenergy bands when a negative voltage is applied:weak inversionenergy bands when small positive

4、 bias voltage is applied:strong inversion at surface now below by or = bulk potential difference between and = voltage necessary to cause strong inversionsurface space charge and vtcharge sheet modelpoisson equation:(disp. vector) neglect fringing fields at edge of transistor, sonormal to sio2 insul

5、atoradppsnnnpqx22derivation of bulk charge ktxqipktxqipppenxnenxp/ dnnenepqdxdxddxddxdxddxdadktxqpktxqpsxx/0/0022222 11202eeeqnxedxdeebsazyproblemnext slides introduce the conventional derivation and modelproblem: simply does not work any more for l 0.35 mm due to:conventional derivationfrom gausss

6、law, total charge in semiconductor is:depletion region depth regard depletion layer as totally devoid of mobile charges carrier concentrations abruptly change to their intrinsic values at distance beneath surface total trapped charge at semiconductor-insulator boundaryflat-band voltage and depletion

7、 layer depthpoisson equation (used to compute depletion layer depth):depletion layer depth wm at strong inversioninversion layer charge inversion layer charge depletion layer charge = surface chargeinversion layer chargesasadsassssassssnqwqnqenqqeeenqeqbssbs2211222bsbsbsbsenqqeeenqqqqsasisssssasdsi2

8、22222212inversion layer thickness tilong-channel mosfetbody effectsurface potential was , becomes relative to source now becomes (relative to source):bvbsbasifbtbsbvbsbasifbbsbbsbevnqdvvvevnqdv2122212222subthreshold current new problemweak inversion variation of minority carrier concentration along

9、channelsubthreshold current (contd)consider grounded fet source, , weak inversion drop almost entirely across reverse-biased substrate-drain - junctionsmall variation of along semiconductor surface component is smalldue to few mobile carriers and small , drift component of subthreshold negligible su

10、bthreshold current (contd)long channel allows the gradual channel approximation to be used depends exponentially on , can be largediffusion current proportional to carrier concentration gradient varies along (distance along channel)terminology channel cross-sectional area electron diffusion coeffici

11、ent channel width inversion layer thickness (per-unit inversion layer area charge)equilibrium electron concentration:charge in inversion layer (weak inversion):derivation (continued)source:drain:observationdifferent situation from mis diode potential gradient along axis, must consider effect of subt

12、hreshold currentfor long-channel mosfet, subthreshold drain-source current remains independent of drain-source voltage varies exponentially with applied gate voltage, so the drain-source current also doesindependence of from ceases when is as large as 2 mm when is large enough to merge source and dr

13、ain depletion regions (punchthrough)must prevent punchthrough, as it makes independent of gate control voltagemust keep punchthrough current smaller than using implantssubthreshold swingsubthreshold swing is inverse of slope of log vs. gate depletion layer capacitance insulator layer capacitance per

14、mittivity of semiconductor permittivity of insulator insulator thickness depletion layer thickness shows how effectively we can stop device drain current flow when goes below (units of milliv/decade)wdccdvidsisoxdgsdst13 . 213 . 2lnlog1subthreshold swing (contd)subthreshold swing (mv/decade) limits

15、how small a power supply we can usefor (100 in practice) due to non-zero oxide thickness and other factorssubmicron mosfetnumber of circuits on chip and their speed grow exponentiallymake faster devices increase (now drain current in saturation) to charge/discharge parasitic s fasterwas predicted th

16、at:, would be independent of instead, decreases with , varies with, decreases as increases instead, increases less rapidly with than with longer channelsneed to understand these effects with small dimension mosfets need to use curve-fitting to model spice parameters submicron effects on vtshort-chan

17、nel-length effect: decreases with decreasing and increasing modeling problemsto understand this, must numerically solve 2-dimensional poisson equationcharge-sharing model: considers channel charge to be shared among source, gate, and drain, didnt work (dibl) decreases due to depletion region charges

18、 in potential energy barrier between source and semiconductor surface.reduces 2-dimensional poisson equation to 1-d by approximating as a constant. works for and as large as 3 vliu model for diblpredicts short-channel threshold voltage shift for deep submicron devicesquasi-2d solution of 2d poisson

19、equation has a horizontal component (drain field) and vertical component (due to gate charge) maximal at source and decreases with to a minimum value at drain value at insulator-semiconductor surface is and goes to 0 at bottom edge of depletion regiondibl modelreplace at each point with its average

20、of values at and use depletion approximation, so depletion region charge is simply the ionic charge ()dyvvyeyeyewyewyweyexesfbtoxoxsoxxxxxx)()()(),0(),0(),(),0(dibl (contd)dibl (contd) is empirical fudge factor and at onset of strong inversioneffective gate voltage is built-in potential at drain-sub

21、strate and substrate-source junctions characteristic length:find by subtracting long-channel value at from minimum of using plotting and curve fittingnote that surface potential is never constant for imsdwlsurface potential along channelfinding subtract minimum value of from rhs of eq. (2.39) to get

22、 if ,simplification:problem: makes it hard to find (the characteristic length)relating to can be related to minimum channel length needed in a mosfet to make it have long-channel characteristicsif , thenleads to :relating to note thatis the junction depthsignificant changes in need:then, for fet wit

23、h poly gate:for fet with poly gate:old equation becomes independent of when 0.7mm:dibl concludednarrow-gate-width effectshave less effect on than short-channel effectsview channel as rectangle in horizontal cross sectionfirst two effects caused by mosfets with raised field-oxide isolation or semi-re

24、cessed (locos)1st effect:narrow-gate-width effects2nd effect: higher channel doping along edges along width dimension (due to channel stop dopants (n) or oxidation of piled-up phosphorous (p) under gate) need a higher to invert channeloverlapping depletion regions (or punchthrough)as decreases, sepa

25、ration between source and drain depletion regions decreasesincreased reverse bias pushes boundaries further from junction and closer to each otherdeep submicron mosfet has a adjust implant only at the surface. causes greater expansion in depletion regions below the surface, so punchthrough first hap

26、pens below the surfacepunchthroughany drain voltage increase after punchthrough happens lowers potential energy barrier for majority carriers in the sourcemore of these enter the substrate, but some collected by drainincreases subthreshold current slope of curve flatter if subsurface punchthrough occurreduse (punchthrough voltage) defined as value of where reaches some specific value with punchthrough (concluded)is approximate value wheres ( bulk dopingvery bad for low-power