《功率因數(shù)校正開(kāi)關(guān)電源的研究與設(shè)計(jì)》外文翻譯

1、功率因數(shù)校正開(kāi)關(guān)電源的研究與設(shè)計(jì)外文翻譯Switching Power Supply Design(開(kāi)關(guān)電源設(shè)計(jì))CHAPTER 3Half- and Full-BridgeConverter Topologies3.1 IntroductionHalf-bridge and full-bridge topologies stress their transistors to a voltage equal to the DC input voltage not to twice this value, as do the push-pull, single-ended, and interl

2、eaved forward converter to pologies. Thus the bridge topologies are used mainly in offline converters where supply voltage would be more than the switching transistors could safely tolerate. Bridge topologies are almost always used where the normal AC input voltage is 220 V or higher, and frequently

3、 even for 120-V AC inputs.An additional valuable feature of the bridge topologies is that primary leakage inductance spikes (Figures 2.1 and 2.10) are easily clamped to the DC supply bus and the energy stored in the leakage inductance is returned to the input instead of having to be dissipated in a

4、resistive snub -ber element.3.2 Half-Bridge Converter Topology3.2.1 Basic OperationHalf-bridge converter topology is shown in Figure 3.1. Its major advantage is that, like the double-ended forward converter, it subjects the “off” transistor to only V dc and not twice that value. Thus it is widely us

5、ed in equipment intended for the European market, where the AC input voltage is 220 V. First consider the input rectifier and filter in Figure 3.1. It is used universally when the equipment is to work from either120-VACAmerican power or 220-V AC European power. The circuit always yields roughly 320-

6、V rectified DC voltage, whether the input is 120 orFIGURE 3.1 Half-bridge converter. One end of the power transformer primary is connected to the junction of filter capacitors C1, C2 via a small DC locking capacitor Cb . The other end is connected to the junction of Q1, Q2, which turn “on” and “off”

7、 on alternate half cycles. With S1 in the closed position, the circuit is a voltage doubler ; in the open position, it is a full-wave rectifier. In either case, the rectified output is about 308 to 336 V dc.220 V AC. It does this when switch S1 is set to the open position for 220-V AC input, or to t

8、he closed position for 120-V AC input. The S1 component is normally not a switch; more often it is a wire link that is either installed for 120 V AC, or not for 220 V AC.With the switch in the open 220-V AC position the circuit is a full wave rectifier, with filter capacitors C1 and C2 in series. It

9、 produces a peak rectified DC voltage of about (1.41×220) 2 or 308 V. When the switch is in the closed 120-V AC position , the circuit acts as a voltage doubler. One half cycle of the input voltage when A is positive relativeto B, C1 is charged positively via D1 to a peak of (1.41 × 120) 1

10、 or 168 V. On a half cycle when A is negative with respect to B, capacitor C2 is charged positively via D2 to 168 V. The total voltage across C1 and C2 in series is then 336 V. It can be seen in Figure 3.1 that with either transistor “on,” the “off” transistor is subjected to the maximum DC input vo

11、ltage and not twice that value. Since the topology subjects the “off” transistor to only Vdc and not 2Vdc, there are many inexpensive bipolar and MOSFET transistors that can support the nominal 336 DC V plus 15% upper maximum of 386 V. Thus the equipment can be used with either 120- or 220-V AC line

12、 inputs by making a simple switch or linkage change.Assuming a nominal rectified DC voltage of 336 V, the topology works as follows: For the moment, ignore the small series blocking capacitor Cb . Assume the bottom end of Np is connected to the junction of C1 and C2. Then if the leakages in C1, C2 a

13、re assumed to be equal, that point will be at half the rectified DC voltage, about 168 V. It is generally good practice to place equal bleeder resistors across C1 and C2 to equalize their voltage drops. Now Q1 and Q2 conduct on alternate half cycles. When Q1 is “on” and Q2 “off” (Figure 3.1), the do

14、t end of Np is 168 V positive with respect to its no-dot end, and the “off” stress on Q2 is only 336 V. When Q2 is “on” and Q1 “off,” the dot end of Np is 168 V negative with respect to its no-dot end and the emitter of Q1 is 336 V negative with respect to its collector.This AC square-wave primary v

15、oltage produces full-wave squareWave-shapes on all second-ariesexactly like the secondary voltages in the push-pull topology. The selection of secondary voltages and wire sizes and the output inductor and capacitor proceed exactly as for the push-pull circuit.3.2.2 Half-Bridge Magnetics3.2.2.1 Selec

16、ting Maximum “On” Time, Magnetic Core,and Primary TurnsIt can be seen in Figure 3.1, that if Q1 and Q2 are “on” simultaneouslyeven for a very short timethere is a short circuit across the supply voltage and the transistors will be destroyed. To make sure that this does not happen, the maximum Q1 or

17、Q2 “on” time, which occurs at minimum DC supply voltage, will be set at 80% of a half period. The secondary turns will be chosen so that the desired output voltages are obtained with an “on” time of no more than 0.8T/2. An “on”-time clamp will be provided to ensure that the “on” time can never be gr

18、eater than 0.8T/2 under fault or transient conditions.The core is selected from the tables in Chapter 7 mentioned earlier. These tables give maximum available output power as a function of operating frequency, peak flux density, core and iron areas, and coil current density.With a core selected and

19、its iron area known, the number of primary turns is calculated from Faradays law (Eq. 1.17) using the minimum primary voltage (Vdc/2) 1, and the maximum “on” time of 0.8T/2. Here, the flux excursion dB in the equation is twice the desired peak flux density (1600 G below 50 kHz, or less at higher fre

20、quency), because the half-bridge core operates in the first and third quadrants of its hysteresis loopunlike the forward converter (Section 2.3.9), which operates in the first quadrant only.3.2.2.2 The Relation Between Input Voltage,Primary Current, and Output PowerIf we assume an efficiency of 80%,

21、 thenPin = 1.25PoThe input power at minimum supply voltage is the product of minimum primary voltage and average primary current at minimum DC input. At minimum DC input, the maximum “on” time in each half period will be set at 0.8T/2 as discussed above, and the primary has two current pulses of wid

22、th 0.8T/2 per period T. At primary voltage Vdc/2, the input power is 1.25Po = (Vdc/2)( Ipft)(0.8T/T),where Ipft is the peak equivalent flat-topped primary current pulse. ThenIpft (half bridge) = 3.13P0/Vdc(3.1)3.2.2.3 Primary Wire Size SelectionPrimary wire size must be much larger in a half bridge

23、than in a push-pull circuit of the same output power. However, there are two half primaries in the push-pull, each of which has to support twice the voltage of the half-bridge primary when operated from the same supply voltage. Consequently, coil sizes for the two topologies are notmuch different. H

24、alf-bridge primary RMS current isIrms = Ipft0.8T/Tand from Eq. 3.1 Irms = 2.79Po/Vdc (3.2)At 500 circular mils per RMS ampere, the required number of circular mils is Circular mils needed = 500 × 2.79Po/Vdc= 1395Po/Vdc (3.3)3.2.2.4 Secondary Turns and Wire Size SelectionIn the following treatme

25、nt the number of secondary turns will be selected using Eqs. 2.1 to 2.3 for Ton = 0.8T/2, and the term Vdc 1 will be replaced by theminimumprimary voltage, which is (Vdc/2)1. The secondary RMS currents and wire sizes are calculated from Eqs. 2.13 and 2.14, exactly as for the full-wave secondaries of

26、 a push-pull circuit.3.2.3 Output Filter CalculationsThe output inductor and capacitor are selected using Eqs. 2.20 and 2.22 as in a push-pull circuit for the same inductor current ramp amplitude and desired output ripple voltage.3.2.4 Blocking Capacitor to AvoidFlux ImbalanceTo avoid the flux-imbal

27、ance problem discussed in connection with the push-pull circuit (Section 2.2.5), a small capacitor Cb is fitted in series with the primary as in Figure 3.1. Recall that flux imbalance occurs if the volt-second product across the primary while the core is set (moves in one direction along the hystere

28、sis loop) differs from the volt-second product after it moves in the opposite direction. Thus, if the junction of C1 and C2 is not at exactly half the supply voltage, the voltage across the primary when Q1 is “on” will differ from the voltage across it when Q2 is “on” and the core will walk up or do

29、wn the hysteresis loop, eventually causing saturation and destroying the transistors.This saturating effect comes about because there is an effective DC current bias in the primary. To avoid this DC bias, the blocking capacitor is placed in series in the primary. The capacitor value is selectedFIGUR

30、E 3.2 The small blocking capacitor Cb in series with the half-bridge primary (Figure 3.1) is needed to prevent flux imbalance if the junction of the filter capacitors is not at exactly the midpoint of the supply voltage. Primary current charges the capacitor, causing a droop in the primary voltage w

31、aveform. This droop should be kept to no more than 10%. (The droop in primary voltage, due to the offset charging of the blocking capacitor, is shown as dV.) as follows. The capacitor charges up as the primary current Ipft flows into it, robbing voltage from the flat-topped primary pulse shown in Fi

32、gure 3.2.This DC offset robs volt-seconds from all secondary windings and forces a longer “on” time to achieve the desired output voltage. In general, it is desirable to keep the primary voltage pulses as flat-topped as possible.In this example, we will assume a permissible droop of dV. The equivale

33、nt flat-topped current pulse that causes this droop is Ipft in Eq. 3.1. Then, because that current flows for 0.8T/2, the required capacitor magnitude is simplyCb = Ipft × 0.8T/2Vdc (3.4)Consider an example assuming a 150-W half bridge operating at 100 kHz from a nominal DC input of 320 V. At 15

34、% low line, the DC input is 272 V and the primary voltage is ±272/2 or ± 136V.A tolerable droop in the flat-topped primary voltage pulse wouldbe 10% or about 14 V.Then fromEq. 3.1 for 150Wand Vdc of 272V, Ipft =3.13×150/272= 1.73 A, and from Eq. 3.4, Cb = 1.73 × 0.8 × 5 

35、5; 106/14 = 0.49 uF. The capacitor must be a nonpolarized type.3.2.5 Half-Bridge LeakageInductance ProblemsLeakage inductance spikes, which are so troublesome in the singleended forward converter and push-pull topology, are easily avoided in the half bridge: they are clamped to Vdc by the clamping d

36、iodes D5, D6 across transistors Q1, Q2.Assuming Q1 is “on,” the load and magnetizing currents flow through it and through the primary leakage inductance of T1, the paralleled T1 magnetizing inductance, and the secondary load impedances that are reflected by their turn ratios squared into the primary

37、. Then it flows through Cb into the C1, C2 junction. The dot end of Np is positive with respect to its no-dot end.When Q1 turns “off,” the magnetizing inductance forces all winding polarities to reverse. The dot end of T1 starts to go negative by flyback action, and if this were to continue, it woul

38、d put more than Vdc across Q1 and could damage it. Also, Q2 could be damaged by imposing a reverse voltage across it. However, the dot end of T1 is clamped by diode D6 to the supply rail Vdc and can go no more negative than the negative end of the supply.Similarly, when Q2 is “on,” it stores current

39、 in the magnetizing inductance, and the dot end of Np is negative with respect to the no-dot end (which is close to Vdc/2). When Q2 turns “off,” the magnetizing inductance reverses all winding polarities by flyback action and the dot end of Np tries to go positive but is caught at Vdc by clamp diode

40、 D5. Thus the energy stored in the leakage inductance during the “on” time is returned to the supply rail Vdc via diodes D5, D6.譯文：第三章 半橋和全橋變換器拓?fù)?.1 概述半橋和全橋拓?fù)溟_(kāi)關(guān)管的穩(wěn)態(tài)關(guān)斷電壓等于直流輸入電壓，而不像推挽、單端正激或交錯(cuò)正激拓?fù)淠菢訛殡妷旱膬杀?。所以橋式拓?fù)鋸V泛用于直接電網(wǎng)的離線式變換器。而對(duì)推挽等拓?fù)鋪?lái)說(shuō)，兩倍的電網(wǎng)整流電壓將超過(guò)其開(kāi)關(guān)管的安全耐壓容限。為此，輸入網(wǎng)壓為220V或更高的場(chǎng)合幾乎都使用橋式拓?fù)?。?dāng)輸入網(wǎng)壓為120V時(shí)也有

41、使用橋式拓?fù)涞那闆r。橋式拓?fù)涞牧硪粌?yōu)點(diǎn)是，能將變壓器初級(jí)側(cè)的漏感尖峰電壓（如圖2.1和圖2.10所示）箝位于直流母線電壓，并將漏感儲(chǔ)存的能量歸還到輸入母線，而不是消耗于電阻元件。3.2 半橋變換器拓?fù)?.2.1 工作原理半橋變換器拓?fù)浣Y(jié)構(gòu)如圖3.1所示。其主要優(yōu)點(diǎn)是，開(kāi)關(guān)管關(guān)斷時(shí)承受電壓為Vdc（與雙端正激變換器相同），而不是像推挽拓?fù)浠蚴菃味苏ぷ儞Q器那樣為2Vdc。因此，該拓?fù)湓诰W(wǎng)壓為220V的歐洲市場(chǎng)設(shè)備中得到廣泛應(yīng)用。首先看圖3.1中的輸入整流和濾波部分。當(dāng)要求設(shè)備適應(yīng)不同的網(wǎng)壓（120V AC（美國(guó)）或220V AC(歐洲)）時(shí)，這是一種普遍采用的方案。不管輸入網(wǎng)壓是120V AC還

42、是220V AC，該電路整流得到的直流電壓均為320V。當(dāng)輸入網(wǎng)壓為220V AC時(shí)，S1斷開(kāi)；為120V AC時(shí)，S1閉合。事實(shí)上S1并不是實(shí)際的開(kāi)關(guān)，而是一個(gè)根據(jù)不同輸入而閉合或斷開(kāi)的接點(diǎn)。S1斷開(kāi)時(shí)，輸入為220V交流電壓，電路為全波整流電路，濾波電容C1和C2串聯(lián)，整流得到的直流電壓峰值約為1.41X220-2=308V；當(dāng)S1閉合時(shí)，輸入為120V交流電壓，電路相當(dāng)于一個(gè)倍壓整流器。在輸入電壓的正半周，A點(diǎn)相對(duì)于B點(diǎn)為正，電源通過(guò)D1給C1充電，C1電壓為上正下負(fù)，峰值約為1.41X120-1=168V；在輸入電壓的負(fù)半周，A點(diǎn)電壓相對(duì)于B點(diǎn)為負(fù)，電源通過(guò)D2給C2充電，C2電壓為上

43、正下負(fù)，峰值也為1.41X120-1=168V，這樣兩個(gè)電容串聯(lián)的輸出為336V。從圖3.1可見(jiàn)，當(dāng)任何一個(gè)晶體管導(dǎo)通時(shí)，另一個(gè)關(guān)斷的晶體管承受的電壓只是最大直流輸入電壓，而并非其兩倍。因此，在電路可以采用價(jià)格較低的雙極性晶體管和場(chǎng)效應(yīng)管，他們能承受336V的開(kāi)路電壓（即使考慮15%的裕量，386V 也在可承受范圍之內(nèi)）。這樣，只需要一個(gè)普通的開(kāi)關(guān)或者連接點(diǎn)的切換，裝置就可以工作于120V或220V交流電中。假設(shè)整流后輸入的直流電壓為336V，該電路工作情況如下。首先忽略小容量阻斷電容Cb，則Np的下端可近似地看作連接到C1與C2的連接點(diǎn)。若C1、C2的容量基本相等，則連接點(diǎn)處的電壓近似為整流

44、輸出電壓的一半，約為168V。通常的做法是在C1、C2兩端各并接等值放電電阻來(lái)均衡兩者的電壓。圖3.1中的開(kāi)關(guān)管Q1、Q2輪流導(dǎo)通半個(gè)周期。Q1導(dǎo)通Q2關(guān)斷時(shí)，Np同名端（又端點(diǎn)）電壓為+168V,Q2承受電壓為336V；同理，Q2導(dǎo)通Q1關(guān)斷時(shí)，Q1承受電壓也為336V，此時(shí)Np同名端電壓為-168V。圖3.1 半橋變換器。開(kāi)關(guān)管的一端通過(guò)直流阻斷電容Cb與濾波電容C1、C2相連，另一端接在開(kāi)關(guān)管Q1、Q2的連接點(diǎn)，功率晶體管Q1、Q2交替導(dǎo)通。當(dāng)開(kāi)關(guān)S1閉合時(shí)，電路為倍壓整流器；而斷開(kāi)時(shí)，電路為全波整流器。整流后的輸出電壓約為308-336V和推挽拓?fù)湟粯樱跫?jí)交流方波電壓使所有次級(jí)感應(yīng)全

45、波式方波電壓，因此這種半橋電路的次級(jí)電壓、導(dǎo)線規(guī)格、輸出電感和電容的選擇都與推挽式電路相同。3.2.2 半橋變換器磁芯設(shè)計(jì)3.2.2.1最大導(dǎo)通時(shí)間、磁芯尺寸和初級(jí)繞組匝數(shù)的選擇從圖3.1可見(jiàn)，若Q1、Q2同時(shí)導(dǎo)通，即使是很短時(shí)間，也將使電源瞬間短路從而損壞開(kāi)關(guān)管。為防止此現(xiàn)象發(fā)生，輸入電壓為最小時(shí)，Q1或Q2的最大導(dǎo)通時(shí)間必須限制在半周期的80%以內(nèi)。應(yīng)選擇合適的次級(jí)匝數(shù)使在導(dǎo)通時(shí)間不大于0.8T/2的情況下保證輸出電壓滿足要求。此外，電路將采用箝位技術(shù)以保證在不正常工作狀態(tài)下導(dǎo)通時(shí)間也不超過(guò)0.8T/2。磁芯可利用第七章中提供的表格進(jìn)行選擇，這些表格給出了額定工作頻率下端最大輸出功率、飽和

46、磁感應(yīng)強(qiáng)度、磁芯尺寸、磁芯面積及繞線電流密度之間的函數(shù)關(guān)系。假定最低輸入電壓為（Vdc/2）-1，最大導(dǎo)通時(shí)間為0.8T/2.，在已知磁芯種類和磁芯面積的情況下，可以通過(guò)法拉第定律（式（1.17）計(jì)算出初級(jí)繞組匝數(shù)。該市中的dB值為峰值磁密期望值（頻率低于50KHz時(shí)選用1600G，頻率越高該值越?。┑膬杀?。2.3.9節(jié)中講過(guò)，正激變換器的磁芯工作于磁滯回線的第一、三象限，所以半橋變換器磁通擺幅dB取峰值磁密期望值的兩倍。3.2.2.2 初級(jí)電流、輸出功率、輸入電壓之間的關(guān)系設(shè)效率為80%，則有Input power=Pin=1.25Po電源輸入電壓最低時(shí)，輸入功率等于初級(jí)電壓最小值與對(duì)應(yīng)的初級(jí)平均電流的乘積。如前所述，輸入直流電壓最小時(shí)，每半周期導(dǎo)通時(shí)間最大值選為0.8T/2/。由于每周期有兩個(gè)脈寬為0.8T/2的電流脈沖，電壓為Vdc/2時(shí)的輸入功率為1.25Po=（Vdc/2）（Ipft）（0.8T/T），其中，Ipft為初級(jí)電流脈沖等效為平頂脈沖后的峰值Ipft（半橋）=3.13PoVdc （3.1）3.2.2.3 初級(jí)線徑的選擇在