eda交通燈課程設(shè)計(jì)new

1、湖南工程學(xué)院課 程 設(shè) 計(jì)課程名稱 嵌入式系統(tǒng) 課題名稱 十字路口的交通信號燈的控制電路設(shè)計(jì) 專 業(yè) 電子信息工程 班 級 電子信息0703 學(xué) 號 200701030309 姓 名 李 海 指導(dǎo)教師 賀 攀 峰 2010年 12月 20日湖南工程學(xué)院課 程 設(shè) 計(jì) 任 務(wù) 書課程名稱： 嵌入式系統(tǒng) 題 目：十字路口的交通信號燈的控制電路設(shè)計(jì)專業(yè)班級： 電信0703班 學(xué)生姓名： 李海 指導(dǎo)老師： 賀攀峰審 批： 任務(wù)書下達(dá)日期 2010 年12 月 20日設(shè) 計(jì) 完成日期 2010 年 12月 31日 設(shè)計(jì)內(nèi)容與設(shè)計(jì)要求CPLD為復(fù)雜可編程邏輯器件，通過EDA技術(shù)對其進(jìn)行編程，可將一個(gè)較復(fù)雜

2、的數(shù)字系統(tǒng)集成于一個(gè)芯片中，制成專用集成電路芯片，并可隨時(shí)在系統(tǒng)修改其邏輯功能。有關(guān)知識可參見相關(guān)教材或參考書。一設(shè)計(jì)內(nèi)容1. 設(shè)計(jì)制作一塊十字路口的交通信號燈的控制電路的專用芯片。2. A方向和B方向各設(shè)置紅（R）、黃（Y）、綠（G）三盞燈，三盞燈按合理的順序亮滅，并能將燈亮的時(shí)間以倒計(jì)時(shí)的方式顯示出來。3. 兩個(gè)方向各燈的時(shí)間可方便地進(jìn)行設(shè)置和修改。假設(shè)A方向?yàn)橹鞲傻?，車流量大，A方向通行時(shí)間比B方向長。設(shè)A方向每次至少通行t1秒,B方向每次至多通行t2秒,黃燈亮t秒。二、設(shè)計(jì)要求：1、 設(shè)計(jì)思路清晰，給出整體設(shè)計(jì)框圖；2、 在QUARTUS中設(shè)計(jì)各單元電路，完成其功能仿真和編譯并生成低層

3、模塊；3、 在QUARTUS中完成頂層設(shè)計(jì)并編譯通過；4、 在QUARTUS中完成設(shè)計(jì)下載并調(diào)試電路；5、寫出設(shè)計(jì)報(bào)告；主要設(shè)計(jì)條件1. 提供EDA實(shí)驗(yàn)室；2. 提供EL實(shí)驗(yàn)箱和CPLD芯片;3. 提供ALTERA公司的QUARTUS II設(shè)計(jì)軟件說明書格式1. 課程設(shè)計(jì)封面；2. 任務(wù)書；3. 說明書目錄；4. 設(shè)計(jì)總體思路，基本原理和框圖（頂層電路圖）；5. 單元電路設(shè)計(jì)（各次級模塊電路圖）；6. 設(shè)計(jì)仿真；7. 編程下載；8. 總結(jié)與體會；9. 附錄；10. 參考文獻(xiàn)。進(jìn)度安排星期一、二：下達(dá)設(shè)計(jì)任務(wù)書，介紹課題內(nèi)容與要求；介紹QUARTUS軟件的使用；查找資料，確定總體設(shè)計(jì)方案和單元電

4、路設(shè)計(jì)；星期三第二周星期一：單元電路設(shè)計(jì)與仿真，硬件下載；第二周星期二、三：硬件下載；第二星期四、五：書寫設(shè)計(jì)報(bào)告，打印相關(guān)圖紙；答辯參考文獻(xiàn)1. 康華光主編.電子技術(shù)基礎(chǔ)（數(shù)字部分），高等教育出版社。2. 閻石主編. 電子技術(shù)基礎(chǔ)（數(shù)字部分），清華大學(xué)出版社。3. 陳大欽主編，電子技術(shù)基礎(chǔ)實(shí)驗(yàn)，高等教育出版社。4. 彭介華主編，電子技術(shù)課程設(shè)計(jì)指導(dǎo)，高等教育出版社。5. 張 原編著，可編程邏輯器件設(shè)計(jì)及應(yīng)用，機(jī)械工業(yè)出版社。6.荀殿棟，徐志軍編著，數(shù)字電路設(shè)計(jì)實(shí)用手冊，電子工業(yè)出版社。7. QUARTUS入門8.劉洪喜，陸穎編著. VHDL電路設(shè)計(jì)實(shí)用教程 清華大學(xué)出版社 目 錄1 .總體設(shè)

5、計(jì)11.1 設(shè)計(jì)總體思路11.2 總體框圖22.單元電路設(shè)計(jì)22.1 控制模塊22.2計(jì)數(shù)模塊52.2.1 25進(jìn)制遞減計(jì)數(shù)器的VHDL源文件62.2.2 3進(jìn)制遞減計(jì)數(shù)器的VHDL源文件82.2.3 35進(jìn)制遞減計(jì)數(shù)器的VHDL源文件102.2.4 30進(jìn)制遞減計(jì)數(shù)器的VHDL源文件122.2.5 45進(jìn)制遞減計(jì)數(shù)器的VHDL源文件142.3 顯示模塊163. 總電路設(shè)計(jì)203.1 仿真結(jié)果203.2 仿真結(jié)果分析214.總結(jié)與體會225.參考文獻(xiàn)231 .總體設(shè)計(jì)1.1 設(shè)計(jì)總體思路用FPGA為核心器件,用VHDL為設(shè)計(jì)手段設(shè)計(jì)制作一個(gè)十字路口交通管理器。該管理器控制甲、乙兩道（乙道為主干

6、道）的左轉(zhuǎn)燈、直行燈和等待黃燈，用以指揮車輛有序安全通過。交通管理器示意圖如圖所示: 圖1-1 交通管理示意圖圖中R1、G1、 Y1分別表示甲道左轉(zhuǎn)、直行、等待燈（滅表示通行，亮表示禁止）；R2、Y2、G2分別表示乙道左轉(zhuǎn)、直行、等待燈（滅表示通行，亮表示禁止）。定時(shí)器分別確定甲道和乙道左轉(zhuǎn)及直行的通行時(shí)間和等待黃燈亮的時(shí)間。具體設(shè)計(jì)要求如下：用四位數(shù)碼顯示器分別顯示甲乙兩道左轉(zhuǎn)、直行、等待時(shí)間（每邊兩位）；其計(jì)時(shí)間隔為1S。交通燈控制器工作流程如下：甲道左轉(zhuǎn)通行（甲道直行禁止，乙道全禁止）25S等待（甲黃燈亮）3S甲道直行通行（甲道左轉(zhuǎn)禁止，乙道全禁止）35S-等待（甲黃燈亮）3S乙道左轉(zhuǎn)通

7、行（乙道直行禁止，甲道全禁止）30S等待（乙黃燈亮）3S乙道直行通行（乙道左轉(zhuǎn)禁止，甲道全禁止）45S-等待（乙黃燈亮）3S重復(fù)因此，我設(shè)置7個(gè)狀態(tài)，用w0到w4控制狀態(tài)的轉(zhuǎn)換。c1到c5、b1到b5控制計(jì)數(shù)器計(jì)數(shù)。同時(shí)，c1到c5控制數(shù)碼管顯示方式。1.2 總體框圖交通燈控 制模 塊計(jì) 數(shù)模 塊顯示模 塊 圖1-2 總體框圖2.單元電路設(shè)計(jì)2.1 控制模塊控制模塊是整個(gè)模塊的核心?？刂浦鞣N狀態(tài)之間的轉(zhuǎn)換，從而實(shí)現(xiàn)設(shè)計(jì)要求實(shí)現(xiàn)的功能?？刂颇K的VHDL源文件如下： LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY jiaotong ISPORT(

8、clk :IN STD_LOGIC;c1,c2,c3,c4,c5,b1,b2,b3,b4,b5:OUT STD_LOGIC;w0,w1,w2,w3,w4 :IN STD_LOGIC; R1,R2 :OUT STD_LOGIC;Y1,Y2 :OUT STD_LOGIC;G1,G2 :OUT STD_LOGIC;reset :IN STD_LOGIC);END jiaotong;ARCHITECTURE a OF jiaotong ISTYPE STATE_SPACE IS(S0,S1,S2,S3,s4,s5,s6,s7);SIGNAL state:STATE_SPACE;BEGINPROCESS

9、(clk)BEGINIF (reset='1') THENstate<=S0;ELSIF (clk'event and clk='1') THEN CASE state is WHEN s0=> IF (w0='1') THEN state<=s1;-25s END IF; b1<='0'IF(w0='0') THEN b1<='1'END IF; WHEN s1=>IF (w1='1')THEN state<=s2;-3s END

10、IF;b2<='0'IF (w1='0') THEN b2<='1'END IF;WHEN s2=>IF (w2='1')THEN state<=s3;-35s END IF;b3<='0'IF (w2='0') THEN b3<='1'END IF; WHEN s3=>IF (w1='1')THEN state<=s4;-3sEND IF;b2<='0'IF (w1='0') TH

11、EN b2<='1'END IF;WHEN s4=>IF (w3='1')THEN state<=s5;-30s END IF;b4<='0'IF (w3='0') THEN b4<='1'END IF; WHEN s5=>IF w1='1'THEN state<=s6;-3s END IF;b2<='0'IF (w1='0') THEN b2<='1'END IF;WHEN s6=>IF (

12、w4='1')THEN state<=s7;-45s END IF; b5<='0'IF (w4='0') THEN b5<='1'END IF;WHEN s7=>IF (w1='1')THEN state<=s0;-3s END IF; b2<='0'IF (w1='0') THEN b2<='1'END IF; END CASE; END IF; END PROCESS;c1<='1' when st

13、ate=s0 else '0'c2<='1' when state=s1 or state=s3 or state=s5 or state=s7 else '0'c3<='1' when state=s2 else '0'c4<='1' when state=s4 else '0'c5<='1' when state=s6 else '0'R1<='0' when state=s0 else '1&

14、#39;G1<='0' when state=s2 else'1'Y1<='0' when state=s1 or state=s3 else'1'R2<='0' when state=s4 else '1'G2<='0' when state=s6 else '1'Y2<='0' when state=s5 or state=s7 else '1'END a;2.2計(jì)數(shù)模塊 計(jì)數(shù)模塊主要是為實(shí)現(xiàn)各種狀態(tài)的

15、計(jì)數(shù)時(shí)間。這里需要的計(jì)數(shù)器的計(jì)數(shù)范圍為0-80。計(jì)到80后，下一個(gè)時(shí)鐘沿回復(fù)到0，開始下一輪計(jì)數(shù)。此外，當(dāng)檢測到特殊情況（EMI =1）發(fā)生是，計(jì)數(shù)器暫停計(jì)數(shù)，而系統(tǒng)復(fù)位信號RESET則使計(jì)數(shù)器異步清零。圖2.1計(jì)數(shù)器模塊2.2.1 25進(jìn)制遞減計(jì)數(shù)器的VHDL源文件library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jcnt20 ISPORT(clk: INSTD_LOGIC;cr: IN STD_LOGIC;EN1: INSTD_LOGIC;J0 : OUTSTD_LOGIC;q1:

16、 OUT STD_LOGIC_VECTOR (3 DOWNTO 0); y10: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );END jcnt20;ARCHITECTURE a OF jcnt25 ISSIGNALbcd1n: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNALvcd10n: STD_LOGIC_VECTOR (3 DOWNTO 0);BEGINPROCESS (clk,cr)BEGINIF (cr = '0') THENbcd1n <= "0000"ELSIF (EN1='1

17、') THEN IF (clk'EVENT AND clk = '1') THENIF (bcd1n=0 and vcd10n/=0) THEN bcd1n<="1001" ELSif (bcd1n=0 and vcd10n=0) THENbcd1n <= "0000"ELSEbcd1n <= bcd1n-1;END IF; END IF; END IF; END PROCESS;q1 <= bcd1n; y10 <= vcd10n;PROCESS (clk, cr)BEGINIF (cr =

18、 '0') THENvcd10n <= "0010"ELSIF (EN1='1') THEN IF(clk'EVENT AND clk = '1') THENIF (bcd1n=0) THEN IF (vcd10n=0) THEN vcd10n<="0000" ELSE vcd10n <= vcd10n-1; END IF; END IF;END IF;END IF;END PROCESS;PROCESS(bcd1n,vcd10n) BEGIN J0<='0'

19、 if (bcd1n=0 and vcd10n=0) THENJ0<='1'END IF;END PROCESS;end a;2.2.2 3進(jìn)制遞減計(jì)數(shù)器的VHDL源文件library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jcnt3 ISPORT(clk: INSTD_LOGIC;cr: INSTD_LOGIC;EN2: INSTD_LOGIC;J1 : OUTSTD_LOGIC;q1: OUT STD_LOGIC_VECTOR (3 DOWNTO 0); END

20、jcnt3;ARCHITECTURE a OF jcnt3 ISSIGNALbcd1n: STD_LOGIC_VECTOR (3 DOWNTO 0); BEGINPROCESS (clk,cr)BEGINIF (cr = '0') THENbcd1n <= "0011" ELSIF (EN2='1') THEN IF (clk'EVENT AND clk = '1') THENIF (bcd1n=0 ) THENbcd1n <= "0000"ELSEbcd1n <= bcd1n-1

21、;END IF; END IF; END IF; END PROCESS;q1 <= bcd1n; PROCESS(bcd1n) BEGIN J1<='0' if (bcd1n=0 ) THENJ1<='1'END IF;END PROCESS;end a;2.2.3 35進(jìn)制遞減計(jì)數(shù)器的VHDL源文件 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jcnt35 ISPORT(clk: INSTD_LOGIC;cr: INSTD_L

22、OGIC;EN3: INSTD_LOGIC;J2 : OUTSTD_LOGIC;q1: OUT STD_LOGIC_VECTOR (3 DOWNTO 0); y10: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );END jcnt35;ARCHITECTURE a OF jcnt35 ISSIGNALbcd1n: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNALvcd10n: STD_LOGIC_VECTOR (3 DOWNTO 0);BEGINPROCESS (clk,cr)BEGINIF (cr = '0') THENbc

23、d1n <= "0101" -J1<='1' ELSIF (EN3='1') THEN IF (clk'EVENT AND clk = '1') THENIF (bcd1n=0 and vcd10n/=0) THEN bcd1n<="1001" ELSif (bcd1n=0 and vcd10n=0) THENbcd1n <= "0000"ELSEbcd1n <= bcd1n-1;END IF; END IF; END IF; END PROCESS

24、;q1 <= bcd1n; y10<=vcd10n;PROCESS (clk, cr)BEGINIF (cr = '0') THENvcd10n <= "0011"-J1<='1'ELSIF (EN3='1') THEN IF(clk'EVENT AND clk = '1') THENIF (bcd1n=0) THEN IF (vcd10n=0) THEN vcd10n<="0000" ELSE vcd10n <= vcd10n - 1; END

25、IF; END IF;END IF;END IF;END PROCESS;PROCESS(bcd1n,vcd10n) BEGIN J2<='0' if (bcd1n=0 and vcd10n=0) THENJ2<='1'END IF;END PROCESS;end a;2.2.4 30進(jìn)制遞減計(jì)數(shù)器的VHDL源文件library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jcnt30 ISPORT(clk: INSTD_LOGIC;cr: INSTD

26、_LOGIC;EN4: INSTD_LOGIC;J3 : OUTSTD_LOGIC;q1: OUT STD_LOGIC_VECTOR (3 DOWNTO 0); y10: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );END jcnt30;ARCHITECTURE a OF jcnt30 ISSIGNALbcd1n: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNALvcd10n: STD_LOGIC_VECTOR (3 DOWNTO 0);BEGINPROCESS (clk,cr)BEGINIF (cr = '0') THEN

27、bcd1n <= "0000" -J1<='1' ELSIF (EN4='1') THEN IF (clk'EVENT AND clk = '1') THENIF (bcd1n=0 and vcd10n/=0) THEN bcd1n<="1001" ELSif (bcd1n=0 and vcd10n=0) THENbcd1n <= "0000"ELSEbcd1n <= bcd1n-1;END IF; END IF; END IF; END PROCE

28、SS;q1 <= bcd1n; y10<=vcd10n;PROCESS (clk, cr)BEGINIF (cr = '0') THENvcd10n <= "0011"-J1<='1'ELSIF (EN4='1') THEN IF(clk'EVENT AND clk = '1') THENIF (bcd1n=0) THEN IF (vcd10n=0) THEN vcd10n<="0000" ELSE vcd10n <= vcd10n - 1; EN

29、D IF; END IF;END IF;END IF;END PROCESS;PROCESS(bcd1n,vcd10n) BEGIN J3<='0' if (bcd1n=0 and vcd10n=0) THENJ3<='1'END IF;END PROCESS;end a;2.2.5 45進(jìn)制遞減計(jì)數(shù)器的VHDL源文件library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY jcnt45 ISPORT(clk: INSTD_LOGIC;cr: INS

30、TD_LOGIC;EN5: INSTD_LOGIC;J4 : OUTSTD_LOGIC;q1: OUT STD_LOGIC_VECTOR (3 DOWNTO 0); y10: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );END jcnt45;ARCHITECTURE a OF jcnt45 ISSIGNALbcd1n: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNALvcd10n: STD_LOGIC_VECTOR (3 DOWNTO 0);BEGINPROCESS (clk,cr)BEGINIF (cr = '0') TH

31、ENbcd1n <= "0101" ELSIF (EN5='1') THEN IF (clk'EVENT AND clk = '1') THENIF (bcd1n=0 and vcd10n/=0) THEN bcd1n<="1001" ELSif (bcd1n=0 and vcd10n=0) THENbcd1n <= "0000"ELSEbcd1n <= bcd1n-1;END IF; END IF; END IF; END PROCESS;q1 <= bcd1n;

32、 y10<=vcd10n;PROCESS (clk, cr)BEGINIF (cr = '0') THENvcd10n <= "0100"ELSIF (EN5='1') THEN IF(clk'EVENT AND clk = '1') THENIF (bcd1n=0) THEN IF (vcd10n=0) THEN vcd10n<="0000" ELSE vcd10n <= vcd10n - 1; END IF; END IF;END IF;END IF;END PROCES

33、S;PROCESS(bcd1n,vcd10n) BEGIN J4<='0' if (bcd1n=0 and vcd10n=0) THEN J4<='1'END IF;END PROCESS;end a;2.3 顯示模塊顯示模塊是把計(jì)數(shù)模塊傳過來的數(shù)字轉(zhuǎn)變成對應(yīng)的十進(jìn)制數(shù)顯示出來。顯示模塊的VHDL源文件如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY sm1 IS PORT ( b1,b2,b3,b4,b5:IN STD_LOGIC;

34、Q0:IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q1:IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q2:IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q3:IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q4:IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q5:IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q6:IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q7:IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q8:IN STD_LO

35、GIC_VECTOR(3 DOWNTO 0); CLK : IN STD_LOGIC; SG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -段控制信號輸出 BT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );-位控制信號輸出 END;ARCHITECTURE one OF sm1 IS SIGNAL CN : integer range 0 to 4; SIGNAL CNT2 : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINP1:PR

36、OCESS(CN) BEGIN IF (b1='1') THEN CN<=0;END IF; IF (b2='1') THEN CN<=1;END IF; IF (b3='1') THEN CN<=2;END IF; IF (b4='1') THEN CN<=3;END IF; IF (b5='1') THEN CN<=4;END IF;CASE CN IS WHEN 0=> CASE CNT2 IS WHEN "00" =>BT <= "

37、;00000001" ; A<=Q0; WHEN "01" =>BT <= "00000010" ; A<=Q1; WHEN OTHERS => NULL ; END CASE; WHEN 1=> BT <= "10000000" ; A <= Q2 ; WHEN 2=> CASE CNT2 IS WHEN "00" =>BT <= "00000001" ; A<=Q3; WHEN "01" =

38、>BT <= "00000010" ; A<=Q4; WHEN OTHERS => NULL ; END CASE; WHEN 3=> CASE CNT2 IS WHEN "00" =>BT <= "00000100" ; A<=Q5; WHEN "01" =>BT <= "00001000" ; A<=Q6; WHEN OTHERS => NULL ; END CASE; WHEN 4=> CASE CNT2 IS

39、WHEN "00" =>BT <= "00000100" ; A<=Q7; WHEN "01" =>BT <= "00001000" ; A<=Q8; WHEN OTHERS => NULL ; END CASE; WHEN OTHERS => NULL ; END CASE ; END PROCESS P1; P2:PROCESS( A ) BEGIN CASE A IS WHEN "0000" => SG <= "0111

40、111" WHEN "0001" => SG <= "0000110" WHEN "0010" => SG <= "1011011" WHEN "0011" => SG <= "1001111" WHEN "0100" => SG <= "1100110" WHEN "0101" => SG <= "1101101" WHEN

41、"0110" => SG <= "1111101" WHEN "0111" => SG <= "0000111" WHEN "1000" => SG <= "1111111" WHEN "1001" => SG <= "1101111" WHEN OTHERS => NULL ; END CASE ; END PROCESS P2; P3:PROCESS(CLK) BEGIN IF (clk'EVENT AND clk = '1') THEN CNT2<=CNT2+1;END IF;END PROCESS P3; END; 3. 總電路設(shè)計(jì)3.1 仿真結(jié)果總電路作為頂層模塊，將計(jì)數(shù)模塊、控制模塊和顯示模塊(