正負(fù)脈寬數(shù)控調(diào)制信號發(fā)生器的設(shè)計

1、實驗三：正負(fù)脈寬數(shù)控調(diào)制信號發(fā)生器的設(shè)計1.實驗?zāi)康模?）學(xué)習(xí)isEXPERT/MAX+plus /Foudation Series軟件的基本使用方法。（2）學(xué)習(xí)GW48-CK EDA實驗開發(fā)系統(tǒng)的基本使用方法。（3）學(xué)習(xí)VHDL程序中數(shù)據(jù)對象、數(shù)據(jù)類型、順序語句、并行語句的綜合使用。2.實驗內(nèi)容設(shè)計并調(diào)試好一個脈寬數(shù)控調(diào)制信號發(fā)生器，此信號發(fā)生器是由兩個完全相同的可自由加載加法計數(shù)器LCNT8組成的，它的輸出信號的高/低電平脈寬可以分別由兩組8位預(yù)置數(shù)進(jìn)行控制。用GW48_CK EDA實驗開發(fā)系統(tǒng)（擬采用的實驗芯片的型號為isPLSI1032E OLCC_84）進(jìn)行硬件驗證。3.實驗條件（1

2、）畫出系統(tǒng)的原理框架圖，說明系統(tǒng)中各主要部分的功能。（2）編寫各個VHDL源程序。（3）根據(jù)選用的軟件編好用于系統(tǒng)仿真的測試文件。（4）根據(jù)選用的軟件及EDA實驗開發(fā)裝置編好用于硬件驗證的管腳鎖定文件。（5）記錄系統(tǒng)仿真、硬件驗證結(jié)果。（6）記錄式樣過程中出現(xiàn)的問題、解決方法及注意事項。4.實驗設(shè)計（1）系統(tǒng)原理圖框架脈寬數(shù)控調(diào)制信號發(fā)生器邏輯圖（2）VHDL源程序源程序pulse.vhdlibrary ieee;use ieee.std_logic_1164.all;entity lcnt8 isport(clk,ld:in std_logic;d:in integer range 0 to

3、 255;cao:out std_logic);end entity lcnt8;architecture art of lcnt8 issignal count:integer range 0 to 255;beginprocess(clk) isbeginif clk'event and clk='1' thenif ld='1' then count<=d;else count<=count+1;end if;end if;end process;process(clk,count) isbeginif clk'event an

4、d clk='1' thenif count=255 then cao<='1'else cao<='0'end if;end if;end process;end architecture art;library ieee;use ieee.std_logic_1164.all;entity pulse isport(clk:in std_logic;a,b:in std_logic_vector(7 downto 0);psout:out std_logic);end entity pulse;architecture art o

5、f pulse iscomponent lcnt8 isport(clk,ld:in std_logic;d:in std_logic_vector(7 downto 0);cao:out std_logic);end component lcnt8 ;signal cao1,cao2:std_logic;signal ld1,ld2:std_logic;signal psint:std_logic;beginu1:lcnt8 port map(clk=>clk,ld=>ld1,d=>a,cao=>cao1);u2:lcnt8 port map(clk=>clk,

6、ld=>ld2,d=>b,cao=>cao2);process(cao1,cao2) isbeginif cao1='1' then psint<='0'elsif cao2'event and cao2='1'then psint<='1'end if;end process;ld1<=not psint;ld2<=psint;psout<=psint;end architecture art;（3）波形仿真文件Module pulse;Clk,a87.0,b87.0,ps

7、out pin;Test_vectors(Clk,a87.0,b87.0->psout);0,0,0,0,1,0,0,0,1,0,0,0,1,0,0,0,1->x；1,0,0,1,0,0,0,1,0,0,0,1,0,0,0,1,0->x；0,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1->x；1,0,1,0,0,0,1,0,0,0,1,0,0,0,1,0,0->x；0,0,1,0,1,0,1,0,1,1,1,0,1,0,1,0,1->x；1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0->x；0,0,1,1,1,0,

8、1,1,1,1,1,1,1,0,1,1,1->x；1,1,0,0,0,1,0,0,0,1,0,0,0,1,0,0,0->x；0,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1->x；1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0->x；0,1,0,1,1,1,0,1,1,1,0,1,1,1,0,1,1->x；1,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0->x；0,1,1,0,1,1,1,0,1,1,1,0,1,1,1,0,1->x；1,1,1,1,0,1,1,1,0,1,1,1,0,1,1,1,0->x；0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1->x（4）管腳鎖定文件管腳鎖定設(shè)計圖管腳鎖定文件/pulse.ppn/part: isPLSI1032E OLCC_84/fromat:pinnanme pintype lockclk in 1a7 in 17a6 in 18a5 in 70a4 in 16a3 in 71a2 in 43a1 in 2a0 in 42b7 in 30b6 in 29b5 in 27b4 in 62b3 in 58b2 in 61b1 in 44b0 in