西南交大數(shù)電實驗報告材料

1、實驗二、三：quartus H原理圖設計1.實驗原理圖2.實驗仿真波形【1口1勺暨HL 1XJBU-JU2LXJL就0JLBUlJ血X譏nt 'll 0 Xll lIL&L 1X?1 0 工 W. ftj( IXL fc£ LZL 1 I 3L a I WL 4mi: 、 tnJ O I M J|X】11l£J X DCK'S S|I dE3J X Ml X LU121 I D 1 Gfiji1i1IIL11_imini,run. wijtm. micrrnifiznnwctiinrri ith. kji itt mjtratirnxmjiutxsi

2、tji tpji csjDl. 、 口 i cj xra： Jslhi x mDi 9(13K Bfn I I 閃】B-i x t| i dL1Lrr11Dffl廠niZDIYI J -!TXtl.J:m ji cn x iWftfisa?.i-dd.iig- - > -L1實驗四：Verilog 描述組合邏輯電路1. 一位數(shù)值比較器1.1源代碼module compare(a_gt,a_eq,a_lt,a,b); in put a,b;output a_gt,a_eq,a_lt;assig n a_gt=a&b;assig n a_eq=a&b|a&b; ass

3、ig n a_lt=a&b;en dmodule1.2代碼生成原理圖instb2. 七段譯碼器2.1源代碼module decode4_7(codeout,i ndec); in put3:0 in dec;output6:0 codeout;reg6:0 codeout;always(i ndec)begincase(i ndec)4'd0:codeout=7'b1111110;4'd1:codeout=7'b0110000;4'd2:codeout=7'b1101101;4'd3:codeout=7'b1111001;

4、4'd4:codeout=7'b0110011;4'd5:codeout=7'b1011011;4'd6:codeout=7'b1011111;4'd7:codeout=7'b1110000;4'd8:codeout=7'b1111111;4'd9:codeout=7'b1111011;default: codeout=7'b1001111;endcaseenden dmodule2.2代碼生成原理圖纟塔瑟口 i亠”i I纟 ?鄉(xiāng):/.鄉(xiāng) ins-t* 鄉(xiāng)indec（古.0）codeoatf

5、fi.03. 總原理圖4. 實驗仿真波形圖實驗五：集成觸發(fā)器的應用1.原理圖I j" "" -u"' -,I PITI I七AWH* - I二45¥0HAYINBWC3NG1時h伽V7H-II-S!（廠m- BIHIIIJ2.實驗仿真波形圖2和o 1 Z 3 4 H3-Z3uL2On1 n_nL.TPJINKnn,nrnnHFn_ n.n74198實驗六：移位寄存器實驗2.實驗仿真波形圖1.原理圖nlrLrLrTLn irLVLrLrLirLirLr rLmr rLr rLmrtr rmrLirLr nrLmrj-rLm-015&quo

6、t;ITemNEgCQBDacEQDFQEGUJ-卜ocscOHS1CLRH0-KSHIFT PEG實驗七：十進制可逆計數(shù)器1.十進制可逆計數(shù)器1.1十進制可逆計數(shù)器源代碼module s2014111909(clk,ud,q,co);in put clk,ud;output reg 3:0 q;output co;assign co=(q=9)&&ud)|(q=0) &&(!ud);always (posedge clk)beginif(ud)beginif(q>8) q<=0;else q<=q+1'd1;endelsebegini

7、f(q=0) q<=4'd9; else q<=q-1'd1;endend en dmodule1.2代碼生成原理圖-clkudCD1.3實驗仿真波形圖2.總原理圖3.波形圖lirn別h:oHe(訊K>丨(IE0 4ocboniStfiOE3下OF(呑些F jp .LQ-1& 11-llsj0 1.2Lqjlll&V3-ilC>dPM）實驗實驗八：脈沖寬度調制(1. 實驗代碼module s1909(clk,h,l,out); input clk; input3:0 h,l; output reg out; reg6:0pwmcnt; reg11:0fcnt; wire 6:0 z; reg clk1;assign z=h*10+l; always(posedge clk) beginif(fcnt>=12'd2499) begin clk1<=clk1; fcnt<=0;end elsebegin fcnt<=fcnt+1;end end always(posedge clk1) beginif(pwmcnt<z) begi