單片機(jī)中英文

1、An Overview of AT89S51The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel's high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction s

2、et and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a hig

3、hly-flexible and cost-effective solution to many embedded control applications. Features：Compatible with MCS.-51 Products4K Bytes of In-System Programmable (ISP) Flash MemoryEndurance: 1000 Write/Erase Cycles4.0V to 5.5V Operating RangeFully Static Operation: 0 Hz to 33 MHzThree-level Program Memory

4、 Lock128 x 8-bit Internal RAM32 Programmable I/O LinesTwo 16-bit Timer/CountersSix Interrupt SourcesFull Duplex UART Serial ChannelLow-power Idle and Power-down ModesInterrupt Recovery from Power-down ModeWatchdog TimerDual Data PointerPower-off FlagFast Programming TimeFlexible ISP Programming (Byt

5、e and Page Mode)Green (Pb/Halide-free) Packaging OptionThe AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-

6、chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue

7、 functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.VCC：Supply voltage (all packages except 42-PDIP).GND：Ground (all packages except 42-PDIP; for 42-PDIP GND connects only the logi

8、c core and the embedded program memory).VDD：Supply voltage for the 42-PDIP which connects only the logic core and the embedded program memory.PWRVDD：Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers. The application board MUST connect both VDD and PWRVDD to the board supply volt

9、age.PWRGND：Ground for the 42-PDIP which connects only the I/O Pad Drivers. PWRGND and GND are weakly connected through the common silicon substrate, but not through any metal link. The application board MUST connect both GND and PWRGND to the board ground.Port 0：Port 0 is an 8-bit open drain bi-dire

10、ctional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode,

11、 PO has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffe

12、rs can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (lip) because of the internal pull-ups.Port 2：Port 2 is an 8-bit bi-directi

13、onal I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (lip) because

14、of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVXDPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data

15、 memory that use 8-bit addresses (MOVXRI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The P

16、ort 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (lip) because of the pull-ups.Port 3 receives some contro

17、l signals for Flash programming and verification.Port 3 also serves the functions of various special features of the AT89S51，as shown in the following table.P3 port can also be used as a number of special features AT89C51 mouth, the following table:PinAlternative functionP3.0 RXD（Serial input）P3.1 T

18、XD（Serial output）P3.2 （External interrupt 0）P3.3 （External interrupt 1）P3.4 T0（Timer 0 External input）P3.5 T1（Timer 1 External input）P3.6 （External data memory write strobe）P3.7 （External data memory read strobe）RST：Reset input. A high on this pin for two machine cycles while the oscillator is runni

19、ng resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/PROG：Address Latch Enable (ALE) is an output

20、pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes

21、. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-

22、disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable (PSEN) is the read strobe to external program memory.When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations

23、are skipped during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at OOOOH up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally la

24、tched on reset. EA should be strapped to Vcc for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverti

25、ng oscillator amplifierSpecial Function Registers：Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software shou

26、ld not write 1 s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Interrupt Registers:The individual interrupt enable bits are in the IE register. Two priorities can be set for e

27、ach of the five interrupt sources in the IP register.Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DPO at SFR address locations 82H-83H and DP1 at 84H-85H.Bit DPS=0 in SFR AUXR1 selects DPO and DP

28、S=1 selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to "1”during power up. It can be set and rest under sof

29、tware control and is not affected by reset.Memory Organization：MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.Program Memory：If the EA pin is connected to GND, all program fetches are directed t

30、o external memory. On the AT89S51，if EA is connected to Vcc, program fetches to addresses OOOOH through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.Data Memory：The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are acc

31、essible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.Watchdog Timer (One-time Enabled with Reset-out)：The WDT is intended as a recovery method in situations where the CPU may be subjected to

32、software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01 EH and OE1 H in sequence to the WDTRST register(SFR location OA6H). When the WDT is enabled, it will increment

33、every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin

34、.The use of watchdog (WDT):WDT to be open to write 01EH and 0E1H in sequence to WDTRST registers (SFR's address 0A6H), when the WDT opened, take some time to 01EH and 0E1H to WDTRST count register in order to avoid WDT overflow. WDT counter 14 count reached 16383 (3FFFH), WDT will overflow and r

35、eset the device. WDT is turned on, it will be with the crystal oscillator in each machine cycle count, which means that users must be less than 16,383 machines each cycle reset WDT, that is to write 01EH and 0E1H to WDTRST register, WDTRST write only register. WDT counter can not be read neither wri

36、te, when the WDT overflows, it is usually RST pin will reset the output of high pulse. Reset pulse duration for the 98 × Tosc, and Tosc = 1/Fosc (crystal oscillation frequency).In order to optimize the work WDT must be at the right time code WDT reset periodically to prevent the WDT overflow.89

37、 s51 SCM interrupt system is introduced.1. interrupt: the execution of a program, allowing external or internal events through hardware interrupt execution, make its steering for handling internal events in the interrupt service routine to;After finishing the interrupt service program, the CPU to co

38、ntinue the original interrupted process, this process is called the interrupt.2. interrupt source: external and internal events can generate interrupts.89 s51 has five interrupt source:(1) INT0: external interrupt 0 request, low level effectively.Through P3.2 input pin.(2) the INT1: external interru

39、pt request 1, low level effectively.Through P3.3 input pin.(3) T0 timer/counter 0 overflow interrupt request.(4) TI: timer/counter 1 overflow interrupt request.(5) the TXD/RXD: serial port interrupt request.When the serial port in the completion of a frame of data sent or received, then request the

40、interrupt.Every interrupt source corresponds to an interrupt request flags, they set up in the special function registers TCON and SCON.When the interrupt request interrupt source, the corresponding marks have TCON and SCON respectively the corresponding latches.3. 89 s51 interrupt system has the fo

41、llowing four special function register:(1) the timer control register TCON (6);(2) serial port control register SCON (2);(3) IE interruption allows register;(4) interrupt priority register IP.Among them, the TCON and SCON part is only used to interrupt control.By you of any of the above special func

42、tion register for operation, such as setting or reset all sorts of interrupt control functions can be realized.翻譯單片機(jī)AT89S51的概述AT89S51是美國(guó)ATMEL公司生產(chǎn)的低功耗，高性能CMOS 8位單片機(jī)，片內(nèi)含4k bytes的可系統(tǒng)編程的Flash只讀程序存儲(chǔ)器，器件采用ATMEL公司的高密度、非易失性存儲(chǔ)技術(shù)生產(chǎn)，兼容標(biāo)準(zhǔn)8051指令系統(tǒng)及引腳。它集Flash程序存儲(chǔ)器既可在線編程（ISP)也可用傳統(tǒng)方法進(jìn)行編程及通用8位微處理器于單片芯片中，ATMEL公司的功能強(qiáng)大

43、，低價(jià)位AT89S51單片機(jī)可為您提供許多高性價(jià)比的應(yīng)用場(chǎng)介，可靈活應(yīng)用于各種控制領(lǐng)域。主要性能參數(shù)：·與MCS-51 產(chǎn)品指令系統(tǒng)完全兼容·4k字節(jié)在線系統(tǒng)編程(ISP) Flash閃速存儲(chǔ)器·1000次擦寫(xiě)周期·4.0-5.5V的工作電壓范圍·全靜態(tài)工作模式：0Hz-33MHz·三級(jí)程序加密鎖·128×8字節(jié)內(nèi)部RAM·32個(gè)可編程I/O口線·2個(gè)16位定時(shí)/計(jì)數(shù)器·6個(gè)中斷源·全雙工串行UART通道·低功耗空閑和掉電模式·中斷可從空閑模式喚醒系統(tǒng)&#

44、183;看門狗(WDT)及雙數(shù)據(jù)指針·掉電標(biāo)識(shí)和快速編程特性·靈活的在線系統(tǒng)編程(ISP一字節(jié)或頁(yè)寫(xiě)模式)功能特性概述：AT89S51提供以下標(biāo)準(zhǔn)功能：4k字節(jié)Flash閃速存儲(chǔ)器，128字節(jié)內(nèi)部RAM， 32個(gè)I/O口線，看門狗（WDT），兩個(gè)數(shù)據(jù)指針，兩個(gè)16位定時(shí)/計(jì)數(shù)器，一個(gè)5向量?jī)杉?jí)中斷結(jié)構(gòu)，一個(gè)全雙工串行通信口，片內(nèi)振蕩器及時(shí)鐘電路。同時(shí)，AT89S51可降至0Hz的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式?？臻e方式停止CPU的工作，但允許RAM，定時(shí)/計(jì)數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器停止工作并禁止其它所有部件工作

45、直到下一個(gè)硬件復(fù)位。引腳功能說(shuō)明：·Vcc： 電源電壓·GND：地·P0口：P0口是一組8位漏極開(kāi)路型雙向I/O口，也即地址/數(shù)據(jù)總線復(fù)用口。作為輸出口用時(shí)，每位能驅(qū)動(dòng)8個(gè)TTL邏輯門電路，對(duì)端口寫(xiě)1可作為高阻抗輸入端用。在訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器或程序存儲(chǔ)器時(shí)，這組口線分時(shí)轉(zhuǎn)換地址(低8位)和數(shù)據(jù)總線復(fù)用，在訪問(wèn)期間激活內(nèi)部上拉電阻。在Flash編程時(shí)，P0 口接收指令字節(jié)，而在程序校驗(yàn)時(shí)，輸出指令字節(jié)，校驗(yàn)時(shí)，要求外接上拉電阻。·P1口：P1是一個(gè)帶內(nèi)部上拉電阻的8位雙向I/O口，P1的輸出緩沖級(jí)可驅(qū)動(dòng)(吸收或輸出電流)4個(gè)TTL邏輯門電路。對(duì)端口寫(xiě)1，通

46、過(guò)內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口。作輸入口使用時(shí)，囚為內(nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流(In)。Flash編程和程序校驗(yàn)期間 P 1接收低8位地址。·P2口：P2是一個(gè)帶有內(nèi)部上拉電阻的8位雙向I/O口，P2的輸出緩沖級(jí)可驅(qū)動(dòng)(吸收或輸出電流)4個(gè)TTL邏輯門電路。對(duì)端口寫(xiě)1，通過(guò)內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口，作輸入口使用時(shí)，囚為內(nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流(In)。在訪問(wèn)外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器(例如執(zhí)行MOVX DPTR指令)時(shí)，P2口送出高 8位地址數(shù)據(jù)。在訪問(wèn)8位地址的外部

47、數(shù)據(jù)存儲(chǔ)器(如執(zhí)行MOVX Ri指令)時(shí)，P2口線卜的內(nèi)容(也即特殊功能寄存器（SFR)區(qū)中P2寄存器的內(nèi)容)，在整個(gè)訪問(wèn)期間不改變。Flash編程或校驗(yàn)時(shí)，P2亦接收高位地址和其它控制信號(hào)。·P3口：P3口是一組帶有內(nèi)部上拉電阻的8位雙向I/O口。P3口輸出緩沖級(jí)可驅(qū)動(dòng)(吸收或輸出電流)4個(gè)TTL邏輯門電路。對(duì)P3 口寫(xiě)入“1”時(shí)，它們被內(nèi)部上拉電阻拉高并可作為輸入端口。作輸入端時(shí)，被外部拉低的P3 口將用上拉電阻輸出電流（In）。 P3口除了作為一般的I/O口線外，更重要的用途是它的第二功能。P3 口還接收一些用于Flash閃速存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。P3口也可作為AT8

48、9C51的一些特殊功能口，如下表所示：管腳備選功能P3.0 RXD（串行輸入口）P3.1 TXD（串行輸出口）P3.2 （外部中斷0）P3.3 （外部中斷1）P3.4 T0（記時(shí)器0外部輸入）P3.5 T1（記時(shí)器1外部輸入）P3.6 （外部數(shù)據(jù)存儲(chǔ)器寫(xiě)選通）P3.7 （外部數(shù)據(jù)存儲(chǔ)器讀選通）·RST：復(fù)位輸入。當(dāng)振蕩器工作時(shí)，RST引腳出現(xiàn)兩個(gè)機(jī)器周期以上高電平將使單片機(jī)復(fù)位。WDT溢出將使該引腳輸出高電平，設(shè)置SFR AUXR 的DISRTO位（地址8EH）可打開(kāi)或關(guān)閉該功能。DISRTO位缺省為RESET輸出高電平打開(kāi)狀態(tài)。·ALE/PROG：當(dāng)訪問(wèn)外部程序存儲(chǔ)器或數(shù)

49、據(jù)存儲(chǔ)器時(shí)，ALE(地址鎖存允許)輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問(wèn)外部存儲(chǔ)器，ALE仍以時(shí)鐘振蕩頻率的1/6輸出固定的正脈沖信號(hào)，囚此它可對(duì)外輸出時(shí)鐘或用于定時(shí)目的。要注意的是：每當(dāng)訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過(guò)一個(gè)ALE脈沖。對(duì)Flash存儲(chǔ)器編程期間，該引腳還用于輸入編程脈沖（PROG）。如有必要，可通過(guò)對(duì)特殊功能寄存器（SFR)區(qū)中的8EH單元的D0位置位，可禁正ALE操作。該位置位后，只有一條MOVX和MOVC指令A(yù)LE才會(huì)被激活。此外，該引腳會(huì)被微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE無(wú)效。·PSEN：程序儲(chǔ)存允許(PSEN)輸出是外部程序存儲(chǔ)器的讀選通信號(hào)，當(dāng)

50、AT89S51由外部程序存儲(chǔ)器取指令(數(shù)據(jù))時(shí)，每個(gè)機(jī)器周期兩次PSEN有效，即輸出兩個(gè)脈沖。當(dāng)訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器，沒(méi)有兩次有效的PSEN信號(hào)。·EA/VPP：外部訪問(wèn)允許。欲使CPU僅訪問(wèn)外部程序存儲(chǔ)器(地址為0000H-FFFFH), EA端必須保持低電平(接地)。需注意的是：如果加密位LB1被編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)。如EA端為高電平(接Vcc端)，CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。Flash存儲(chǔ)器編程時(shí)，該引腳加上+12 V的編程電壓Vpp。·XTAL 1：振蕩器反相放大器及內(nèi)部時(shí)鐘發(fā)生器的輸入端。·XTAL2：振蕩器反相放大器的輸出端。·特殊功能寄存器：特殊功能寄存器的于片內(nèi)的空間分布的這些地址并沒(méi)有全部占用，沒(méi)有占用的地址亦不可使用，讀這些地址將得到一