課件計(jì)算機(jī)系統(tǒng)存儲(chǔ)

1、1計(jì)算機(jī)體系結(jié)構(gòu)內(nèi)存和外設(shè)2次課2Random-Access Memory (RAM)Key featuresRAM is packaged as a chip.Basic storage unit is a cell (one bit per cell).Multiple RAM chips form a memory.3Random-Access Memory (RAM)Static RAM (SRAM)Each cell stores bit with a six-transistor circuit.Retains value indefinitely, as long as it i

2、s kept powered.Relatively insensitive to disturbances such as electrical noise.Faster and more expensive than DRAM.4Random-Access Memory (RAM)5Random-Access Memory (RAM)Dynamic RAM (DRAM)Each cell stores bit with a capacitor and transistor.Value must be refreshed every 10-100 ms.Sensitive to disturb

3、ances.Slower and cheaper than SRAM.6SRAM vs DRAM summaryTran.Accessper bit timePersist?Sensitive?CostApplicationsSRAM61XYesNo100 xcache memoriesDRAM110XNoYes1XMain memories,frame buffers7Conventional DRAM organizationd x w DRAM:dw total bits organized as d supercells of size w bitscolsrows01230123in

4、ternal row buffer16 x 8 DRAM chipaddrdatasupercell(2,1)2 bits/8 bits/memorycontroller(to CPU)pins8Reading DRAM supercell (2,1)Step 1(a): Row access strobe (RAS) selects row 2.Step 1(b): Row 2 copied from DRAM array to row buffer.RAS=2colsrows01230123internal row buffer16 x 8 DRAM chiprow 2addrdata2/

5、8/memorycontroller9Reading DRAM supercell (2,1)Step 2(a): Column access strobe (CAS) selects column 1.Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU.supercell (2,1)colsrows01230123internal row buffer16 x 8 DRAM chipCAS=1addrdata2/8/memorycontrollerMemory

6、modulesDRAM chips are packaged in memory modulesdual inline memory module (DIMM)Common packages 168-pin, 204-pinMain memory can be aggregated by connecting multiple memory controllerWhen the controller receives an address A, the controller selects the module K that contains A11Memory modules （DIMM）:

7、 supercell (i,j)0317815162324326339404748555664-bit doubleword at main memory address Aaddr (row = i, col = j)data64 MB memory moduleconsisting ofeight 8Mx8 DRAMsMemorycontrollerbits0-7DRAM 7DRAM 0bits8-15bits16-23bits24-31bits32-39bits40-47bits48-55bits56-6364-bit doubleword to CPU chipBus Structur

8、e12Bus Structure (1)A bus is a collection of parallel wires carry address, data, and control signalsconnect to a bus interface on each moduleBuses are typically shared by multiple modules14Bus Structure Connecting CPU and memorymainmemoryI/O bridgebus interfaceALUregister fileCPU chipsystem busmemor

9、y busmemory controller15Memory read transaction1. CPU places address A on the memory bus ALUregister filebus interfaceA0Axmain memoryI/O bridge%eaxLoad operation: movl A, %eax16Memory read transaction2. Main memory reads A from the memory bus, retrieves word x, and places it on the bus. ALUregister

10、filebus interfaceX0Axmain memoryI/O bridge%eaxLoad operation: movl A, %eax17Memory read transaction3. CPU read word x from the bus and copies it into register %eax. ALUregister filebus interfaceX0Axmain memoryI/O bridge%eaxLoad operation: movl A, %eax18Memory write transaction ALUregister filebus in

11、terfaceA0Amain memoryI/O bridge%eaxStore operation: movl %eax, AY1. CPU place address A on bus. Main memory reads it and waits for the corresponding data to arrive.19Memory write transaction2. CPU places data word Y on the bus. ALUregister filebus interfaceY0Amain memoryI/O bridge%eaxStore operation

12、: movl %eax, AY20Memory write transaction3. Main memory read data word Y from the bus and stores it at address A ALUregister filebus interfaceY0Amain memoryI/O bridge%eaxStore operation: movl %eax, AY21Read the Block from the DIMM To access data in the address A in a form AxxxAxxx0Aymain memoryI/Obr

13、idgebus interfaceALUregister fileCPU chipsystem busmemory busCachememory22Read the Block from the DIMM Main memory reads A from the memory bus, retrieves 8 bytes y, and places it on the busy0Aymain memoryI/Obridgebus interfaceALUregister fileCPU chipsystem busmemory busCachememoryBus Structure (2)Bu

14、s arbitration protocoldecide which module may send or receive a message at any particular timeBus arbiter (optional)a circuit to choose which modules can use the busBroadcast link every module hears every messageA message contains a field: bus address whichIdentifies the intended recipientBus addres

15、sBus address space (physical address)Each module has its own bus address rangeBIOS is in charge of managing at booting timeEach module examines the bus address field For every message Ignores those not intended for it24Working modeAsynchronous the bus and the attached modules run uncoordinated clock

16、s Synchronousthe bus and all the attached modules are running with a common clock 25Split-transaction (asynchronous)Senderrequires exclusive use of the busplaces onthe address wiresa bus address of the destine module the data wiresthe reminder messageSignal the READY wire (one of the control wire) t

17、o alert the other modules26Split-transaction (asynchronous)The Receiverchecks the address lines after altered by READY Copies the datasingles ACKNOWLEDGE wireSendercheck the ACKNOWLEDGE wire releases the busIf synchronized, then READY & ACKNOWLEDGE are not needed, just check the address lines on eac

18、h clock cycleSource module releases the bus27Split-transaction (synchronous)Senderrequires exclusive use of the busplaces onthe address wiresa bus address of the destine module the data wiresthe reminder messagereleases the bus on the next cycleThe Receiverchecks the address lines on the every cycle

19、 Copies the data28Memory load example: LOAD 1742, R1Processor #2 = all bus modules: 1742, READ, 10229Memory load example: LOAD 1742, R1Memory1 recognizes the address is within its rangeBy examining just a few high-order address bits30Memory load example: LOAD 1742, R1Memory1 acknowledges and process

20、or2 releases the busMemory1 performs the internal operation to get the valuevalue all bus modules: 102, value32Memory load example: LOAD 1742, R1Processor2 is waiting for this resultjust copies the data on the bus to its register R133Memory load example: LOAD 1742, R1Processor2 acknowledges Memory1

21、releases the bus34Memory load example: LOAD 1742, R1Processor2 acknowledges and memory1 releases the bus3536Enhanced DRAMsAll enhanced DRAMs are built around the conventional DRAM coreFast page mode DRAM (FPM DRAM)Access contents of row with RAS, CAS, CAS, CAS, CAS instead of (RAS,CAS), (RAS,CAS), (

22、RAS,CAS), (RAS,CAS).37Enhanced DRAMsExtended data out DRAM (EDO DRAM)Enhanced FPM DRAM with more closely spaced CAS signals.Synchronous DRAM (SDRAM)Driven with rising clock edge instead of asynchronous control signalsClock is electronic signals as the followingClock38Enhanced DRAMsDouble data-rate s

23、ynchronous DRAM (DDR SDRAM)Enhancement of SDRAM that uses both clock edges as control signalsDDR, DDR2, and DDR3Rambus DRAM(RDRAM)Video RAM (VRAM)Like FPM DRAM, but output is produced by shifting row bufferDual ported (allows concurrent reads and writes)39Nonvolatile memoriesDRAM and SRAM are volati

24、le memoriesLose information if powered off.Nonvolatile memories retain value even if powered offGeneric name is read-only memory (ROM).Misleading because some ROMs can be read and modified.40Types of ROMsProgrammable ROM (PROM)Write onceErasable programmable ROM (EPROM)Erase by ultraviolet lightWrit

25、e by a special deviceAbout 1000 timesElectrically erasable PROM (EEPROM)Reprogramming in-place on printed circuit cards Flash memoryBased on EEPROM41Nonvolatile memoriesFirmwareProgram stored in a ROMBIOS (basic input/output system)Boot time codea small set of primitive input and output functionsgra

26、phics cards, disk controllersTranslate I/O (input/output) requests from the CPUWhats inside a disk drive?SpindleArmActuatorPlattersElectronics(including a processor and memory!)SCSIconnectorImage courtesy of Seagate Technology43Disk geometryDisks consist of platters, each with two surfaces.surface 0

27、surface 1surface 2surface 3surface 4surface 5spindleplatter 0platter 1platter 244Disk geometryEach surface consists of concentric rings called tracks.Each track consists of sectors separated by gaps.spindlesurfacetrackstrack ksectorsgaps45Disk geometry (muliple-platter view) Aligned tracks form a cy

28、linder.surface 0surface 1surface 2surface 3surface 4surface 5cylinder kspindleplatter 0platter 1platter 246Disk capacityCapacitymaximum number of bits that can be storedVendors express capacity in units of gigabytes (GB), where 1 GB = 109. Capacity is determined by these technology factors:Recording

29、 density (bits/in): number of bits that can be squeezed into a 1 inch segment of a track.Track density (tracks/in): number of tracks that can be squeezed into a 1 inch radial segment.Areal density (bits/in2): product of recording and track density.47Disk capacityOld fashioned disks Each track has th

30、e same number of sectors Modern disks partition tracks into disjoint subsets called recording zonesEach track in a zone has the same number of sectors, determined by the circumference of innermost trackEach zone has a different number of sectors/track48 Computing disk capacityCapacity = (# bytes/sec

31、tor) x (avg. # sectors/track) x (# tracks/surface) x (# surfaces/platter) x (# platters/disk)Example:512 bytes/sector300 sectors/track (on average)20,000 tracks/surface2 surfaces/platter5 platters/diskCapacity = 512 x 300 x 20000 x 2 x 5 = 30,720,000,000 = 30.72 GB 49Disk operation (single-platter v

32、iew)By moving radially, the arm can position the read/write head over any track.spindleThe disk surface spins at a fixedrotational rateThe read/write headis attached to the end of the arm and flies over the disk surface ona thin cushion of air.50Disk operation (multi-platter view)armread/write heads

33、 move in unisonfrom cylinder to cylinderspindleTracks divided into sectorsDisk Structure - top view of single platterSurface organized into tracksDisk AccessHead in position above a trackDisk AccessRotation is counter-clockwiseDisk Access ReadAbout to read blue sectorDisk Access ReadAfter BLUE readA

34、fter reading blue sectorDisk Access ReadAfter BLUE readRed request scheduled nextDisk Access SeekAfter BLUE readSeek for REDSeek to reds trackDisk Access Rotational LatencyAfter BLUE readSeek for REDRotational latencyWait for red sector to rotate aroundDisk Access ReadAfter BLUE readSeek for REDRota

35、tional latencyAfter RED readComplete read of redDisk Access Service Time ComponentsAfter BLUE readSeek for REDRotational latencyAfter RED readData transferSeekRotational latencyData transfer61Disk access timeAverage time to access some target sector approximated byTaccess = Tavg seek + Tavg rotation

36、 + Tavg transfer The average seek timeTime to position heads over cylinder containing target sectorThe time to move the head over 1/3 of the diskTypical Tavg seek = 8 msDisk access timeA typical modern 400 gigabyte diskHas 16,383 cylinders, or about 24 Mbytes per cylinderWould have 8 two-sided platt

37、ers and thus 16 read/write headsWould be 24/16 = 1.5 MB per trackWhen rotating at 7200 revolutions per minuteThe bits will go by a head at 1201.5=180 MB/s62Disk access timeBits read from a disk encounter two potential transfer rate limitsThe rate at which bits spin under the disk heads on their way

38、to a bufferThe rate at which the I/O channel or I/O bus can transfer the contents of the buffer to the computer63Disk access timeThe Integrated Device Electronics (IDE) bus66MB/s is a common numberThe Serial ATA 3 bus 3GB/s With the IDE bus The electronics would be the bottleneck at 66MB/sWith a Ser

39、ial ATA 3 bus The mechanics would be the bottleneck at 180MB/s64Disk access timeFor IDE, read a 4KB block chosen at random takesaverage seek time + average rotation latency + transmission of 4 kilobytes = 8 + 4.17 + (4 / (66 1024) 1000 ms= 8 + 4.17 + 0.06 ms= 12.23 msThe throughput for reading rando

40、mly-chosen 4k blocks one by one is:= 1000/12.23 4 KB/s = 327 KB/s65Disk access timeFor SATA 3, read a 4KB block chosen at random takesaverage seek time + average rotation latency + transmission of 4 kilobytes = 8 + 4.17 + (4 / (180 1024) 1000 ms= 8 + 4.17 + 0.02 ms= 12.19 msThe throughput for readin

41、g randomly-chosen sectors one by one is:= 1000/12.19 4 KB/s = 328 KB/s6667Disk access time exampleImportant pointsAccess time dominated by seek time and rotational latencyFirst bit in a sector is the most expensive, the rest are freeSRAM access time is about 1.5 nsDRAM is about 40 nsDisk is about 30

42、0,000 times slower than SRAM Disk is about 12,500 times slower then DRAM68Logical disk blocksModern disks present a simpler abstract view of the complex sector geometry:The set of available sectors is modeled as a sequence of b-sized logical blocks (0, 1, 2, .)Mapping between logical blocks and actu

43、al (physical) sectorsMaintained by hardware/firmware device called disk controllerConverts requests for logical blocks into (surface, track, sector) triples.69I/O bridgebus interfaceALUregister fileCPU chipsystem busdisk controllerdiskI/O busHost BusAdaptorSCSI/SATADisk driveLogical block numbsurfac

44、e, track, sector70Formatted disk capacityAllows controller to set aside spare cylinders for each zoneAccounts for the difference in “formatted capacity” and “maximum capacity”71mainmemoryI/O bridgebus interfaceALUregister fileCPU chipsystem busmemory busdisk controllergraphicsadapterUSBcontrollermou

45、sekeyboardmonitordiskI/O busExpansion slots forother devices suchas network adaptersHost BusAdaptorSCSI/SATAPeripheral Component Interconnect(PCI)solid stat diskDisk drive60MB/s(2.0)600MB/s(30.)SupportMultipledrivesSupport one drive72Memory-mapped I/OI/O PortA reserved address in the address space E

46、ach device is associated with (or mapped to)One or more ports when it is attached to the busA port is assigned to a control register or a buffer in the deviceProvide a uniform interface to bus modulesThe device controller/adaptor translates the bus address to the associated register or buffer intern

47、allyMemory mapped I/O73ProcessorPhysical address (System bus address)MemoryDiskKeyboardInternally translate the ddress to th register or the bufferUse LOAD and STORE instructions to operate the I/O portsJust like access memoryKeyboard ControllerKeyboard Controller Has 2 RegistersData register: save

48、the code of the hit keyState register with 2 bits:Interrupt enable: is the CPU allow keyboard to interrupt it?Ready bit: is the character in data register new?74KeyboardWhat happens when a user depresses a key ?Keyboard ControllerSaves the value of the key in the data registerSet the Ready bitInterr

49、upts the CPU if the interrupt bit is on7576InterruptI/O devices notifies the processor an external event happened by interrupt controller The CPU checks whether there are interrupts at the end of every instruction cycle stops what it is currently working on if yes jumps to the corresponding interrup

50、t handler77Keyboard controller sets interruptLocal/IO BusMemoryNetworkadapterSerial ATAcontrollerVideoadapterDisplayNetworkProcessorInterruptcontrollerIDEcontrollerUSB controllerKeyboardcontrollerKeyboardMousePrinterdiskCDROMThe Keyboard Interrupt HandlerTests the Ready Bit of the status register of

51、 the keyboard controller and clears itCopies the key stroke from the data register of the keyboard controller to a buffer owned by the keyboard driver immediatelyNotifies the keyboard driver to be active78The Keyboard Driver An operating system routineDoing some complex processing Convert the keystr

52、oke value in buffer into ASCII Inactive again79Why interrupt CPU may checks the ready bit periodicallyToo Frequently May waste processor cyclesSince often there will be no input availableToo Infrequently A long time before a device receives attentionUnresponsive and bad interactive experienceUsers s

53、econd key may overwrite the previous one8081DMADirect memory access A device performs a read or write bus transaction on its own, without any involvement of the CPUThe transfer of data is known as a DMA transferDMAbus addresscontrol register 120 command 121 sector_number 122 memory_address 123 count

54、 124 controlR0 0 R1 11742; R2 3328; R3 512; R4 1;STORE R0, 120/set WRITESTORE R1, 121/set sector numberSTORE R2, 122/set starting memory addressSTORE R3, 123/set byte countSTORE R4, 124/start disk controller running82DMA example83BIOSMemoryDiskProcessor 1101256-5113072-4095121-124Processor #1 = all

55、bus modules: 120, WRITE, 0Disk acknowledge and write the value 0 to its control registerProcessor #1 = all bus modules: 121, WRITE, 11742Processor #1 = all bus modules: 122, WRITE, 3328Processor #1 = all bus modules: 123, WRITE, 256Processor #1 = all bus modules: 124, WRITE, 1102Processor 2DMA examp

56、le84BIOSMemoryDiskProcessor 1101256-5113072-4095121-124Disk = all bus modules: 3328, WRITE, data11742Memory acknowledge and save data11742Disk = all bus modules: 3329, WRITE, data11743. (loop)Disk = all bus modules: 3839, WRITE, data12253102Processor 2DMA example85BIOSMemoryDiskProcessor 1101256-511

57、3072-4095121-124When transferring is finished, disk controller interrupts the processorJust like keyboard controller does when press a keyProcessor will enter interrupt handler next cycleNow the processor knows that the DMA is done102Processor 286Solid State Disk (SSD)Solid state disk (SSD) is a sto

58、rage technology, based on flash memorySSD package plugs into a standard disk slot on the I/O bus (typically USB or SATA)Flash translation layer = disk controllerSolid State Disk (SSD)Pages: 512KB to 4KB, Blocks: 32 to 128 pagesData read/written in units of pages. Page can be written only after its block has been erasedA block wears out after 100,000 repeated writes.Flash translation layerI/O busPage 0Page 1Page P-1Block 0Page 0Page 1Page P-1Block B-1