電子表單元電路匯編

1、第四章 數(shù)字(shz)系統(tǒng)設(shè)計(jì)數(shù)字(shz)電子時(shí)鐘單元電路分頻器；延時(shí)電路；微分電路；同步計(jì)數(shù)器；消抖電路共二十頁分頻器用途(yngt)：計(jì)數(shù)器即是簡(jiǎn)易分頻器D0D1D2Clk輸出(shch)頻率公式：共二十頁延遲(ynch)電路用途(yngt)：產(chǎn)生n個(gè)CP的相位延時(shí)CPDINDCPQ#QDCPQ#QQ1Q0共二十頁延遲(ynch)與微分電路時(shí)序(sh x)圖：CPDINQ0Q1共二十頁- *LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.AL

2、L;-*ENTITY dly1 isPORT( CP,DIN: INSTD_LOGIC; Q1: OUTSTD_LOGIC);END dly1;-*ARCHITECTURE a OF dly1 ISSIGNAL Q0 STD_LOGIC;BEGINPROCESS (CP)BEGINIF CPevent AND CP=1 THEN Q0 = Din;Q1 = Q0;END IF;END PROCESS;END a;共二十頁微分電路用途：將寬脈沖轉(zhuǎn)換為一個(gè)(y )CP周期的脈沖CPDINDCPQ#QDCPQ#QDOUTQ0Q1共二十頁延遲(ynch)與微分電路時(shí)序(sh x)圖：CPDINQ0Q1

3、DOUT共二十頁LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;-*ENTITY dly1 isPORT( CP,DIN: INSTD_LOGIC; DOUT: OUTSTD_LOGIC);END dly1;-*ARCHITECTURE a OF dly1 ISSIGNAL Q0,Q1 STD_LOGIC;BEGINPROCESS (CP)BEGINIF CPevent AND CP=1 THEN Q0 = Din;Q1 = Q0;END

4、IF;END PROCESS;DOUT = Q1 AND NOT Q0;END a;共二十頁同步(tngb)計(jì)數(shù)器電路用途：消除(xioch)競(jìng)爭(zhēng)冒險(xiǎn)；消除(xioch)延時(shí)誤差CPINDCPQ#QDCPQ#QECCLKQ共二十頁Free_Counter : Block Signal Q: STD_LOGIC_VECTOR(24 DOWNTO 0);Signal DLY : STD_LOGIC;BeginPROCESS (CP)BeginIF CPEvent AND CP=1 thenDLY = Q(21);Q = Q+1;END IF;END PROCESS;SEC = Q(21) AND

5、NOT DLY;-about 1Hz End Block Free_Counter;共二十頁- 60進(jìn)制計(jì)數(shù)器-*LIBRARY IEEE;USE IEEE.STD_LOGIC_UNSIGNED.ALL;-*ENTITY COUNTER60 ISPORT(CP : IN STD_LOGIC;BIN: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);S : IN STD_LOGIC;CLR : IN STD_LOGIC;EC : IN STD_LOGIC;CY60 : OUT STD_LOGIC);END COUNTER60;共二十頁- 子文件(wnjin)定義代碼ARCHI

6、TECTURE a OF COUNTER60 ISSIGNAL Q : STD_LOGIC_VECTOR (5 DOWNTO 0) ;SIGNAL RST, DLY : STD_LOGIC;BEGINPROCESS (CP,RST)BEGINIF RST = 1 THENQ = 000000;ELSIF CPevent AND CP = 1 THENDLY = Q(5);IF EC = 1 THENQ = Q+1;END IF; END IF;END PROCESS;CY60 = NOT Q(5) AND DLY;RST = 1 WHEN Q=60 OR CLR=1 ELSE 0;BIN =

7、Q WHEN S = 1 ELSE 000000;END a;共二十頁同步(tngb)計(jì)數(shù)器電路（有進(jìn)位）CPDINECCLKQ微分器微分器CY共二十頁消抖電路(dinl)用途(yngt)：消除競(jìng)爭(zhēng)冒險(xiǎn)；消除抖動(dòng)共二十頁消抖電路(dinl)CPINDCPQ#QDCPQ#QSRQ#QDOUT共二十頁-*LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;-*ENTITY Debunce isPORT( test_S: OUT STD_LOGIC;

8、 CP: IN STD_LOGIC; Key : IN STD_LOGIC; DLY_OUT : OUT STD_LOGIC; DIF_OUT: OUT STD_LOGIC);END Debunce;-*ARCHITECTURE a OF Debunce IS共二十頁SIGNAL SAMPLE, DLY, NDLY, DIFF: STD_LOGIC;- Binary BEGINtest_S = SAMPLE; Free_Counter : Block- 計(jì)數(shù)器 & 產(chǎn)生掃描(somio)信號(hào) Signal Q: STD_LOGIC_VECTOR(14 DOWNTO 0);Signal D0 :

9、 STD_LOGIC;BeginPROCESS (CP)- 計(jì)數(shù)器計(jì)數(shù) BeginIF CPEvent AND CP=1 thenD0 = Q(4);Q = Q+1;END IF;END PROCESS;SAMPLE = Q(4) AND NOT D0;-產(chǎn)生125HZ脈沖? -SAMPLE = Q(1) AND NOT D0;END Block Free_Counter;共二十頁Debunce : Block- DebounceSIGNAL D0, D1, S, R : STD_LOGIC; BeginProcess (CP)BeginIF CPEVENT AND CP=1 THENIF S

10、AMPLE = 1 THEND1 = D0; D0 = KEY;- Two Stage DelayS = D0 AND D1;- Generate S、RR = NOT D0 AND NOT D1;END IF;END IF;End Process;DLY = R NOR NDLY;- Debounce O/PNDLY =S NOR DLY;DLY_OUT = DLY;End Block Debunce;共二十頁Differential : Block-DifferentialSignal D1,D0 : STD_LOGIC;BEGINProcess (CP)BeginIF CPEVENT A

11、ND CP=1 THEND1 = D0; D0 = DLY;- Two State DelayEND IF;End Process;DIFF = D0 AND NOT D1;- DifferentialEND Block Differential;DIF_OUT = DIFF;- Differential O/PEND a;共二十頁內(nèi)容摘要第四章 數(shù)字系統(tǒng)設(shè)計(jì)。SIGNAL Q0 STD_LOGIC。Q1 = Q0。END a。用途：將寬脈沖轉(zhuǎn)換(zhunhun)為一個(gè)CP周期的脈沖。SIGNAL Q0,Q1 STD_LOGIC。ENTITY COUNTER60 IS。DLY = Q(5)。test_S = S