PrimeTime時(shí)序分析流程和方法培訓(xùn)講學(xué)

1、Good is good, but better carries it.精益求精，善益求善。PrimeTime時(shí)序分析流程和方法-PrimeTime時(shí)序分析流程和方法PrimeTime是Synopsys的一個(gè)單點(diǎn)的全芯片、門級靜態(tài)時(shí)序分析器。它能分析大規(guī)模、同步、數(shù)字ASICS的時(shí)序。PrimeTime工作在設(shè)計(jì)的門級層次，并且和Synopsys其它工具整合得很緊密。,m8F0u)D;|$l(G!Z*n9基本特點(diǎn)和功能：DICDER,f5e&D6s3I(?時(shí)序檢查方面：80n8y8H9z3g#P5u!?數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,V

2、CS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL建立和保持時(shí)序的檢查（Setupandholdchecks）+h)b.P6v/Ak3!Z1B(Q數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,

3、DPLL重新覆蓋和去除檢查（Recoveryandremovalchecks）+i1z4I6O%YDigitalICDesignersforum時(shí)鐘脈沖寬度檢查(Clockpulsewidthchecks)DigitalICDesignersforum#F3H(Fy#z#m(e5.時(shí)鐘門鎖檢查(Clock-gatingchecks)(8V$WJ$3O6E設(shè)計(jì)檢查方面：%.VC6v;|*/VDICDER沒有時(shí)鐘端的寄存器&e9i98a$&k!j;E(a2F#i沒有時(shí)序約束的結(jié)束點(diǎn)（endpoint）9E!j4V6K(T:v(q數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處

4、理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL主從時(shí)鐘分離（Master-slaveclockseparation）;l3Z-C8)z(D,n(_5c數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRA

5、M,SRAM,IIR,FIR,DPLL有多哥時(shí)鐘的寄存器g)W2i+J7h,D(G.X*e對層次敏感的時(shí)鐘（Level-sensitiveclocking）-xK$d:A.m(_+H.1DigitalICDesignersforum組合電路的反饋環(huán)（Combinationalfeedbackloops）DigitalICDesignersforum*6(I:o#F:x+|q設(shè)計(jì)規(guī)則檢查，包括最大電容(maximumcapacitance)、最大傳輸時(shí)間(maximumtransition)和最大扇出(maximumfanout)*7-/W;K%_%K4Dp9e)2PrimeTime時(shí)序分析流程

6、和方法：05Q*i6X6qT在時(shí)序分析之前需要做的步驟：4N,D3n9J3?DigitalICDesignersforum1、建立設(shè)計(jì)環(huán)境3s6h;n#pV(LJf-nDigitalICDesignersforum-建立搜索路徑（searchpath）和鏈接路徑（linkpath）數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL7K/*N.a/

7、P%E:W!e-讀入設(shè)計(jì)和庫數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL$V+o&d,i.C#+T)o-鏈接頂層設(shè)計(jì)數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,

8、primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL3W7Cb4U-建立運(yùn)作條件、連線負(fù)載模型、端口負(fù)載、驅(qū)動和傳輸時(shí)間a:Q!j8)k5.R0j/b2、說明時(shí)序聲明（約束）DigitalICDesignersforum-#J;K.|3c*E9D5Y;L-定義時(shí)鐘周期、波形、不確定性(uncertainty)和滯后時(shí)間(latency)DigitalICDesignersforum;Nq/(B!f3L9E#w-說明輸入、輸出端口的延時(shí)a/6Y-9a;k%s+S3、說明時(shí)序例外情況（timingexceptions）(j(D,B)zN-多周期路徑（multicyclepa

9、ths）數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL&!Q!z/J4&hC-不合法路徑(falsepaths)(H6i(Vq;J;K-n2-說明最大和最小延時(shí)、路徑分割（pathsegmentation）和失效?。╠isabledarcs）/Kr.D(s(,c-j4、進(jìn)行分析和生成報(bào)告$q%g.5m;F:u9D9h數(shù)字,集成電路,IC,FA

10、Q,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL-檢查時(shí)序數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL9t+Y56

11、T88vV*-生成約束報(bào)告數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL9e-m!_sd4R-生成路徑時(shí)序報(bào)告數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,prim

12、etime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL*G%O2.x6D(j7l,H2#Cv!q8Z開始數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL5Cx5h3t!z:H)T9Nq先建立目錄并將PrimeTime本身所帶的一個(gè)例子拷到新建的目錄下，在下面的內(nèi)容中將要用到這個(gè)例子。數(shù)字,集成電路,IC,FAQ,Designcom

13、piler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL4H8H0k+cSmkdirprimetime$q)s/3V?&LDICDERcdprimetime數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,

14、FIFO,SDRAM,SRAM,IIR,FIR,DPLL7P%ae,m7q.?xcpr$SYNOPSYS/doc/pt/tutorial.&?&B*H%X,a1bcdtutorial;.j%W%P;r61|,DigitalICDesignersforum確認(rèn)目錄中有以下這些文件：,O8TX/G!u!-AM2910.dbThedesign.dbforthetop-levelofthedesign9e-A-O$8d:g;G(BB&CONTROL.dbThedesign.dbfortheCONTROLblock#.nV4R-z4M)GDICDERREGCNT.dbThedesign.dbforthe

15、REGCNT0&4M1Ng&E0MUPC.dbThedesign.dbfortheUPCblock-D(U6A$F%S_:l8t6Z+MY.dataTheStampdatafilefortheYblock5qu+y-zK;數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLY.modTheStampmodelfilefortheYblock+s4C

16、3i,?7X6b-Q7v數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLY_lib.dbThelibrary.dbfortheY5o9b#C%_/b&tp3$r%rSTACK_lib.dbThelibrary.dbfortheSTACKblock數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,N

17、C,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL)E(y2t(Q+c5x7h.f*lpt_lib.dbThetechnologylibrary.dbDigitalICDesignersforum;?8U+&N+cx0_8Fstack.qtm.ptThequicktimingmodelscriptforthestackblock$U:F$o,g,S./o%L4r/p:m數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾

18、波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLoptimize.dcshThedc_shelloptimizationscriptDigitalICDesignersforum.C8w.J!F5_6x.Gtiming.dcshAnexampleDCshelltimingscriptfortranslationDigitalICDesignersforum6P*J2S7P1w6+3tutorial.ptThecompl

19、etePrimeTimetutorialscriptforyour數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL6G00)I7y:ureference.,z:b,G7L)H*B(rDICDER(Y2c,?0U4C數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,m

20、odelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL例子是一個(gè)AM2910微處理器，如圖所示模塊圖。9|)c6Z#S(R1BC5PDigitalICDesignersforumattachment=141DICDER;D-0l6+h!x$E1h)T1m#M8t9F5VM8I運(yùn)行PrimeTime：!u,V6tH8Q4i;|&數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix

21、,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLpt_shellDICDER9A,(b5D/m2C#Q:G5y7T0s)nDigitalICDesignersforum定義搜索路徑和鏈接路徑：N+x,q.U0o%H*,pt_shellsetsearch_path“.”數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,prim

22、etime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLk:|4u#z)V;r&X0pPt_shellsetlink_path“*pt_lib.dbSTACK_lib.dbY_lib.db”z.Z6n;:D1+D)T9P1%*pt_lib.dbSTACK_lib.dbY_lib.db:R&M+_*fi*Z/e數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,

23、IIR,FIR,DPLL;r7v?6N+.e5D;o-|8F4|$e讀入設(shè)計(jì)：8m#t5p2Q.y080s6x:PrimeTime支持以下設(shè)計(jì)格式：!A,E%S%We#數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL.Synopsysdatabasefiles(.db)(Usetheread_dbcommand)&*N/X(F;Y%I.Veri

24、lognetlistfiles(Usetheread_verilogcommand)DigitalICDesignersforum-A&5t$D2B)m.ElectronicDesignInterchangeFormat(EDIF)netlistfiles(Usetheread_edifcommand.)7t-K+%r8D9k_H3I)M(M.VHDLnetlistfiles(Usetheread_vhdlcommand.)DigitalICDesignersforumW.s4Ku;g%j:S2_讀入AM2910的頂層設(shè)計(jì)文件：數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信

25、號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL&%a6T7E;N:U,n%jpt_shellread_dbAM2910.dbr4o$?.g5F/p#V:Loadingdbfile/u/joe/primetime/tutorial/AM2910.db數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,

26、verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL1-a7b2V3w8x17_*3TN(?.f!數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLDigitalICDesignersforum4m;a+J1I*?:p鏈接設(shè)計(jì)：$Q3a8h!.j;j)J!?p

27、t_shelllink_designAM29107DB:,U71E-e數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLLoadingdbfile/u/joe/primetime/tutorial/pt_lib.db數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,m

28、odelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL5|3_!z:qP9GlLoadingdbfile/u/joe/primetime/tutorial/STACK_lib.dbM*l2j3E4Uk%t1?.bLoadingdbfile/u/joe/primetime/tutorial/Y_lib.dbDICDER7+dB6n:GY1cLinkingdesignAM2010.1i3Q)w%F!m.I8tLoadingdbfile/u/joe/primetime/tutorial

29、/STACK.db數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLH!i$YL1E.數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDR

30、AM,SRAM,IIR,FIR,DPLL+L1E#R24M*Tr#MDesignsusedtolinkAM2910:#f%$N2_6/F/CONTROL,REGCNT,STACK,UPC,Y;_!K$C:u5V)gLibrariesusedtolinkAM2910:5s;t6#l.cDigitalICDesignersforumSTACK_lib,Y_lib,pt_lib45i/_!8R:3s95i*r數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL

31、,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLDesignAM2910wassuccessfullylinkedL3_8S3e3x9k9p+6eT;X)?60M4o2S,V%Q/E%v;JM2J+_h+Q-Pp$Q%b9數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL顯示當(dāng)前已載入的

32、設(shè)計(jì)：數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL.l4IO4|0u(6E.v3?pt_shelllist_designs6w)|$e.X2E/c;_5jZ數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,

33、VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL得到當(dāng)前載入單元的信息：1R-a$n$1G8XR9v6w1Cpt_shellreport_cell)c)j/ON2d&C&y數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL/G:r+H,d;d&g編譯一個(gè)標(biāo)記模型（StampMod

34、el）：);Z*K0B+G7m8J數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL標(biāo)記模型是一個(gè)諸如像DSP或RAMS那樣復(fù)雜模塊的靜態(tài)時(shí)序模型。1x(L(h3o+(g/+n#o數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,ver

35、ilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL標(biāo)記模型與.lib模型共存，而不能代替它們。(W2f,P(j0.N,N)x-建立標(biāo)記模型是用在晶體管層次的設(shè)計(jì)上，在這個(gè)層次上沒有門級網(wǎng)表。3n*r2F%*i1z0W2j:x數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR

36、,DPLL-標(biāo)記模型語言是一種源代碼語言，被編譯成Synopsys的.db文件格式，可以被PrimeTime或DesignCompiler使用。數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL;A-?9W-XJ.w2X-P-標(biāo)記模型包含引腳到引腳的時(shí)序弧、建立和保持時(shí)間數(shù)據(jù)、模式信息、引腳的電容和驅(qū)動能力等等。標(biāo)記模型還能保存屬性（面積等等）。

37、$r-D-y2H/qe6d1D2gB數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL-三態(tài)輸出、鎖存器和內(nèi)部生成的時(shí)鐘都可以被建模。DigitalICDesignersforum,e56d-z&Q1+:E一個(gè)標(biāo)記模型包括兩種源代碼文件格式：%U(g,E8K3.d數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,D

38、SP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL-.mod文件&U5z(A0eL*v數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL僅包含引腳到引腳的弧的描述（沒有延時(shí)數(shù)據(jù)）。

39、$D5y$i*r2C.6-.data文件4U1d4G,M7,R#NqDigitalICDesignersforum包含.mod文件中每條弧的延時(shí)數(shù)據(jù)。DICDER9f!-Wc-sw標(biāo)記模型可以有多個(gè).data文件來描述不同運(yùn)作條件下的時(shí)序。DigitalICDesignersforum(_)!c/o66mo!lV兩種文件格式都需要編譯成一個(gè).db模型。:G!5I;(y9D0T#&F7q#nh0數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,S

40、TA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL編譯AM2910中Y模塊的標(biāo)記模型（標(biāo)記源代碼文件是Y.mod和Y.data）：#Xo8Lr,S:l數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLpt_shellcompile_stamp_model-model_fileY.mod;FR+Q&m

41、)r數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL-data_fileY.data-outputY數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,

42、FIFO,SDRAM,SRAM,IIR,FIR,DPLL;7R3m0#U0r.t)7MWrotemodellibrarycoreto./Y_lib.dbh,y)y8T(c,H:B8_DICDERWrotemodelto./Y.db數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL/R5-YO)%J&W2QPrimeTime生成兩個(gè).db文件：數(shù)字

43、,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL2X1b4n;Y$R+t*o*w)v)N;J%yY_lib.db：一個(gè)庫文件，包含一個(gè)單元(cell)。這個(gè)單元叫做核(core)。7m(l/D#R9e!vY.db：一個(gè)設(shè)計(jì)文件，引用Y_lib.db中的單元核。9v64E$i-s.H數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號

44、處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL3U6H7B%Z,H(XDigitalICDesignersforum3hb2D&x5a+818b6c編譯一個(gè)快速時(shí)序模型(QuickTimingModel)：數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,ST

45、A,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLH5r&F&g$Z-Z4e可以為設(shè)計(jì)中還沒有完成的模塊建立一個(gè)快速時(shí)序模型，以使得完整的時(shí)序分析能夠進(jìn)行。通常的情形是：7f&S%W2R*數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL-模塊的HDL代碼還沒有完成時(shí)數(shù)字,集成電路,IC,FAQ,De

46、signcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL5jl9z*J)V2s-為了劃分設(shè)計(jì)，在評估階段為實(shí)際設(shè)計(jì)進(jìn)行時(shí)序預(yù)測、約束估計(jì)時(shí),z#V93Q5Z(?#7-模塊的標(biāo)記模型還沒有完成時(shí)數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,

47、IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL8j!N%S$(F1k一個(gè)快速時(shí)序模型是一組PrimeTime命令，而不是一種語言。為了方便和文檔化可以將它們寫在一個(gè)腳本文件中，然后保存為.db的格式。在PrimeTime和DesignCompile中快速時(shí)序模型很有用處。&z,t3h$v)L+?)H數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primeti

48、me,FIFO,SDRAM,SRAM,IIR,FIR,DPLL還可以將快速時(shí)序模型保存為標(biāo)記模型，這是開始一個(gè)復(fù)雜標(biāo)記模型的一種便利的方法。DICDER&l)l:(r:S&e/r$A3G例子中STACK模塊的快速時(shí)序模型腳本文件是stack.qtm.pt，建立這個(gè)模型：數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL0L1O6S*p#P1R0h

49、:_/Ppt_shellsource-echostack.qtm.pt$O.X*|$L1J+|3A&.(y:aR(i)FX9r9p8O5pt_shellreport_qtm_model;|.l0N*H+k0|9(w,DigitalICDesignersforum.DigitalICDesignersforum0g0T!R5e9gpt_shellsave_qtm_model-outputSTACK-formatdb+c&I(t;MF;RG8I;y:nWrotemodellibrarycoreto./STACK_lib.db8t!F2BI.aC%tDICDERWrotemodelto./STACK

50、.db2!O8m+y2E/O8H#A*P,S97J9rj$i8ci&O)g9J:c)a;Y,q1G1AC#r數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL進(jìn)行時(shí)序分析DICDER%gj5u4D?&d5b.f(B5配置運(yùn)作環(huán)境/i9?v6*%aE*t數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS

51、,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL!x5n*l$H9N;P4L讀入并鏈接AM2910設(shè)計(jì)：8rM,l5Y3M7數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLpt_shell

52、setsearch_path.+d1w58I,n:?*b4n數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLpt_shellsetlink_path*pt_lib.dbSTACK_lib.dbY_lib.db1u%Q9C9i2|1a(J2qpt_shellread_dbAM2910.db6F2.C9_8v3d)數(shù)字,集成電路,IC,FAQ,De

53、signcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLpt_shelllink_designAM2910(|;A9e*&e%&B:F,w數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FI

54、FO,SDRAM,SRAM,IIR,FIR,DPLL鏈接了AM2910會導(dǎo)致其它已經(jīng)鏈接的設(shè)計(jì)變?yōu)椴绘溄拥臓顟B(tài)。在內(nèi)存里只允許有一個(gè)鏈接的設(shè)計(jì)。當(dāng)一個(gè)設(shè)計(jì)不鏈接，所有時(shí)序信息將被去除，并會出現(xiàn)警告，這和DesignCompiler不同。如果需要保存所標(biāo)注的信息，可以在鏈接一個(gè)新的設(shè)計(jì)之前用write_script命令。如果以后重新鏈接這個(gè)設(shè)計(jì)，只要運(yùn)行這個(gè)腳本就可以了。數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,p

55、rimetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL#s-r5t1M!%O$x:X9z7T%U*c0t建立運(yùn)作條件和連線負(fù)載模型：56V;X2e0p7I4D2w&_+Jk數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLLPrimeTime在生成建立時(shí)序報(bào)告(setuptimingreports)時(shí)使用最大(Maximum)運(yùn)

56、作條件和連線負(fù)載模型；在生成保持時(shí)序報(bào)告(holdtimingreports)時(shí)使用最小(Minimum)運(yùn)作條件和連線負(fù)載模型。DigitalICDesignersforum8w4I(o-Mpt_shellset_operating_conditions-librarypt_lib-minBCCOM-maxWCCOMDICDER0s:x8KM9O3T1O%wpt_shellset_wire_load_81n-s$hQm9|-Qpt_shellset_wire_load_model-librarypt_lib-name05x05-min2?6an+|4l2H25pt_shellset_wire

57、_load_model-librarypt_lib-name20 x20max數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL8P3dB/i;#*-p如果運(yùn)作條件在兩個(gè)不同的庫中，用set_min_library命令來在最大庫和最小庫中建立聯(lián)系。:p?2I&o6k8N6&A:G得到一張庫的列表：數(shù)字,集成電路,IC,FAQ,Designcomp

58、iler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL&S9B*m8E0Xnpt_shelllist_librariesDICDER:w/s%:A:%i0I2Z9JLibraryRegistry:DigitalICDesignersforum3N8w;o9Y7MS7STACK_lib/home/gray/primetime/tutorial/0ic(x8H&s1SSTACK_lib.db:STACK

59、_lib&*i*8D;w%w#Y_lib/home/gray/primetime/tutorial/Y_lib.db:Y_lib2N;5D!J-a4BDICDER*pt_lib/home/gray/primetime/tutorial/6v/V*v4l1t.G26iDigitalICDesignersforumpt_lib.db:pt_lib數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,

60、SDRAM,SRAM,IIR,FIR,DPLL(F2r/_+F*F8z得到一個(gè)庫的詳細(xì)信息：6U!|5y9T$Apt_shellreport_libpt_lib8q,i15%k+g&)rDICDER4J3uc3m56x0Pu4_數(shù)字,集成電路,IC,FAQ,Designcompiler,數(shù)字信號處理,濾波器,DSP,VCS,NC,coverage,覆蓋率,modelsim,unix,c,verilog,hdl,VHDL,IP,STA,vera,驗(yàn)證,primetime,FIFO,SDRAM,SRAM,IIR,FIR,DPLL基本聲明：數(shù)字,集成電路,IC,FAQ,Designcompiler,