課件：數(shù)字邏輯2-3

1、Time delay and power consumptionInterface design for IC packageChapter 2 Digital circuit design for logic unitDynamic model of CMOSAny device has its input and output capacitorsDynamic model of CMOSDynamic behaviorWhen state changed, capacitors must be charged or uncharged through a resistor ! Time

2、delay rely on capacitance for charge or uncharge ,and capacitance of a unit decided by its logic area.Time delay in logic deviceDynamic power consumptionPower consumption is mainly happened when the state is changed!Parallel design for logic unit Parallel design may be get less time delay and power

3、consumptionDesign for 4X INV Use 2 large transistors:Logic area is 8 Driving ability is 4XDesign for 4X NAND Design for NX Device Only inverter may be designed for NX unit; Any NX driving ability should be provided by an inverter; Output unit of an IC package is much larger than the unit in chip. De

4、sign for NX Device SSI and MSI design: Output unit take the main area; Logic design for 1X unit may be not important. LSI and VLSI design: 1X unit take the main area; Each unit may be an IP core for system design; Their logic design become important.Interface design for Analog device Hold the voltage margin and current limitFor NAND2 in Table 3-3: VOHmin= 3.84 V IOHmax=4 mAThen RI 3.84 R 3.84/4 = 0.96 kInterface design for Analog device Fig 3-54 74AC Device : VOLmax = 0.37 V IOLmax= 10 mAInterface design for Analog device Schmitt-Trigger inputOutput changes after inp