AltiumDesigner規(guī)則設(shè)置三例

1、SEED SEED #覆銅高級(jí)連接方式如過孔全連接，焊盤熱焊盤連接；頂層GND網(wǎng)絡(luò)全連接，其他層熱焊盤連接線寬0.3mm在ADPCB環(huán)境下，DesignRulesPlanePolygonConnectstyle,點(diǎn)中PolygonConnectstyle,右鍵點(diǎn)擊newrule新建一個(gè)規(guī)則點(diǎn)擊新建的規(guī)則既選中該規(guī)則，在name框中改變里面的內(nèi)容即可修改該規(guī)則的名稱，默認(rèn)是PolygonConnect_l，現(xiàn)我們修改為GND-Via，選項(xiàng)WhereTheFristObjectMatches選Advanced(Query)，F(xiàn)ullQuery輸入IsVia(大小寫隨意)，ConnectStyle選

2、DirectConnect,其他默認(rèn)設(shè)置，點(diǎn)擊下邊的priorities把GND-Via規(guī)則優(yōu)先級(jí)置最高，(1為最高，2次之)如下圖：一仝D已wijiRu皚w：+摯Electrical+Ruutingi-oSMT+Maski|Plane一JPowerPl門已ConnectStyleFlaneCunnect一JPowerPlaneClearanceFlaneClearancePolygunConnectSUrlPolvgonConnect+歹Testpuint+Manufacturing+c=z：HiqhSpeed+靈Fl-ac已ii已門t+SignalIntegrityNamejpLilygo

3、nConnectExportRules.ImportRules.Wh已址The三已匚口1匚1Obje匚tF-latches(FullQuery匚onstraintsSEED #SEED ConnectStyleDi已匚tCun門已匚:tVPriuritvEnabledfJameScopeAttributesGND-ViaIsVia-AllStyle-DirectConnect122PolHgunCunnectAll-AllStyle-ReliefConnectWidth=10milAngle=90#Entrie回到PCB設(shè)計(jì)環(huán)境下進(jìn)行覆銅，覆銅網(wǎng)絡(luò)選GND,覆好銅以后對(duì)于網(wǎng)絡(luò)為GND的Via(

4、過孔)將為全覆銅的連接，而非默認(rèn)的reliefconnect方式(熱焊盤方式)，由于規(guī)則是對(duì)過孔的全連接覆銅，所以對(duì)于焊盤的覆銅是熱焊盤方式連接方式，見下圖(左)：NINPortl1Pnrtl117P&rtl15Portli.z(cPcrtiaV；cccE17Portl如果想過孔和焊盤多用熱焊盤方式，那在FullQuery修改為IsViaorIspad，更新下剛才的覆銅，地焊盤也全連接了，如上圖(右)同樣也可以FullQuery為Ispad，InNet(GND),InNet(GND)AndOnLayer(TopLayer),InComponent(U1),InComponent(UI)ORIn

5、Component(U2)ORInComponent(U3),innetclass(Power)等等I.InNet(GND)對(duì)于網(wǎng)絡(luò)名為GND的網(wǎng)絡(luò)進(jìn)行覆銅連接，覆銅連接規(guī)則采用InNet(GND)的覆銅連接規(guī)則，注：InNet(X),X為PCB中的網(wǎng)絡(luò)名，ConnectStyle可全連接或熱焊盤或無連接方式；熱焊盤方式還可設(shè)置2，4連接，45度，90度和連接線寬，下面的也類同；2.InNet(GND)AndOnLayer(TopLayer)，對(duì)于位于TopLayer層的GND網(wǎng)絡(luò)進(jìn)行的覆銅米用該覆銅連接規(guī)則，OnLayer(X),X為層名，層名稱修改可通過DesignLayerStackMa

6、nager,雙擊層名稱修改。；3.InComponent(U1)，對(duì)于元件U1的覆銅采用該覆銅連接規(guī)則，U1上有個(gè)X網(wǎng)絡(luò)，同時(shí)覆銅的網(wǎng)絡(luò)也為X，這樣改規(guī)則才有效果，例如U1上有個(gè)管腳連接到GND網(wǎng)絡(luò)，同時(shí)覆銅網(wǎng)絡(luò)選GND，此時(shí)改規(guī)則才有效果；否則等于沒有這個(gè)規(guī)則，與不建立規(guī)則效果一樣；4.InComponent(U1)ORInComponent(U2)ORInComponent(U3)對(duì)于元件U1,U2,U3米用該覆銅連接規(guī)貝U,即U1,U2,U3多采用改覆銅連接規(guī)則，關(guān)系是OR,而非AND;innetclass(Power),Power類網(wǎng)絡(luò)的覆銅連接方式規(guī)則，DesignClasses創(chuàng)建

7、一個(gè)規(guī)則類，類的方式有多種，網(wǎng)絡(luò)類，元件類,網(wǎng)絡(luò)類指向PCB中的網(wǎng)絡(luò)名，層類指向PCB中的元件(焊位)，層類指向PCB中的層；例：innetclass(Power)，在netclasses(網(wǎng)絡(luò)類)下新建一個(gè)規(guī)則(newrule)，同樣是右鍵增加，并改名為Power，選中這個(gè)網(wǎng)絡(luò)類規(guī)，添加左邊的的網(wǎng)絡(luò)到右邊去，比如添加GND,VCCINT,VCC3.3,VCC1.2,VCCA,GNDA等這樣在多個(gè)多個(gè)網(wǎng)絡(luò)的不同覆銅就不用分另U建立GND，VCCINT，VCC3.3，VCC1.2，VCCA，GNDA的覆銅連接規(guī)則，自需要建立一個(gè)網(wǎng)絡(luò)類覆銅連接規(guī)則即可，在覆銅的時(shí)候覆銅網(wǎng)絡(luò)連接到相應(yīng)的網(wǎng)絡(luò)即可；注

8、意：所有上面的規(guī)則多要設(shè)置相應(yīng)的優(yōu)先級(jí)和新建規(guī)則，新建規(guī)則的優(yōu)先級(jí)設(shè)為高，默認(rèn)規(guī)則的優(yōu)先級(jí)最低，其他優(yōu)先級(jí)看實(shí)際排列。所有選項(xiàng)選WhereTheFristObjectMatches選Advanced(Query)，F(xiàn)ullQuery輸入相應(yīng)的數(shù)據(jù)命令，對(duì)于相對(duì)簡單的類似只是網(wǎng)絡(luò)和層的覆銅連接InNet(GND)AndOnLayer(TopLayer)頂層地網(wǎng)絡(luò)的覆銅連接方式，可選擇TheFristObjectMatchesNetandLayer，在里面的下拉框中選擇相應(yīng)的Net和Layer后。FullQuery框軟件會(huì)執(zhí)行填充數(shù)據(jù)，完成后ApplyOK回到PCB中(FullQuery框中語法錯(cuò)

9、誤，軟件會(huì)提示錯(cuò)誤，而填入一個(gè)不存在的層或網(wǎng)絡(luò)名則不會(huì))，再在PCB進(jìn)行覆銅選擇相應(yīng)的覆銅網(wǎng)絡(luò)即可，覆銅間距默認(rèn)是lOmil,如需特殊間距則需修改間距規(guī)則；SEED 高級(jí)間距規(guī)則比如覆銅間距16mil,其他安全間距8mil,過孔到過孔間距100mil,焊盤到焊盤間距100mil,焊盤到過孔間距100mil,頂層地覆銅0.8mm,頂層VCC3.3與VCC1.8覆銅間距0.5mm等AltiumDesigner的間距規(guī)則默認(rèn)為一個(gè)10mil間距，沒有區(qū)分焊盤到焊盤，過孔到過孔，走線到覆銅等的間距，想要高級(jí)規(guī)則，必須自己新建。在PCB設(shè)計(jì)環(huán)境下DesignRulesElectricalClearanc

10、e,同樣右鍵新建一個(gè)間距規(guī)則并重命名為Poly,WhereTheFirstObjectMatches選Adcanced(Query),FullQuery輸入inpolygon,Constraints把默認(rèn)的10mil修改為20mil,優(yōu)先級(jí)Poly比默認(rèn)的的Clearance的10mil高，這2個(gè)間距規(guī)則共同構(gòu)成覆銅間距為20mil,其他間距例如走線到走線，走線到焊盤過孔間距為10mil的規(guī)則，如下圖：-DesignRules日著ElectricalClearanciNewRule.脊Clear;-摯Short-Circ&elete心Comm已門t沁計(jì)Sh0rt(Report.-摯Un-Flo

11、ute護(hù)UnFl0ExportRules.薩Un-LunniImpurtRules.+!FloutingWhereTheFirstObjectMatchesFullQueryAllConstraintsFullQueryinpolygonSEED #SEED #ditRulePrioritiesDifferentNetsUnlyMinimumClearance20milPriurityEnabl已dNam已ScopeAttributesPolyinpulyqun-.AllClearanc已=20mil|2味ClearanceAll-AllClearance=10milRuleTnpe:匚I已a(bǔ)

12、ranceSEED #SEED #下2圖是過孔覆銅全連接viaconnect,默認(rèn)安全間距clearance8mil,覆銅間距16mil規(guī)則的覆銅，inpolygon是所有的覆銅，如果想要其他覆銅間距，則需要在新建覆銅規(guī)則，比如VCC3.3覆銅0.5mm,VCC1.8覆銅間距0.6mm,其他覆銅0.4mm；優(yōu)先級(jí)16mil的最低；覆一片銅到VCC3.3網(wǎng)絡(luò)同時(shí)起名該覆銅為VCC3.3-ALL;覆一片銅到VCC1.8網(wǎng)絡(luò)同時(shí)起名該覆銅為VCC1.8-ALL;同樣要興建間距規(guī)則，見下面第3-6張圖：SEED #SEED 一3DesignRules-計(jì)Electrical-摯ClearancePol

13、yComment摯Clearance一已門F；ul已富：-摯Electrical-挈Clearance君Poly君Clearance-挈Short-Circuit摯ShortCircuit-計(jì)Un-FloutedNet護(hù)UnRoutedNet護(hù)IJn-ConnectedFin+/SFlnuting+J-&SMT+Mask白Plane-IFd甲冋Plane匚門門已匚tStyI已FlaneConnect一IPowerPlaneClearanceFlaneCI已日呂門匚e一Polygon匚匚i門門已匚tStylef-Jameviaconnecl：CummentWhereTheFirstObjectM

14、atchesFullQueryisviaWhereTheFirstObjectMatchesWhereTheSeccindObjectMatchesFullQueryinpolygonvidCuririecl：WhereTheSecondCbje匚t陰日t匚卜庁All(J)Net(J)NetClassLayer(J)NetandLayerOAdvanced(Query)FullQueryAllAII(j-Net(j-NetClassOLayerNetandLayerOAdva忙已d(Query)FullQueryAllCunstraintsQueryBuilderPulHgonConnect+

15、鄉(xiāng)Testpuint+Mdnufdcturing+c=dHighSp已已H+Placement+lllji.-SignalIntegrityDifferentN已也UnhrMinimumClearance1BmilConstraints：ConnectStyleDi已匚tConnect|vSEED SEED #已signRules-護(hù)Electrical-摯Cle-dranceNameVCC1.0-ALLCommentUniqueIDTVSKOSVCC1.0-ALL摯VCC3.3-ALL摯OtherPoly摯Clearance-挈Short-Circuit摯ShortCircuit-摯Un-R

16、outedNet摯UnFloutedNet針Un-ConnectedPinWhereTheFirstObjectMatchesFullQueryIiil-Jan已匚IP丄爭g:ni：1VCC18-ALL1：iDifferentNetsUnhrMinimumClearanceO.E；mmHdh已r已TheSecundObjectMatchesConstraintsFullQueryAll-+3DesignRules-摯Electrical-摯ClearanceNameVCC3.3-ALLCommentUniqueIDGDOTGJISEED WhereTheFirstObjectMatchesFu

17、llQueryInNaitiedPolygon(1VCC3.3-ALL1)ConstraintsFullQueryAllVCC3.3-ALL計(jì)OtherPoly計(jì)Clearance-摯Short-Circuit警ShortCircuit-計(jì)Un-RoutedNet縈UnRoutedNet計(jì)Un-ConnectedPin+衛(wèi)Flouting+ISMT+Mask-PlaneDifferentNetsOnlyMinimumClearance0.5mmSEED SEED 一31DesignRules-挈Electrical-護(hù)ClearanceJ*VCC1.8-ALL君VCC3.3-ALL5*Othe

18、rPoly計(jì)Clearance-挈Short-Circuit護(hù)ShortCircuit-鬻Un-RoutedNet護(hù)UnRoutedNet護(hù)Un-ConnectedFin+Flnuting+J-&SMT+MaskNameUtherFuhr1L_CommentFullQueryinpijlygonDifferentNetsUnlyCunstr-aintsWhereTheFirstObj已匚tMatchesOMOr-JetFullQueryAll一2DesignRules-挈Electrical-挈ClearanceJ*VCC1.8-ALLf*VCC3.3-ALL錄OtherPolyClearan

19、ce-/Short-Circuit計(jì)ShortCircuit-摯Un-RoutedNet護(hù)UnRoutedNet計(jì)Un-ConnectedPin+Routing+汕T+Mask-PlaneDifferentNetsOnlyMinimumClearance0.254mmConstraintsSEED Narnevia-to-viaJComment:WhereTh已FirstObjectr-latch已呂FullQueryHXhEr已The5已匚ijiclObj已匚tMatch已FullQueryConstraintsDifferentNetsOnlyMinimumClearance2.54mm下

20、圖是過孔到過孔的間距規(guī)貝I,WhereTheFirstObjectMatches,WhereTheSecondObjectMatches的FullQuery,只有這2個(gè)參數(shù)一個(gè)是isvia,另一個(gè)是ispad即可；如果一個(gè)是ispad另一個(gè)是isvia，那就是過孔到焊盤的間距；如果一個(gè)是ispad另一個(gè)是ispad，那就是焊盤到焊盤的間距；隨后填入具體的間距即可，WhereTheSecondObjectMatches默認(rèn)是ALL，修改他就是第一個(gè)和第二個(gè)間距規(guī)則，IsVia和ALL就是Via到其他的間距規(guī)則，IsVia和IsVia就是過孔到過孔的間距規(guī)則；一3DesignRules-摯Elec

21、trical-摯Clearancevid-to-vid挈holef*L1-GND_ALLJ*L4-GND_ALL君L3Jrack_.WANAf*Poly-L45*Poly-L3挈Pol-r-L1護(hù)Clearance-摯Short-Circuit挈ShortCircuit-挈Un-FluutedNet鬻LlnFlnutedNet挈Un-ConnectedPin+Floutingi-fcSMT+Mask-Plane一PowerPlaneConnectStyleFl日門已Cun門已匚t一Fuw已PlaneClearanc已PlaneClearance-Pulvgon匚門門已匚tSUrIe|Polyg

22、on_Relief_BOTTOMPolygon_Relief_T0PPolygon_ReliefPolygurLCunnect+初幻Testpoint+Manufacturing+KHighSpeed過孔到過孔間距沒有到2.54mm的在線DRC檢查出來綠色顯示；注：設(shè)置小間距管腳間距：一些FPGA芯片等很多焊盤間距多達(dá)到了0.2mm,默認(rèn)的lOmil(0.254mm)間距顯然是沖突的，上述問題可以通過HasFootprint(PQ208)或IsPadandInComponent(UI);(IsPadandInComponent(JP4)or(IsPadandInComponent(JP3)Ha

23、sFootprint(PQ208),封裝為PQ208的兀件；sPadandInComponent(U1)，元件U1的管腳間的間距；上面2個(gè)規(guī)則只是管腳間距，叢上面拉出來的線的間距是其他的規(guī)則值，當(dāng)然不能太大；比如上面的PQ208焊盤0.3mm。焊盤間距0.2mm，布線0.2mm，那拉出來的線間距就是0.4mm。如果把布線間距設(shè)為0.5mm,1mm，要么綠色，要么拉不出來；(IsPadandInComponent(JP4)or(IsPadandInComponent(JP3)，元件JP3,JP4的間距規(guī)則；見下面3張圖：SEED SEED #一3DesignRules-摯Electrical-摯

24、Clearance護(hù)ClearanL：e_F,Lihr|gon挈Clearance_FPGA挈Clearance+挈Short-Circuit-摯Un-RoutedNet挈IJnRuutedfJet挈Un-ConnectedPin+FloutingS-fcSMT+Mask-Plane一PowerPlaneConnectStyleFlaneConnect一IPuA已PlaneClearanc已FlaneClearance一JPolygunConnectStylePolHgunCunnect+Testpoint+Manufacturing+wHighSpeed+Placement+SignalI門

25、t已grityNarneClear.ance_FF,G.ACommentWhereTh已SecondObjectMatchesCcmstraintsUniqueID|GYTVFullQueryIsPadandInCuinpunent(1U11：iFullQueryAllSEED #SEED #ConstraintsDifferentNetsOnly一3DesignRules-摯Electrical-摯Clearance鬻CledrdnL：e_FQ2LlE!挈Clear.3nce_F,Lihrgun護(hù)Clearance_FPGA計(jì)Clearance+摯Short-Circuit-摯Un-Fluu

26、tedNet鬻LlnFlnutedNet摯Un-ConnectedPin+Flouting由SMT+Mask白JPlane一IPowerPlaneConnectStyleFl日門已Cun門已匚t一JFuw已PlaneClearanc已PlaneClearance-Pulvgon匚門門已匚tSUrIePolygunCunnect+VTestpoint+Manufacturing+KHighSpeed+Placement+SignalIntegritySEED SEED #一工5D已-摯Electrical-挈Clearance護(hù)Clearance摯8milNameClearanceCumment

27、UniqueIDHFXAKJTMDifferentNetsOnlyMinimumClearance5mil(IsPadandInCuinpunent(1JP41)ori：IsPaclandInCutciponent.(1JP31)ori：IsPaclandInCuinpun已門匸i：丨u21：i：ior(IsPaclandInCuinpuiint.(1ip51)ori：IsPaclandInCuinpunent.(1ip21：i：iFullQu已叩WhereTheSecondObjectMatches0711FullQu已ryAllSEED 下圖是一個(gè)定位孔間距為3mm的間距規(guī)則：常用一個(gè)內(nèi)孔

28、=外孔的焊盤做定位孔。該孔不連接到任何網(wǎng)絡(luò)（不進(jìn)行電氣連接），只擰螺絲用我們?cè)赑CB上4個(gè)腳上放4個(gè)定位孔，不連接到任何網(wǎng)絡(luò)，焊盤名稱起為HOLE,內(nèi)孔=外孔大小；free-hole含義free不連接到任何網(wǎng)絡(luò)，Hole焊盤名稱；可以是free-0，free-1，free-2等等；SEED #SEED #-DesignRules-摯Electrical-計(jì)Cleararice護(hù)via-to-viarNamephul已匚I已日石門匚已CummentUniiphul已匚I已日石門匚已WhereTheFirstObjectMatchesFullQueryHasPad(1至匸已p-HOLE1：iFul

29、lQueryAllSEED #0夠Oo匚二IR2ConstraintsDifferentNetsUnlyMinimumClearance1nrimilF圖為一個(gè)在toplayer層覆銅名為5VANA的間距規(guī)則，當(dāng)然toplayer可以換成其他層，5VANA可以換成其他覆銅的名稱;SEED #SEED -2DesignRules-挈Electrical-計(jì)Clearance君top_.WANAI*VCC1.8-ALLf*VCC3.3-ALL護(hù)OtherPoly護(hù)Clearance-鬻Short-Circuit護(hù)ShortCircuit-護(hù)Un-RoutedNet計(jì)UnRoutedNet挈Un-C

30、onnectedFin+Flouting+&SMT+Mask白|Plane一PowerPlaneConnectStyleFlaneCun門已匚t一JPowerPlaneClearancePlane匚I已引日門匚呂-PolygunConnectStyleviaconnectPLilygunCLinnect+莎T已stpoint+Manufacturing+1二三:HighSpeed+Placement+SignalIntegrityNametop_5，lv,AN11CummentUniqueID|lDConstraintsWhereTheFirstObjectMatchesWhereThe5已匸

31、ondObje匚tF-lat匚h已呂FullQu已ryOnLayeri：1toplayer1：iA1FDIiil-LztiriedP1ygoni：15VAIJA1：iSEED F圖為DM到DP網(wǎng)絡(luò)間距為20mil的間距規(guī)則:SEED #-2lDesignRules-護(hù)Electrical-摯Clearance摯DP-DMf*Smil-挈Short-Circuit摯ShortCircuit-Un-RoutedNet計(jì)UnRoutedNet縈Un-ConnectedPin+左Routing+ISMT+Mask-PlanePowerPlaneConnectStylePlaneConnectPower

32、PlaneClearancePlaneClearancePolygonConnectStylePolygonConnect+*Testpoint+Manufacturing+琵HighSpeed+Placement+SignalIntegrityNameDP-DMCommentWhereTheFirstObjectMatchesIIj-NetCjNetClassOLayerJNetandLayerDM(_.)Advan匚已H(Query)WhereTheSeccindObjectMatchesConstraintsFullQueryIiil-Jet.i：1DM1：iFullQueryIiil-

33、J已匸i：1Dp1：iDifferentNetsUnivMinimumClearance20milSEED #SEED ConstraintsDifferentNets：0nlyMinimumClearance1BmilF圖為MSCLK1網(wǎng)絡(luò)到其他間距為16mil的間距規(guī)則一3DesignRules-摯Electrical-挈ClearanceJ*DP-DM挈netclass挈8mil-挈Short-Circuit挈ShortCircuit-護(hù)Un-RoutedNet護(hù)UnRoutedNet摯Un-ConnectedFin+Flouting卄&SMT+MaskEJ-tIPlane一JPower

34、PlaneCcm門已匚tStyleFlaneCunnect一JPowerPlaneClearanceFlaneCI已日日門匚已一PulygunConnectStyleFolygonCunnect+莎Testpuint+Manufacturing+c=：HighSpeed+Flac已I已門t+SignalI門t已gritySEED #SEED #SEED SEED 高級(jí)線寬規(guī)則設(shè)置GND網(wǎng)絡(luò)30mil,VCC網(wǎng)絡(luò)線寬20mil,布線時(shí)按TAB,TrackWidthMode選RulePreferred；)WalkaroundCunflicting匸Ibj已匚tOHugAndPushCunflict

35、ingObject0Cumpl已t已RoutingWidthConstraintsInteractiveRoutingUpticmsIIRestrictTo90/45FloutingConflictF；已sulutiun(*)NonePushConflictingObjectO.AutomaticallyTerminateFlouting0.AutomaticallvRemoveLuupsTraceWidthiscurrentlyconstrainedbytheruleWGNDtoaminimumuf1Umilandamaximumof1UUmil.IIHugExistingTracesly/

36、alkaroundModeViasUrleiscurr已門tlyconstrai門已Hbytheul已FluutingVias1.TheminimumandmaximumholesizesareUmiland14mil.TheminimumandmaximumdiametersareUmiland24mil.SmartConnectionPadExits0AllowDiagunalInteractiveRoutingWidth/ViaSizeSuurceskckWithModeRulePreferred_-ViaSizeModeRulePreferred一3DesignRules+挈Elect

37、rical-Flouting-WidthNameW_VCCCommentwVCCWGND0%WidthFloutingTupulugyRuutingTupulogvwRoutingPriorityhRoutingPriorityFloutingLasers：龍F(tuán)loutingLayers一FloutingCur門已氏：龍RuutingCurners：RoutingViaStyle衛(wèi)FluutingVias+Fanout匚untrul.DifferentialPairsFluuting/SDiffFairsFloutinga-fcSMT+Mask白；|Plane一PowerPlaneConnec

38、tSUjeFlaneCun門已匚tPniAiprPlanalaarnriLaWhereTheFirstObjectMatchesConstraintsIICharacteristicImpeda回LasersinlaverstackoMinWidth10milFullQueryInNet(VCC)AttributesonLayerLayerStackReferenceMinWidthPreferredSizeMa:-:WidthName10mil20mil10OrnilTopLayer10mil20mil1LiOmilBottomLayerI.01SEED SEED -13DesignFlules+摯Electrical-Flouting-SWidthW_VCCV/GNDWidth-龍F(tuán)loutingTopolugyZiFlLiutingTopLilLigy-FluutingFrioritvwRoutingPriority-/SFlnutingLayersFloutingLaHers-FloutingCornersZiFlouting匚匚i廣歸：:：-RoutingViaStyle.rtFloutingVias：+龍F(tuán)anout匚Lintr