MOS集成電路的基本制造工藝

半導(dǎo)體集成電路2022/10/25半導(dǎo)體2022-10-181上節(jié)課內(nèi)容要點(diǎn)雙極集成電路的基本工藝雙極集成電路中元件結(jié)構(gòu)2022/10/25上節(jié)課內(nèi)容要點(diǎn)雙極集成電路的基本工藝2022-10-182pn+n-epin+P-Sin+-BLCBESP+P+雙極集成電路的基本工藝2022/10/25pn+n-epin+P-Sin+-BLCBESP+P+雙極集3P-SiTepiCBEpn+n-epin+P-SiP+P+Sn+-BLTepiAA’TBL-uptepi-oxxmcxjc四層三結(jié)結(jié)構(gòu)的雙極晶體管雙極集成電路中元件結(jié)構(gòu)2022/10/25P-SiTepiCBEpn+n-epin+P-SiP+P+S4ECB2022/10/25ECB2022-10-185相關(guān)知識(shí)點(diǎn)隱埋層的作用、電隔離的概念、寄生晶體管2022/10/25相關(guān)知識(shí)點(diǎn)隱埋層的作用、電隔離的概念、寄生晶體管2022-16本節(jié)課內(nèi)容

MOS集成電路的工藝

P阱CMOS工藝

BiCMOS集成電路的工藝

N阱CMOS工藝雙阱CMOS工藝2022/10/25本節(jié)課內(nèi)容MOS集成電路的工藝P阱CMOS工藝7MOS晶體管的動(dòng)作

MOS晶體管實(shí)質(zhì)上是一種使電流時(shí)而流過，時(shí)而切斷的開關(guān)n+n+P型硅基板柵極（金屬）絕緣層（SiO2）半導(dǎo)體基板漏極源極N溝MOS晶體管的基本結(jié)構(gòu)源極(S)漏極(D)柵極(G)MOSFET的基本結(jié)構(gòu)2022/10/25MOS晶體管的動(dòng)作MOS晶體管實(shí)質(zhì)上是一種使n+n+P型8siliconsubstratesourcedraingateoxideoxidetopnitridemetalconnectiontosourcemetalconnectiontogatemetalconnectiontodrainpolysilicongatedopedsiliconfieldoxidegateoxideMOS晶體管的立體結(jié)構(gòu)2022/10/25siliconsubstratesourcedrainga9在硅襯底上制作MOS晶體管siliconsubstrate2022/10/25在硅襯底上制作MOS晶體管siliconsubstrate10siliconsubstrateoxidefieldoxide2022/10/25siliconsubstrateoxidefieldox11siliconsubstrateoxidephotoresist2022/10/25siliconsubstrateoxidephotores12ShadowonphotoresistphotoresistExposedareaofphotoresistChromeplatedglassmaskUltravioletLightsiliconsubstrateoxide2022/10/25Shadowonphotoresistphotoresi13非感光區(qū)域siliconsubstrate感光區(qū)域oxidephotoresist2022/10/25非感光區(qū)域siliconsubstrate感光區(qū)域oxid14Shadowonphotoresistsiliconsubstrateoxidephotoresistphotoresist顯影2022/10/25Shadowonphotoresistsilicons15siliconsubstrateoxideoxidesiliconsubstratephotoresist腐蝕2022/10/25siliconsubstrateoxideoxidesil16siliconsubstrateoxideoxidesiliconsubstratefieldoxide去膠2022/10/25siliconsubstrateoxideoxidesil17siliconsubstrateoxideoxidegateoxidethinoxidelayer2022/10/25siliconsubstrateoxideoxidegat18siliconsubstrateoxideoxidepolysilicongateoxide2022/10/25siliconsubstrateoxideoxidepol19siliconsubstrateoxideoxidegategateultra-thingateoxidepolysilicongate2022/10/25siliconsubstrateoxideoxidegat20siliconsubstrateoxideoxidegategatephotoresistScanningdirectionofionbeamimplantedionsinactiveregionoftransistorsImplantedionsinphotoresisttoberemovedduringresiststrip.sourcedrainionbeam2022/10/25siliconsubstrateoxideoxidegat21siliconsubstrateoxideoxidegategatesourcedraindopedsilicon2022/10/25siliconsubstrateoxideoxidegat22自對(duì)準(zhǔn)工藝在有源區(qū)上覆蓋一層薄氧化層淀積多晶硅，用多晶硅柵極版圖刻蝕多晶硅以多晶硅柵極圖形為掩膜板，刻蝕氧化膜離子注入2022/10/25自對(duì)準(zhǔn)工藝在有源區(qū)上覆蓋一層薄氧化層2022-10-1823siliconsubstratesourcedraingate2022/10/25siliconsubstratesourcedrainga24siliconsubstrategatecontactholesdrainsource2022/10/25siliconsubstrategatecontacth25siliconsubstrategatecontactholesdrainsource2022/10/25siliconsubstrategatecontacth26完整的簡(jiǎn)單MOS晶體管結(jié)構(gòu)siliconsubstratesourcedraingateoxideoxidetopnitridemetalconnectiontosourcemetalconnectiontogatemetalconnectiontodrainpolysilicongatedopedsiliconfieldoxidegateoxide2022/10/25完整的簡(jiǎn)單MOS晶體管結(jié)構(gòu)siliconsubstrate27CMOSFETP型sisubn+gateoxiden+gateoxideoxidep+p+2022/10/25CMOSFETP型sisubn+gateoxiden+28主要的CMOS工藝VDDP阱工藝N阱工藝雙阱工藝P-P+P+N+N+P+N+VSSVOUTVINVDDN-P+P+N+N+P+N+VSSVOUTVINVDDP-P+P+N+N+P+N+VSSVOUTVINN-SiP-SiN-I-SiN+-Si2022/10/25主要的CMOS工藝VDDP阱工藝N阱工藝雙阱工藝P-P+P+29掩膜1：P阱光刻P-wellP-well

N+

N+

P+

P+

N+

P+N-SiP2022/10/25掩膜1：P阱光刻P-wellP-wellN+N+30具體步驟如下：1．生長(zhǎng)二氧化硅（濕法氧化）：Si(固體)+2H2OSiO2（固體）+2H22022/10/25具體步驟如下：Si(固體)+2H2OSiO2（固體）31氧化2022/10/25氧化2022-10-18322．P阱光刻：涂膠腌膜對(duì)準(zhǔn)曝光光源顯影2022/10/252．P阱光刻：涂膠腌膜對(duì)準(zhǔn)曝光光源顯影2022-10-18332022/10/252022-10-1834硼摻雜（離子注入）刻蝕（等離子體刻蝕）去膠P+去除氧化膜P-well3．P阱摻雜：2022/10/25硼摻雜（離子注入）刻蝕（等離子體刻蝕）去膠P+去除氧化膜P-352022/10/252022-10-1836離子源高壓電源電流積分器離子束2022/10/25離子源高壓電流離子束2022-10-1837掩膜2：光刻有源區(qū)有源區(qū)：nMOS、PMOS

晶體管形成的區(qū)域P+N+N+P+N-SiP-wellP-wellP-well淀積氮化硅光刻有源區(qū)場(chǎng)區(qū)氧化去除有源區(qū)氮化硅及二氧化硅SiO2隔離島2022/10/25掩膜2：光刻有源區(qū)有源區(qū)：nMOS、PMOSP+N+N+38有源區(qū)depositednitridelayer有源區(qū)光刻板N型p型MOS制作區(qū)域(漏-柵-源)2022/10/25有源區(qū)deposited有源區(qū)光刻板2022-10-1839P-well1.淀積氮化硅：氧化膜生長(zhǎng)（濕法氧化）P-well氮化膜生長(zhǎng)P-well涂膠P-well對(duì)版曝光有源區(qū)光刻板2.光刻有源區(qū)：2022/10/25P-well1.淀積氮化硅：氧化膜生長(zhǎng)（濕法氧化）P-we40P-well顯影P-well氮化硅刻蝕去膠3.場(chǎng)區(qū)氧化：P-well場(chǎng)區(qū)氧化（濕法氧化）P-well去除氮化硅薄膜及有源區(qū)SiO22022/10/25P-well顯影P-well氮化硅刻蝕去膠3.場(chǎng)區(qū)氧化：P41掩膜3：光刻多晶硅P-well去除氮化硅薄膜及有源區(qū)SiO2P-wellP+N+N+P+N-SiP-well柵極氧化膜多晶硅柵極生長(zhǎng)柵極氧化膜淀積多晶硅光刻多晶硅2022/10/25掩膜3：光刻多晶硅P-well去除氮化硅薄膜及有源區(qū)Si42P-well生長(zhǎng)柵極氧化膜P-well淀積多晶硅P-well涂膠光刻多晶硅光刻板P-well多晶硅刻蝕2022/10/25P-well生長(zhǎng)柵極氧化膜P-well淀積多晶硅P-well43掩膜4

：P+區(qū)光刻

1、P+區(qū)光刻

2、離子注入B+，柵區(qū)有多晶硅做掩蔽，稱為硅柵自對(duì)準(zhǔn)工藝。

3、去膠P-wellP+N+N+P+N-SiP-wellP-wellP+P+2022/10/25掩膜4：P+區(qū)光刻1、P+區(qū)光刻P-wellP+44P-wellP+P-wellP+P+硼離子注入去膠2022/10/25P-wellP+P-wellP+P+硼離子注入去膠2022-45掩膜5

：N+區(qū)光刻

1、N+區(qū)光刻

2、離子注入P+，柵區(qū)有多晶硅做掩蔽，稱為硅柵自對(duì)準(zhǔn)工藝。

3、去膠P-wellP+N+N+P+N-SiP-wellP-wellP+P+N+N+2022/10/25掩膜5：N+區(qū)光刻1、N+區(qū)光刻P-wellP+46P-wellN+P-wellP+P+磷離子注入去膠P+P+N+N+2022/10/25P-wellN+P-wellP+P+磷離子注入去膠P+P+N47掩膜6

：光刻接觸孔1、淀積PSG.2、光刻接觸孔3、刻蝕接觸孔P-wellP+N+N+P+N-SiP-wellP-wellP+P+N+N+磷硅玻璃（PSG)2022/10/25掩膜6：光刻接觸孔1、淀積PSG.P-wellP+N+N48掩膜6

：光刻接觸孔P-wellP+P+N+N+淀積PSGP-wellP+P+N+N+光刻接觸孔P-wellP+P+N+N+刻蝕接觸孔P-wellP+P+N+N+去膠2022/10/25掩膜6：光刻接觸孔P-wellP+P+N+N+淀積PSG492022/10/252022-10-1850掩膜7

：光刻鋁線1、淀積鋁.2、光刻鋁3、去膠P-wellP-wellP+P+N+N+2022/10/25掩膜7：光刻鋁線1、淀積鋁.P-wellP-wellP+51P-wellP+P+N+N+鋁線PSG場(chǎng)氧柵極氧化膜P+區(qū)P-wellN-型硅極板多晶硅N+區(qū)2022/10/25P-wellP+P+N+N+鋁線PSG場(chǎng)氧柵極氧化膜P+區(qū)P52Example:Intel0.25micronProcess5metallayersTi/Al-Cu/Ti/TiNPolysilicondielectric2022/10/25Example:Intel0.25micronPro53InterconnectImpactonChip2022/10/25InterconnectImpactonChip20254掩膜8

：刻鈍化孔CircuitPADCHIP2022/10/25掩膜8：刻鈍化孔CircuitPADCHIP2022-1055雙阱標(biāo)準(zhǔn)CMOS工藝P+p-epipwellnwellp+n+gateoxideAl(Cu)tungstenSiO2SiO2TiSi2fieldoxide增加器件密度防止寄生晶體管效應(yīng)（閂鎖效應(yīng)）2022/10/25雙阱標(biāo)準(zhǔn)CMOS工藝P+p-epipwellnwellp56p-epiP阱n+STITiSi2STI深亞微米CMOS晶體管結(jié)構(gòu)STISTISTIN阱n-n+n-p+p-p+p-源/漏擴(kuò)展區(qū)淺槽隔離側(cè)墻多晶硅硅化物2022/10/25p-epiP阱n+STITiSi2STI深亞微米CMOS晶體57功耗驅(qū)動(dòng)能力CMOS雙極型Bi-CMOSBiCMOS集成電路工藝2022/10/25功耗驅(qū)動(dòng)能力CMOS雙極型Bi-CMOSBiCMOS集成電路58BiCMOS工藝分類以CMOS工藝為基礎(chǔ)的BiCMOS工藝以雙極工藝為基礎(chǔ)的BiCMOS工藝。2022/10/25BiCMOS工藝分類以CMOS工藝為基礎(chǔ)的BiCMOS工藝259以P阱CMOS工藝為基礎(chǔ)的BiCMOS工藝NPN晶體管電流增益?。患姌O的串聯(lián)電阻很大;NPN管C極只能接固定電位，從而限制了NPN管的使用2022/10/25以P阱CMOS工藝為基礎(chǔ)的BiCMOS工藝NPN晶體管電流增60以N阱CMOS工藝為基礎(chǔ)的BiCMOS工藝NPN具有較薄的基區(qū)，提高了其性能；N阱使得NPN管C極與襯底隔開，可根據(jù)電路需要接電位集電極串聯(lián)電阻還是太大，影響雙極器件的驅(qū)動(dòng)能力在現(xiàn)有N阱CMOS工藝上增加一塊掩膜板2022/10/25以N阱CMOS工藝為基礎(chǔ)的BiCMOS工藝NPN具有較薄的基61

以N阱CMOS工藝為基礎(chǔ)的改進(jìn)BiCMOS工藝使NPN管的集電極串聯(lián)電阻減小56倍；使CMOS器件的抗閂鎖性能大大提高2022/10/25以N阱CMOS工藝為基礎(chǔ)的改進(jìn)BiCMOS工藝使N62三、后部封裝（在另外廠房）（1）背面減薄（2）切片（3）粘片（4）壓焊：金絲球焊（5）切筋（6）整形（7）密封（8）沾錫：保證管腳的電學(xué)接觸（9）老化（10）成測(cè)（11）打印、包裝2022/10/25三、后部封裝（在另外廠房）2022-10-1863金絲劈加熱壓焊2022/10/25金絲劈加熱壓焊2022-10-1864三、后部封裝（在另外廠房）2022/10/25三、后部封裝（在另外廠房）2022-10-18652022/10/252022-10-1866作業(yè)：1.課本P14，1.2題2.下圖是NMOS晶體管的立體結(jié)構(gòu)圖，請(qǐng)標(biāo)出各區(qū)域名稱及摻雜類型，并畫出這個(gè)器件的版圖（包括接觸孔和金屬線）。3.名詞解釋：MOSNMOSPMOSCMOS場(chǎng)氧、有源區(qū)、硅柵自對(duì)準(zhǔn)工藝2022/10/25作業(yè)：1.課本P14，1.2題2.下圖是NMOS晶體管67半導(dǎo)體集成電路2022/10/25半導(dǎo)體2022-10-1868上節(jié)課內(nèi)容要點(diǎn)雙極集成電路的基本工藝雙極集成電路中元件結(jié)構(gòu)2022/10/25上節(jié)課內(nèi)容要點(diǎn)雙極集成電路的基本工藝2022-10-1869pn+n-epin+P-Sin+-BLCBESP+P+雙極集成電路的基本工藝2022/10/25pn+n-epin+P-Sin+-BLCBESP+P+雙極集70P-SiTepiCBEpn+n-epin+P-SiP+P+Sn+-BLTepiAA’TBL-uptepi-oxxmcxjc四層三結(jié)結(jié)構(gòu)的雙極晶體管雙極集成電路中元件結(jié)構(gòu)2022/10/25P-SiTepiCBEpn+n-epin+P-SiP+P+S71ECB2022/10/25ECB2022-10-1872相關(guān)知識(shí)點(diǎn)隱埋層的作用、電隔離的概念、寄生晶體管2022/10/25相關(guān)知識(shí)點(diǎn)隱埋層的作用、電隔離的概念、寄生晶體管2022-173本節(jié)課內(nèi)容

MOS集成電路的工藝

P阱CMOS工藝

BiCMOS集成電路的工藝

N阱CMOS工藝雙阱CMOS工藝2022/10/25本節(jié)課內(nèi)容MOS集成電路的工藝P阱CMOS工藝74MOS晶體管的動(dòng)作

MOS晶體管實(shí)質(zhì)上是一種使電流時(shí)而流過，時(shí)而切斷的開關(guān)n+n+P型硅基板柵極（金屬）絕緣層（SiO2）半導(dǎo)體基板漏極源極N溝MOS晶體管的基本結(jié)構(gòu)源極(S)漏極(D)柵極(G)MOSFET的基本結(jié)構(gòu)2022/10/25MOS晶體管的動(dòng)作MOS晶體管實(shí)質(zhì)上是一種使n+n+P型75siliconsubstratesourcedraingateoxideoxidetopnitridemetalconnectiontosourcemetalconnectiontogatemetalconnectiontodrainpolysilicongatedopedsiliconfieldoxidegateoxideMOS晶體管的立體結(jié)構(gòu)2022/10/25siliconsubstratesourcedrainga76在硅襯底上制作MOS晶體管siliconsubstrate2022/10/25在硅襯底上制作MOS晶體管siliconsubstrate77siliconsubstrateoxidefieldoxide2022/10/25siliconsubstrateoxidefieldox78siliconsubstrateoxidephotoresist2022/10/25siliconsubstrateoxidephotores79ShadowonphotoresistphotoresistExposedareaofphotoresistChromeplatedglassmaskUltravioletLightsiliconsubstrateoxide2022/10/25Shadowonphotoresistphotoresi80非感光區(qū)域siliconsubstrate感光區(qū)域oxidephotoresist2022/10/25非感光區(qū)域siliconsubstrate感光區(qū)域oxid81Shadowonphotoresistsiliconsubstrateoxidephotoresistphotoresist顯影2022/10/25Shadowonphotoresistsilicons82siliconsubstrateoxideoxidesiliconsubstratephotoresist腐蝕2022/10/25siliconsubstrateoxideoxidesil83siliconsubstrateoxideoxidesiliconsubstratefieldoxide去膠2022/10/25siliconsubstrateoxideoxidesil84siliconsubstrateoxideoxidegateoxidethinoxidelayer2022/10/25siliconsubstrateoxideoxidegat85siliconsubstrateoxideoxidepolysilicongateoxide2022/10/25siliconsubstrateoxideoxidepol86siliconsubstrateoxideoxidegategateultra-thingateoxidepolysilicongate2022/10/25siliconsubstrateoxideoxidegat87siliconsubstrateoxideoxidegategatephotoresistScanningdirectionofionbeamimplantedionsinactiveregionoftransistorsImplantedionsinphotoresisttoberemovedduringresiststrip.sourcedrainionbeam2022/10/25siliconsubstrateoxideoxidegat88siliconsubstrateoxideoxidegategatesourcedraindopedsilicon2022/10/25siliconsubstrateoxideoxidegat89自對(duì)準(zhǔn)工藝在有源區(qū)上覆蓋一層薄氧化層淀積多晶硅，用多晶硅柵極版圖刻蝕多晶硅以多晶硅柵極圖形為掩膜板，刻蝕氧化膜離子注入2022/10/25自對(duì)準(zhǔn)工藝在有源區(qū)上覆蓋一層薄氧化層2022-10-1890siliconsubstratesourcedraingate2022/10/25siliconsubstratesourcedrainga91siliconsubstrategatecontactholesdrainsource2022/10/25siliconsubstrategatecontacth92siliconsubstrategatecontactholesdrainsource2022/10/25siliconsubstrategatecontacth93完整的簡(jiǎn)單MOS晶體管結(jié)構(gòu)siliconsubstratesourcedraingateoxideoxidetopnitridemetalconnectiontosourcemetalconnectiontogatemetalconnectiontodrainpolysilicongatedopedsiliconfieldoxidegateoxide2022/10/25完整的簡(jiǎn)單MOS晶體管結(jié)構(gòu)siliconsubstrate94CMOSFETP型sisubn+gateoxiden+gateoxideoxidep+p+2022/10/25CMOSFETP型sisubn+gateoxiden+95主要的CMOS工藝VDDP阱工藝N阱工藝雙阱工藝P-P+P+N+N+P+N+VSSVOUTVINVDDN-P+P+N+N+P+N+VSSVOUTVINVDDP-P+P+N+N+P+N+VSSVOUTVINN-SiP-SiN-I-SiN+-Si2022/10/25主要的CMOS工藝VDDP阱工藝N阱工藝雙阱工藝P-P+P+96掩膜1：P阱光刻P-wellP-well

N+

N+

P+

P+

N+

P+N-SiP2022/10/25掩膜1：P阱光刻P-wellP-wellN+N+97具體步驟如下：1．生長(zhǎng)二氧化硅（濕法氧化）：Si(固體)+2H2OSiO2（固體）+2H22022/10/25具體步驟如下：Si(固體)+2H2OSiO2（固體）98氧化2022/10/25氧化2022-10-18992．P阱光刻：涂膠腌膜對(duì)準(zhǔn)曝光光源顯影2022/10/252．P阱光刻：涂膠腌膜對(duì)準(zhǔn)曝光光源顯影2022-10-181002022/10/252022-10-18101硼摻雜（離子注入）刻蝕（等離子體刻蝕）去膠P+去除氧化膜P-well3．P阱摻雜：2022/10/25硼摻雜（離子注入）刻蝕（等離子體刻蝕）去膠P+去除氧化膜P-1022022/10/252022-10-18103離子源高壓電源電流積分器離子束2022/10/25離子源高壓電流離子束2022-10-18104掩膜2：光刻有源區(qū)有源區(qū)：nMOS、PMOS

晶體管形成的區(qū)域P+N+N+P+N-SiP-wellP-wellP-well淀積氮化硅光刻有源區(qū)場(chǎng)區(qū)氧化去除有源區(qū)氮化硅及二氧化硅SiO2隔離島2022/10/25掩膜2：光刻有源區(qū)有源區(qū)：nMOS、PMOSP+N+N+105有源區(qū)depositednitridelayer有源區(qū)光刻板N型p型MOS制作區(qū)域(漏-柵-源)2022/10/25有源區(qū)deposited有源區(qū)光刻板2022-10-18106P-well1.淀積氮化硅：氧化膜生長(zhǎng)（濕法氧化）P-well氮化膜生長(zhǎng)P-well涂膠P-well對(duì)版曝光有源區(qū)光刻板2.光刻有源區(qū)：2022/10/25P-well1.淀積氮化硅：氧化膜生長(zhǎng)（濕法氧化）P-we107P-well顯影P-well氮化硅刻蝕去膠3.場(chǎng)區(qū)氧化：P-well場(chǎng)區(qū)氧化（濕法氧化）P-well去除氮化硅薄膜及有源區(qū)SiO22022/10/25P-well顯影P-well氮化硅刻蝕去膠3.場(chǎng)區(qū)氧化：P108掩膜3：光刻多晶硅P-well去除氮化硅薄膜及有源區(qū)SiO2P-wellP+N+N+P+N-SiP-well柵極氧化膜多晶硅柵極生長(zhǎng)柵極氧化膜淀積多晶硅光刻多晶硅2022/10/25掩膜3：光刻多晶硅P-well去除氮化硅薄膜及有源區(qū)Si109P-well生長(zhǎng)柵極氧化膜P-well淀積多晶硅P-well涂膠光刻多晶硅光刻板P-well多晶硅刻蝕2022/10/25P-well生長(zhǎng)柵極氧化膜P-well淀積多晶硅P-well110掩膜4

：P+區(qū)光刻

1、P+區(qū)光刻

2、離子注入B+，柵區(qū)有多晶硅做掩蔽，稱為硅柵自對(duì)準(zhǔn)工藝。

3、去膠P-wellP+N+N+P+N-SiP-wellP-wellP+P+2022/10/25掩膜4：P+區(qū)光刻1、P+區(qū)光刻P-wellP+111P-wellP+P-wellP+P+硼離子注入去膠2022/10/25P-wellP+P-wellP+P+硼離子注入去膠2022-112掩膜5

：N+區(qū)光刻

1、N+區(qū)光刻

2、離子注入P+，柵區(qū)有多晶硅做掩蔽，稱為硅柵自對(duì)準(zhǔn)工藝。

3、去膠P-wellP+N+N+P+N-SiP-wellP-wellP+P+N+N+2022/10/25掩膜5：N+區(qū)光刻1、N+區(qū)光刻P-wellP+113P-wellN+P-wellP+P+磷離子注入去膠P+P+N+N+2022/10/25P-wellN+P-wellP+P+磷離子注入去膠P+P+N114掩膜6

：光刻接觸孔1、淀積PSG.2、光刻接觸孔3、刻蝕接觸孔P-wellP+N+N+P+N-SiP-wellP-wellP+P+N+N+磷硅玻璃（PSG)2022/10/25掩膜6：光刻接觸孔1、淀積PSG.P-wellP+N+N115掩膜6

：光刻接觸孔P-wellP+P+N+N+淀積PSGP-wellP+P+N+N+光刻接觸孔P-wellP+P+N+N+刻蝕接觸孔P-wellP+P+N+N+去膠2022/10/25掩膜6：光刻接觸孔P-wellP+P+N+N+淀積PSG1162022/10/252022-10-18117掩膜7

：光刻鋁線1、淀積鋁.2、光刻鋁3、去膠P-wellP-wellP+P+N+N+2022/10/25掩膜7：光刻鋁線1、淀積鋁.P-wellP-wellP+118P-wellP+P+N+N+鋁線PSG場(chǎng)氧柵極氧化膜P+區(qū)P-wellN-型硅極板多晶硅N+區(qū)2022/10/25P-wellP+P+N+N+鋁線PSG場(chǎng)氧柵極氧化膜P+區(qū)P119Example:Intel0.25micronProcess5metallayersTi/Al-Cu/Ti/TiNPolysilicondielectric2022/10/25Example:Intel0.25micronPro120InterconnectImpact