數(shù)電實驗二數(shù)據(jù)報告

5/54選1數(shù)據(jù)選擇器實驗任務(wù)說明：用VHDL語言設(shè)計實現(xiàn)一個4選1數(shù)據(jù)選擇器，根據(jù)地址端的不同取值選擇不同的數(shù)據(jù)端到輸出端，仿真驗證其功能。代碼：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL; --choose1from4,dataselectorENTITYmux41IS PORT(sel:INSTD_LOGIC_VECTOR(1DOWNTO0);--twobitsofselectsignal d0,d1,d2,d3:INSTD_LOGIC; --d0-d3areinputsignals q:OUTSTD_LOGIC); --qisoutputsignalENDmux41;ARCHITECTUREbehaveOFmux41ISBEGIN PROCESS(d0,d1,d2,d3,sel) --sensitivesignals BEGIN CASEselIS WHEN"00"=>q<=d0; WHEN"01"=>q<=d1; WHEN"10"=>q<=d2; WHEN"11"=>q<=d3; WHENOTHERS=>q<='Z'; --highresistance ENDCASE; ENDPROCESS;ENDbehave;仿真波形：仿真波形分析真值表：sel[1]sel[0]q00d001d110d211d3分析：由波形圖可知，在第一個sel的周期中，當(dāng)sel=00時選擇d0輸出，此時d0等于0，輸出q=0；當(dāng)sel=01時，選擇的d1輸出，此時d1=0，輸出q=0；當(dāng)sel=10時選擇d2輸出，此時d2等于0，輸出q=0；當(dāng)sel=11時選擇d3輸出，此時d3=1，輸出q=0，其余同理，實現(xiàn)了四選一數(shù)據(jù)選擇器。共陰極7段數(shù)碼管譯碼器實驗任務(wù)說明：用VHDL語言設(shè)計實現(xiàn)一個共陰極7段數(shù)碼管譯碼器，仿真驗證其功能，并下載到實驗板測試。要求用撥碼開關(guān)設(shè)定輸入信號，7段數(shù)碼管顯示輸出信號代碼：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYseg7_1IS --seg7decoding PORT( a:INSTD_LOGIC_VECTOR(3DOWNTO0); --input b:OUTSTD_LOGIC_VECTOR(6DOWNTO0) --output );ENDseg7_1;ARCHITECTUREaaOFseg7_1ISBEGIN PROCESS(a) BEGIN CASEaIS --b6-0->abcdefg WHEN"0000"=>b<="1111110"; --0 WHEN"0001"=>b<="0110000"; --1 WHEN"0010"=>b<="1101101"; --2 WHEN"0011"=>b<="1111001"; --3 WHEN"0100"=>b<="0110011"; --4 WHEN"0101"=>b<="1011011"; --5 WHEN"0110"=>b<="1011111"; --6 WHEN"0111"=>b<="1110000"; --7 WHEN"1000"=>b<="1111111"; --8 WHEN"1001"=>b<="1111011"; --9 WHENOTHERS=>b<="0000000"; ENDCASE; ENDPROCESS;ENDaa;仿真波形：仿真波形分析真值表：a[3]a[2]a[1]a[0]b[6]b[5]b[4]b[3]b[2]b[1]b[0]00000111111010001011000020010110110130011111100140100011001150101101101160110101111170111111000081000111111191001111101110101000000001110110000000121100000000013110100000001411100000000151