IBMCA硬件架構(gòu)與動(dòng)作原理

IBMPC/AT硬體架構(gòu)與動(dòng)作原理(1).PC/ATOriginalSchematics1.TheBlocksStructure2.Decoder3.DataBusFlow4.AddressBusFlow5.OtherSignalsandISA(2).KT9System(ATIRS200MP+ALIM1535+)1.SystemBlockDiagram2.SystemStartSteps3.POST(Power-OnSelfTest)4.BIOS(3).Differences(versusCPU/PCI/ISA)1.Introduction2.CPUBusCycle3.PCI(4).IntroductiontheCompactPCIbyJRJen’01-12-05

HomWo’03-12-291IBMPC/AT原版電路之功能方塊的內(nèi)容1.系統(tǒng)時(shí)脈電路2.DRAM解碼電路3.RAS&CAS產(chǎn)生電路4.DRAM偵測電路5.DRAM定址電路6.ROMAccess電路7.Decoder8.等待電路9.刷新要求電路10.DMA控制電路11.系統(tǒng)中斷電路12.系統(tǒng)計(jì)時(shí)/計(jì)數(shù)器電路13.鍵盤控制器電路14.及時(shí)時(shí)脈電路15.NMI控制電路16.Shut-downLogic2Figure:Decoder(PC/AToriginalschematic)HLDA-DMA1CS-INTR1CS

-T/CCS-PPICS

-PGREGCS-INTR2CS-DMA2CS-CS28700~1FH20~3FH40~5FH60~7FH80~9FHA0~BFHC0~DFHE0~FFHXA5XA6XA7XA9XA8-ACK-ACK+ACK-MASTERY77Y69Y510Y411Y312Y213Y114Y015G2A4G2B5G16A1B2C3U123ALS13834IBMPC/ATIOPortAddresses1.Range00H~FFH:Systemboard2.Range100~3FFH:I/OChannel3.00H~1FH:DMAController1Registers4.20H~3FH:InterruptController1Register5.40H~5FH:ProgrammableInterruptTimer6.60H~64H:keyboardControllerbuffer7.70H:CMOSRAMaddressregisterport58.71H:CMOSRAMdataregisterPort9.80H:ManufacturingTestPort10.81H~8FH:DMApagetableaddressreg.11.A0H~BFH:Programmableinterruptctrl212.C0H~DFH:DMAController2Register13.F0H~FFH:MathCoprocessorregs.14.170H~177H:Fixeddisk1registers15.1F0H~1F7H:Fixeddisk0registers16.200H~20FH:Gamecontrolport17.201H:GamePortI/OData18.278H~27AH:ParallelPort3registers19.2F8H~2FFH:SerialPort2registers620.370H~377H:DisketteController1reg21.378H~37AH:ParallelPort2registers22.3BCH~3BEH:ParallelPort1registers23.3F0H~3FFH:DisketteController0reg24.3F8H~3FFH:SerialPort1registers25.3C0H~3CFH:VGAI/OPortregisters78042ControlRegister

(I/OPortAddress:61H)Read/WritestatusBit7=1ParitycheckBit6=1ChannelcheckBit5=1Timer2outputBit4=1TogglewitheachrefreshrequestBit3=1ChannelcheckenabledBit2=1ParitycheckenabledBit1=1SpeakdataenabledBit0=1Timer2gatetospeakerenabled

8Systembuffer36pinslotSD8~SD1562pinslotSD0~SD7U7480286U8382288U7680287U66ALS245U67LS646U5ALS245U102ALS245U11ALS24574LS612MC146818804282548237*28259*2U113ALS245RAMROMA0~A23D8~D15D0~D7SD0~SD7主機(jī)板內(nèi)DATABus的流程ExternalBufferSD8~SD15SD0~SD7MD8~MD15MD0~MD7D8~D15D0~D7SD0~SD7IVLByteBufferSD8~SD15XD0~XD7MemoryBufferSD0~SD79DIRDIR245GGATE24574ALS245ABU113SD0-SD7SD8--SD15ALS04U97F10U97F10U97F10ALS04DENNPCS#XBHE#CNRLOFF#XA0DT/R#LSA0DT/R#CKBSRBDIRCKASRAABU67E1274LS646GDIRBDT/R#74ALS245U66AD8--D15D0--D7高/低位元組和系統(tǒng)緩衝器簡圖10INTAXIORXIOWI/O

DIR功能描述

X01000H~0F7HBACPU對(duì)主機(jī)板I/O埠設(shè)備讀取

X010F8H~0FFHABCPU對(duì)80287埠設(shè)備讀取

X01100H~3FFHABCPU對(duì)擴(kuò)充板I/O埠設(shè)備讀取

X10000H~0F7HABCPU對(duì)主機(jī)板I/O埠設(shè)備寫入

X100F8H~0FFHABCPU對(duì)80287埠設(shè)備寫入

X10100H~3FFHABCPU對(duì)擴(kuò)充板I/O埠設(shè)備寫入

X1

X

XABCPU不在I/O的動(dòng)作0

X

X

XBA8259送中斷向量給CPU外在緩衝器控控制線路外在緩衝器ExternalBuffer的的OIR控制制得分析11SA0~SA19刷新位址產(chǎn)生器74LS590U7228S42SA0~SA1962腳位擴(kuò)充值

A0A1~A1980286A20~A2374LS6128237*2ROM其它與XBUS有關(guān)的組件CONVA0A0A17ALS~244A19U7574ALS573*3U56U60U73GOEA17~A23A1~A19SA0~SA7SA074ALS245*2U48DIRU38SA1~SA16ALS245U65DIRLA17~LA23LA17~LA2336腳位擴(kuò)充值A(chǔ)17~A23A17~A19XA1~XA16ALECPUHLDAMASTER74F158*3SA0~SA18RAMMA0~MA9

ADDRSELDMAAENHOLDMASTER位址匯流排方塊圖12HLDA65U7480286ALE5U8382288RESET12U8282284111213U11ALS08456U80ALS32Y5Y7Y3Y9A1510A13A17A11G19U75ALS244CPUHLDAHLDA-MASTERALE+ACKGATEALE+RESETHLDAAENBALERESETDRVAEN,BALE,RESETDRV:ATSlotsignals.AEN,BALE,RESETDRV信信號(hào)的的流程FromATslotHLDA13S1＃4S0＃5M/IO＃67U7480286S1＃3S0＃19M/IO＃18MRDC＃8MWDC＃9IORC＃11IOWC＃13U8382288A12A28A34A42G＃1Y118Y212ALS244D3D4D6D8D9D7D5D2G11OE＃1Q12Q13Q14Q15Q16Q17Q18Q19ALS573ALS573-CSROMF16GATEALE“LOW”'-MEGCS-LMEGCS82S147A23A22A21A20A19A18A17+REFRESH-RAMSELS0S1M/IO#-MEMR-MEMW-LMEGCSU49-MEMR-MEMW-SMEMR-SMEMW-IOR-IOWD06D17D28D39D411D512D613D714A617A716A01A12A23A34A45A518A619G15U?MemoryRead/Write於IORead/Write控制信號(hào)在CPU於ATslot之間的流程-LMEGCS:DccoderMemory在1MB以內(nèi)記憶體空間14MRDC#8MWTC#9IOWC#11IORC#12U8382288B15B16B17B11B12B18A2A4A8A9A3A5DIR1G#U89LS245IOW#1IOW#2MEMW#3MEMR#4U1118237*2CLR1PR4D2CLK3Q5U77F74123U77LS1251234567891011121314151617181920U87PAL16L8U122-MEMR-MEMW-IOR-IOW-IOW-IOR-MEMW-MEMRATSLOTSA0SBHE-DMAAEN"LOW""PULLUP''-XMEMR-DMAMEMRDMACLK-RESET-XMEMR-DMAMEMR-XMEMW-XIOR-XIOWXA0XBHE+5XBHEXA0+RAS-MEMW-IOR+AIOWQ1-IOCS16-AEN1-AEN2Q4+FSYS16-RES/OWSDATACONVDIR245GATE245-DMAAEN-ENDCYCMemoryRead/Write與IORead/Write控制信號(hào)在82288與8237之間的流程1516KT9SystemBlockDiagram17NS87570MS1535+DCtoDCBuckConverterLogic&Delaycircuit-DNBSWON-NBSWON-SUSB-SUSCSUSONMAINONVRONHWPG_POWERNPWROKNB_PWROKSB_PWROKCPU_PWRGD(1)RVCC(2)(3)(4)(5)(6)(7)PWRBUTTONKT9PowerOnBlockDiagram18SystemStartSteps(1)1.PowerON/OFFButtonPC87570(PCU)2.PC87570M1535+(SouthBridge)3.M1535+PC87570SUSPower(3VSUS、5VSUS)4.PC87570MainPower(3V、5V、2.5V)VHcore-NBSWON-SUSB/-SUSC-DNBSWONSUSONMAINON-VRON191.WhenwepushthePowerButton,thesignal-NBSWONwillbegeneratedandsendtothePCU(PC87570).2.AsthePCUreceivesthe-NBSWON,itwillsendthe-DNBSWONtothesouthbridge(M1535+).3.ThentheSBasserts-SUSBand-SUSCsignalstothePCU.4.ThePCUwillsendtheSUSON,MAINONand–VRONforsuspendpower,mainpowerandVHcoregenerating.SystemStartSteps(1)204.1PC87570SUSONSC1470PQ51/PQ16PQ3/PQ552.5VSUS12VSPQ8PQ403VSUS5VSUS4.2PC87570MAINONPQ61PQ44PQ50/PQ39LP2996PQ7/PQ573VAGP2.5V12VVTT_DDRPQ8PQ403V5VSUSDMAIND4.3PC87570-VRON2.5VSUSHIP6301VHcore21SystemStartSteps(2)HWPG5.MAX1632HWPG-POWERPC875706.PC87570NPWROKNB_PWROKRS200MP(NB)NB_PWROKU66PWROK7.SB_PWROKM1535+Q58Q59CPU_PWRGDPWRGOODCPU22SystemStartSteps(3)-SYS_RST8.M1535+-PCI_RST-PCI_RST9.-NB_PCIRSTRS200MPSB_PWROK-PCIRSTI/ODevices10.RS200MP-CPU_RSTCPU**CPUandallI/Odeviceshavebeenreset.23SystemStartSteps(4)11.CPU–MemoryCodeReadNorthBridge--Address(A31#~A3#):FFFFFFF012.NorthBridge:CPUCommandPCICommandCPUAddressPCIAddress13.NorthBridge–MemoryReadSouthBridge--Address(AD31~AD0):FFFFFFF014.SouthBridge:PCICommandISACommandPCIAddressISAAddress24SystemStartSteps(4)11.CPUwillgeneratethefirstcommand--MemoryCodeReadtotheNorthBridge,andtheHostaddress--(A31#~A3#):FFFFFFF0.12.WhentheNBreceivestheCPUcommandandHostaddress,ItwilltranslatetheCPUcommandtoPCIcommand--(MemoryRead),andtranslatetheHostAddresstothePCIaddress--(AD31#~AD0#):FFFFFFF0.13.ThentheNBsendsthePCIcommandandPCIaddresstotheSouthBridgeviathePCIBus.14.AStheSBreceivesthePCIcommandandPCIaddress,itwilltranslatethePCIcommandtotheISAcommand--(MEMR#)andthePCIaddresstotheISAaddress--(A19~A0):FFFFF.25SystemStartSteps(5)15.SouthBridge–MEMR#SystemROM--Address(SA17~SA0):1FFF016.ROMData–ISADataBusSouthBridge17.SouthBridge–PCIDataBusNorthBridge18.NorthBridge–HostDataBusCPU19.CPU:DecodeandExecute(GoToStep11:Decode&Execute)26SystemStartSteps(5)15.THESBwilldrivetheMEMR#commandtotheSystemROMandaccesstheROMaddress(SA17~SA0):1FFF016.SotheROMDatawillbetransferredtoSouthBridgethroughtheISABus17.AndthenthroughthePCIBus,theSouthBridgewillsendthePCIdatetotheNorthBridge18.AtthelasttheNorthBridgewillsendHostdatatotheCPUthroughtheHostBus.19.AftertheCPUfetchthehostdatawhichistransferredfromNorthBridge,itbeginstoDecode&Execute(GoToStep11:Decode&Execute).27ThefirstExecutionInstructioninPCATCPUAddress::A31~A3=FFFFFFF0CPU::CS:IP=F000:FFF0FFFF0ISAAddress::SA17~SA0=1FFF0ISAData::1FFF0:EA5BE000F030372F1FFF8:31352F393900FC005.EA5BE000F0=LongJumpF000:E05B30372F31352F3939=07/15/9928POST(Power-OnSelfTest)ProcessPOSTtestsandinitializesthefollowing:Thecentralprocessingunit(CPU)TheROMBIOS(checksum)TheCMOSRAMTheIntel8237DMAControllerThekeyboardcontrollerThebase64KSystemRAMTheProgrammableInterruptcontroller298.TheProgrammableInterruptTimer9.Thecachecontroller10.COMSRAMconfigurationdata11.TheCRTcontroller12.RAMmemoryabove64K13.Thekeyboard14.DiskettedriveAavailability15.Theserialinterfacecircuitry16.Thediskettecontroller17.Thefixeddiskcontroller18.Anyadditionalhardware30AWARDBIOSPOSTTestcodelistingPOSTCODEAwardPOSTRoutineDescriptionC0Turnoffchipsetcache.01Testprocessorflagregister.02TestallprocessorregistersexceptSS,SPandBPwithpatternFFand00.03InitializeChips(RTC,8254,8237,8259),Resetmathcoprocessor,ClearCMOSshutdownbyteandpageregister.04TestDRAMrefresh05Blankvideo,keyboardcontrollerinitialization.07TestCMOSinterfaceandbatterystatus.BEInitializechipsetwithpoweronBIOSdefaults.C1Memory-presencetest.(OEMSpecific-Testtosizeon-boardmemory)31C5C6EarlyShadow.(OEMSpecific-EarlyShadowenableforfastboot)Cachepresencetest.(Externalcachesizedetection)08Setuplowmemory(base64Kmemorytest).09Earlycacheinitialization(CyrixCPUinitialization,CacheInitialization.)0ASetupinterruptvectortable.0BTestCMOSRAMchecksum,loaddefaultvalueiftestisbad.0CInitializekeyboard(detectkeyboardtypeandsetNUM_LOCKstatus)0DInitializeanddetectvideoadapterinterface.0ETestvideomemory,writesign-onmessagetoscreen.SetupshadowRAM-Enableshadowaccording

tosetup.0FTestDMAcontroller0.10TestDMAcontroller1.3211TestDMApageregisters(74612)14TestTimer0counter215Test8259-1interruptmaskregister(port21H)16Test8259-2interruptmaskregister(portA1H)17Teststuck8259’sinterruptbits18Test8259interruptfunctionality33IBMPC/ATSystemRAMDataArea(1).Range:00Hto3FFHInterruptVectorTableInterruptVectorStoredasoffset/segmentformat(2).Range:400Hto4FFHBIOSDataAreaDatadefinitionsrelatedtoBIOSfixeddisk,diskette,Keyboard,video,……34ThefirsttwowordsofexpansionROMareaVGABIOS(CS:IP=C000:0000)ROMByteValue055H1AAH2ROMLengthin512-byteblocks3EntrypointforROMinitialization(viaFARCALL)35Differences(vs.CPU/PCI/ISA)CPUPCIISA1.Speed66/100/13333/668MHz2.PowerVcore&Vio3.3V5V3.AddressBus32/(36)32/6424bit4.DataBus6432/6416bit5.Address/DataSeparateSharedSeparate366.ControlBus(Commands/Controlsignals)CPUPCIISA6.1Types8/(32)1646.2StartADS-FRAME-BALE6.3EndReady-IRDY-&TRDY-IOCHRDY7.IDVPID[0:3]IDSEL-(Decoder)3738BUSCYCLEDEFINITIONM/IO#D/C#W/R#BusCycleInitiated000InterruptAcknowledge001Halt/SpecialCycle010I/ORead011I/OWrite100CodeRead101Reserved110MemoryRead111MemoryWrite39TransactionREQ[4:0]#(FirstClock)REQ[4:0]#(SecondClock)4321043210DeferredReply00000╳╳╳╳╳Rsvd(ignore)00001╳╳╳╳╳InterruptAcknowledge01000DSZ#╳00SpecialTransactions01000DSZ#╳01Rsvd(Centralagentresponse)01001DSZ#╳1╳BranchTraceMessage01001DSZ#╳00Rsvd(Centralagentresponse)01001DSZ#╳01I/ORead10000DSZ#╳LEN#I/OWrite10001DSZ#╳LEN#Rsvd(Ignore)1100╳DSZ#╳╳╳MemoryRead&InvalidateASZ#010DSZ#╳LEN#Rsvd(MemoryWrite)ASZ#011DSZ#╳LEN#MemoryCodeReadASZ#1D/C#=00DSZ#╳LEN#MemoryDataReadASZ#1D/C#=10DSZ#╳LEN#MemoryWrite(maynotberetried)ASZ#1W/WB#=01DSZ#╳LEN#MemoryWrite(mayberetried)ASZ#1W/WB#=01DSZ#╳LEN#TransactionTypeDefinedbyREQ#Signals40TableLEN[1:0]#SignalDataTransferLengthsLEN[1:0]#RequestInitiator’sDataTransferLength000-8Bytes0116Bytes1032Bytes11ReservedASZ[1:0]#Description000<=A[35:3]#<4GB014GB<=A[35:3]#<64GB1xReservedTableASZ[1:0]#SignalDecode41POWERGOODRelationshipatPower-OnVCCcoreVCCL2PWRGOODRESET#Clock1msRatioBCLK42RatioofprocessorCoreFrequencytoSystemBusFrequencyLINT[1]LINT[0]IGNNE#A20M#ReservedHLHH3/2HHLH2HHHH5/2LHLL3LLHL7/2LHHL4LLLH9/2LHLH5LLHH11/2LHHH6HLLL13/2HHLL7HLHL15/2HHHL8HLLHSystemBusToCoreFrequencyMultiplierConfiguration43ProcessorPCILocalBusBridge/MemoryControllerCacheDRAMLANSCSIExpBusXfaceBaseI/OsISA/EISA–MicroChannelAudioMotionvideoGraphics44ADDRESSPHASEDATAPHASEDATAPHASEDATAPHASEBUSTRANSACTIONFigure:BasicReadOperation123456789CLKFRAME#ADADDRESSDATA-1DATA-2DATA-3C/BE#BUSCMDBE#'SIRDY#WAITDATATRANSFERWAITDATATRANSFERWAITDATATRANSFERTRDY#DEVSEL#45CommandDefinitionC/BE[3::0]#CommandType0000InterruptAcknowledge0001SpecialCycle0010I/ORead0011I/OWrite0100Reserved0101Reserved0110MemoryRead0111MemoryWrite1000Reserved1001Reserved1010ConfigurationRead1011ConfigurationWrite1100MemoryReadMultiple1101DualAddressCycle1110MemoryReadLine1111MemoryWriteandInvalidate46DATAPHASEDATAPHASEDATAPHASEBUSTRANSACTION123456789CLKFRAME#ADADDRESSDATA-1DATA-3C/BE#BUSCMDBE#'S-3IRDY#WAITDATATRANSFERWAITDATATRANSFERWAITDATATRANSFERTRDY#DEVSEL#DATA-2BE#'S-1BE#'S-2ADDRESSPHASEFigure:BasicWriteOperation47PCICOMPLIANTDEVICEAD[63::32]C/BE[7::4]#AD[31::00]C/BE[3::0]#PARAddress&DataInterfaceControlFR