chap13未來(lái)趨勢(shì)與挑戰(zhàn)課件

新型器件結(jié)構(gòu)目前研發(fā)焦點(diǎn)“無(wú)光源”納米結(jié)構(gòu)制備技術(shù)19001950196019702000VacuumTubeTransistorICLSIULSI10cmcmmm10mm100nm一百年中，電子開(kāi)關(guān)器件的關(guān)鍵（最?。┏叽缈s小106倍!10-1

m10-2

m10-3

m10-5

m10-7

m器件幾何尺寸的持續(xù)減小成就了微電子技術(shù)的無(wú)處不在，產(chǎn)生了無(wú)數(shù)的應(yīng)用，造就了信息社會(huì)。DownScaling：Enabler器件幾何尺寸的減小直接導(dǎo)致：1、減小寄生電容，由此減小MOSFET的開(kāi)關(guān)時(shí)間

減小功耗2、增加單位面積晶體管的數(shù)量

增強(qiáng)電路功能

促成并行運(yùn)算

增大運(yùn)算速度器件幾何尺寸的減小最為關(guān)鍵、有效Prof.Iwai,TokyoInstTech.為什么要減小器件的幾何尺寸?WakabayashiNECLengthof18SiatomsIt’sreal(nano-device)!!體硅MOSFET技術(shù)CurrentflowingbetweentheSourceandDrainiscontrolledbythevoltageontheGateelectrodeSubstrateGateSourceDrainMetal-Oxide-SemiconductorField-EffectTransistor:柵長(zhǎng),Lg絕緣氧柵厚度,Tox結(jié)深,XjM.Bohr,IntelDeveloperForum,September2004GSDcourtesyofProf.KurodaKeioUniversity)期望得到的MOSFET特性:開(kāi)啟時(shí)驅(qū)動(dòng)電流要大（HighONcurrent）關(guān)閉時(shí)漏電流要?。↙owOFFcurrent）|GATEVOLTAGE|CURRENTVTMOSFET：一個(gè)低功耗、效率高的邏輯開(kāi)關(guān)Pwelln+sourcen+drainGateoxiden+polygateGatespacerVGLog(ID)IdealswitchVtIonIoffMOSFETswitchIoffLWS/CWD/CSourceDrainVG=VDChannelBCPVD------------N+N+N+----LWS/CWD/CSourceDrainVG=0ChannelBCPd------------N+N+N+AfterF.BOEUF,MIGAS2006薄體MOSFET使用薄體可以有效地控制漏電流，要求：TSi<Lg雙柵結(jié)構(gòu)更有利于溝道的縮短，可至Lg<10nmUltra-ThinBody(UTB)BuriedOxideSubstrateSourceDrainGateTSiLgDouble-Gate(DG)GateSourceDrainGateTSi雙柵“FinFET”P(pán)lanarDG-FETGateSourceDrainGateTSiFinWidth=TSi

LgGATESOURCEDRAIN20nm10nmY.-K.Choietal.,IEEEInt’lElectronDevicesMeeting200115nmLgFinFET:FinHeightHFIN=W/2D.Hisamotoetal.,IEEEInt’lElectronDevicesMeeting,1998N.Lindertetal.,IEEEElectronDeviceLetters,p.487,2001FinFETSourceDrainGateLgΦ<14nmΦ<10nmABMetalGateNanowireChannelMetallicSourceMetallicDrainHigh-KgatedielectricSpacerSpacerABLG<10nmd<14nmd<10nm一種可能的未來(lái)MOSFET的結(jié)構(gòu)前端工藝中的一些關(guān)鍵技術(shù)原子層級(jí)淀積Atomiclayerdeposition(ALD)實(shí)現(xiàn)柵氧層淀積的原子層級(jí)控制脈沖激光退火Pulsedlaserannealing實(shí)現(xiàn)超快、低“熱預(yù)算”（即小Dt）高溫退火等離子浸沒(méi)式注入Plasmaimmersionimplantation實(shí)現(xiàn)超淺離子注入高電導(dǎo)溝導(dǎo)工程Highmobilitychannel實(shí)現(xiàn)局域壓縮或拉伸應(yīng)力等等Prof.Iwai,TokyoInstTech.后端工藝中的一些關(guān)鍵技術(shù)Prof.Iwai,TokyoInstTech.原子層級(jí)淀積Atomiclayerdeposition(ALD)實(shí)現(xiàn)銅籽晶層和擴(kuò)散阻擋層淀積的原子層級(jí)控制多孔金屬間介質(zhì)薄膜的材料和工藝有效地減小互連體系中的寄生電容大馬士革工藝Damasceneprocessing實(shí)現(xiàn)取代傳統(tǒng)鋁布線的先進(jìn)銅互連技術(shù)三維多層金屬布線Multilevel-multilayermetallization，3D有效使用珍貴的硅表面，實(shí)現(xiàn)超大規(guī)模集成技術(shù)等等GraphenesheetSingle-walledcarbonnanotube(SWNT)Variouskindsofsemiconductingnanowires:Si,Ge,InSb,GaAs,SiC,GaN,ZnO,etc.Ref：KLATencorWavelength(I)LinewidthDeepSub-wavelengthLithoSub-wavelengthLithoOPCat180nmAggressiveOPCat<130nmProcesswindowshrinkingonaverage>30%foreachnodeImmersionLithography350nm365nm180nm248nm193nm130nm90nm65nm45nmPROCESSCONTROL:THEINVESTMENTTHATYIELDSNovelProcessing（工藝革新）：EnablerProf.Iwai,TokyoInstTech.為什么“光刻”技術(shù)如此成功?價(jià)格方面：

193nm光刻設(shè)備~20M$

一套光刻版~1M$高分辨率并能實(shí)現(xiàn)大批量生產(chǎn)！

~100wafers/hour光刻基本要求理想的光刻分辨率ResolutionGood圖形PatternshapeAny大、小圖形混合Large&smallpatternsYes對(duì)準(zhǔn)精度AlignmentGood產(chǎn)量ThroughputHigh初始價(jià)位InitialcostLow運(yùn)行費(fèi)RunningcostLowEBL的特征和優(yōu)點(diǎn)直寫(xiě)、靈活任意形狀

<0.1nm束斑直徑/寬~5nmEBL的分辨率高能：100keV高對(duì)比度的光刻膠薄光刻膠用疊層光刻膠用“硬膠”HardmaskWaferThickresistThinresistWaferHardMaskEBL分辨率的提高使用不同光刻膠的對(duì)比相等亮/暗線寬的分辨率NIL在大尺寸硅片上應(yīng)用實(shí)例NIL在多柵納米晶體管FinFET中應(yīng)用實(shí)例TopviewCrosssectionWaferSiO2poly-SiSi0.2Ge0.8SiNSTL的工藝流程，2TopviewCrosssectionWaferSiO2poly-SiSi0.2Ge0.8SiNSiNSTL的工藝流程，3TopviewCrosssectionWaferSiO2poly-SiSiNResistSTL的工藝流程，4TopviewCrosssectionWaferSiO2poly-SiSiNResistSTL的工藝流程，5TopviewCrosssectionWaferSiO2poly-SiSiNResistSTL的工藝流程，6TopviewCrosssectionWaferSiO2poly-SiSTL的工藝流程，7SiN10poly-SilinesWidth=45nmpoly-SicontactH=15nmW=15nmpoly-SiNiSi50nm150nmSiSTL的工藝流程，8FinW=35nmFinH=27nmL=70nmZhang&Qiuetal.IEEEEDLMay2008AlwiringContactholestoS/DDoubleFinchannelGateFinFETproducedusingSTLtwice常規(guī)光刻技術(shù)和標(biāo)準(zhǔn)硅薄膜工藝技術(shù)的革新和結(jié)合對(duì)細(xì)線條而言，理論上k10Pitch的大小由常規(guī)光刻技術(shù)的分辨率決定常規(guī)光刻技術(shù)的使用保證了高產(chǎn)率“側(cè)墻轉(zhuǎn)移”(STL)的特征和優(yōu)點(diǎn)2nlinesafterniterationsofspacerlithography!1stSpacers2ndSpacers3rdSpacers運(yùn)用STL技術(shù)產(chǎn)生高密度圖形Photo-lithographicallydefinedsacrificialstructuresY.-K.Choietal.,JVST-B21,2951-2955(2003)STL工藝中線條尺寸的控制CVD技術(shù)淀積的薄膜具有超常均勻性和可控性STL納米線的線寬由SiN薄膜決定STL納米線的線厚由poly-Si薄膜決定Choietal.,IEEET-ED49,436（2002）Lg

LgSTL技術(shù)得到的柵均勻的Lg通常光刻技術(shù)制備的柵不均勻的

LgSTLEBArFKanekoet.al.,IEDM2005用STL制備線條的線寬不均勻性非常小!STLSummaryIdealOpticalEBLNILSTLResolution