EDA技術(shù)（機(jī)械）實(shí)驗(yàn)報(bào)告-序列計(jì)數(shù)器

PAGEPAGE1 西華大學(xué)實(shí)驗(yàn)報(bào)告第組.第組實(shí)驗(yàn)報(bào)告（計(jì)算機(jī)類）開課學(xué)院及實(shí)驗(yàn)室：實(shí)驗(yàn)時間：年月日學(xué)生姓名學(xué)號成績學(xué)生所在學(xué)院年級/專業(yè)/班課程名稱EDA技術(shù)（機(jī)械）課程代碼實(shí)驗(yàn)項(xiàng)目名稱序列計(jì)數(shù)器項(xiàng)目代碼指導(dǎo)教師項(xiàng)目學(xué)分一、實(shí)驗(yàn)?zāi)康?.了解VHDL語言編程方法，學(xué)會熟練運(yùn)用quartus軟件2.了解如何使用VHDL設(shè)計(jì)序列計(jì)數(shù)器二、內(nèi)容與設(shè)計(jì)思想1.序列計(jì)數(shù)器是經(jīng)常出現(xiàn)在通信協(xié)議編碼器電路中的器件，其基本功能是對一個8bit寬的二進(jìn)制中出現(xiàn)的連續(xù)為0的個數(shù)進(jìn)行統(tǒng)計(jì)2.在單個時鐘脈沖時間內(nèi)，完成對一個8bit寬的二進(jìn)制中出現(xiàn)的連續(xù)為0的個數(shù)進(jìn)行統(tǒng)計(jì)，且要求只能有一串連0出現(xiàn)，即8bit中0是相鄰的。此時認(rèn)為輸出有效，并且輸出連0的個數(shù)；否則認(rèn)為無效，并且連0計(jì)數(shù)器清零，同時輸出錯誤指示信號。這里規(guī)定全1的序列為有效序列，其連0個數(shù)為0個。三、使用環(huán)境winXP或win7Quartusii編程環(huán)境核心代碼及調(diào)試過程序列計(jì)數(shù)器zero1模塊libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityzero1is port(d:instd_logic_vector(7downto0); clk,clr:instd_logic; ge:outstd_logic_vector(3downto0); alm:outstd_logic );endzero1;architectureze_arcofzero1isbegin process(clk,clr) variables:std_logic_vector(6downto0); variablesd,ss:std_logic_vector(3downto0);begin ifclr='0'then alm<='0'; elsifclk'eventandclk='1'then s(0):=d(0)xord(1); ifs(0)='1'then ss:=ss+1; endif; s(1):=d(1)xord(2); ifs(1)='1'then ss:=ss+1; endif; s(2):=d(2)xord(3); ifs(2)='1'then ss:=ss+1; endif; s(3):=d(3)xord(4); ifs(3)='1'then ss:=ss+1; endif; s(4):=d(4)xord(5); ifs(4)='1'then ss:=ss+1; endif; s(5):=d(5)xord(6); ifs(5)='1'then ss:=ss+1; endif; s(6):=d(6)xord(7); ifs(6)='1'then ss:=ss+1; endif; ifd(0)='1'then sd:=sd+1; endif; ifd(1)='1'then sd:=sd+1; endif; ifd(2)='1'then sd:=sd+1; endif; ifd(3)='1'then sd:=sd+1; endif; ifd(4)='1'then sd:=sd+1; endif; ifd(5)='1'then sd:=sd+1; endif; ifd(6)='1'then sd:=sd+1; endif; ifd(7)='1'then sd:=sd+1; endif; ifd(0)='0'then ifss>1then alm<='1'; ge<="0000"; else ge<=8-sd; endif; endif; endif; sd:="0000"; ss:="0000"; endprocess; endze_arc;disp模塊libraryieee;useieee.std_logic_1164.all;entitydispis port(d:instd_logic_vector(3downto0); q:outstd_logic_vector(6downto0) );enddisp;architecturedisp_arcofdispisbegin process(d) begin casedis when"0000"=>q<="0111111"; when"0001"=>q<="0000110"; when"0010"=>q<="1011011"; when"0011"=>q<="1001111"; when"0100"=>q<="1100110"; when"0101"=>q<="1101101"; when"0110"=>q<="1111101"; when"0111