EDA技術(shù)（機(jī)械）實(shí)驗(yàn)報(bào)告-數(shù)字信號(hào)發(fā)送和接收電路

PAGEPAGE1 西華大學(xué)實(shí)驗(yàn)報(bào)告第組.第組實(shí)驗(yàn)報(bào)告（計(jì)算機(jī)類）開課學(xué)院及實(shí)驗(yàn)室：實(shí)驗(yàn)時(shí)間：年月日學(xué)生姓名學(xué)號(hào)成績(jī)學(xué)生所在學(xué)院年級(jí)/專業(yè)/班課程名稱EDA技術(shù)（機(jī)械）課程代碼實(shí)驗(yàn)項(xiàng)目名稱數(shù)字信號(hào)發(fā)送和接收電路項(xiàng)目代碼指導(dǎo)教師項(xiàng)目學(xué)分一、實(shí)驗(yàn)?zāi)康?.了解VHDL語(yǔ)言編程方法，學(xué)會(huì)熟練運(yùn)用quartus軟件2.了解如何使用VHDL設(shè)計(jì)數(shù)字信號(hào)發(fā)送和接收電路二、內(nèi)容與設(shè)計(jì)思想1.設(shè)計(jì)一個(gè)5位數(shù)字信號(hào)發(fā)送和接收電路，在數(shù)據(jù)接收端只有在代碼傳送無(wú)誤后才把數(shù)據(jù)代碼并行輸出，串行偶校驗(yàn)檢測(cè)器可通過(guò)異或?qū)崿F(xiàn)。2.數(shù)據(jù)傳送的格式采用異步串行通信的格式，包含起始位、數(shù)據(jù)位、校驗(yàn)位、停止位和空閑位。3.此實(shí)驗(yàn)可選用兩個(gè)實(shí)驗(yàn)箱完成，一個(gè)發(fā)送數(shù)據(jù)，一個(gè)接收數(shù)據(jù)，其時(shí)鐘必須一樣，且共地三、使用環(huán)境winXP或win7Quartusii編程環(huán)境核心代碼及調(diào)試過(guò)程數(shù)字信號(hào)發(fā)送和接收電路信號(hào)發(fā)送模塊libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityfaisport(start:instd_logic;a:std_logic_vector(4downto0);clk:instd_logic;b:outstd_logic);endfa;architecturert1offaisbeginprocess(clk,a)variabletemp:std_logic_vector(6downto0);variabletmp,m:std_logic;variabletmp1:integerrange0to7;beginif(clk'eventandclk='1')thenif(m='0')thentmp:='1';endif;if(start='0')thenm:='1';temp(5downto1):=a(4downto0);temp(6):=a(4)xora(3)xora(2)xora(1)xora(0);temp(0):='0';temp:='1'&temp(6downto1);if(tmp1<7)thentmp1:=tmp1+1;elsem:='0';temp:="0000000";tmp1:=0;endif;endif;endif;b<=tmp;endprocess;endrt1;信號(hào)接收模塊libraryieee;useieee.std_logic_1164.all;entityrcvisport(clk,re:instd_logic;lmp:outstd_logic_vector(4downto0);alm:outstd_logic);endrcv;architecturercv_arcofrcvisbeginprocess(clk)variablea:std_logic;variablecnt:integerrange0to6;variableshift:std_logic_vector(5downto0);beginifclk'eventandclk='1'thenifa='0'thenifre='0'thena:='1';alm<='0';endif;elseifcnt<6thenshift:=re&shift(5downto1);cnt:=cnt+1;elsecnt:=0;a:='0';if(shift(0)xorshift(1)xorshift(2)xorshift(3)xorshift(4)xorshift(5))='0'thenlmp<=shift(4downto0);e