EDA技術(shù)（機(jī)械）實(shí)驗(yàn)報(bào)告-定時(shí)器

PAGEPAGE1 西華大學(xué)實(shí)驗(yàn)報(bào)告第組.第組實(shí)驗(yàn)報(bào)告（計(jì)算機(jī)類）開課學(xué)院及實(shí)驗(yàn)室：實(shí)驗(yàn)時(shí)間：年月日學(xué)生姓名學(xué)號(hào)成績(jī)學(xué)生所在學(xué)院年級(jí)/專業(yè)/班2012/自動(dòng)化/西華理1課程名稱EDA技術(shù)（機(jī)械）課程代碼實(shí)驗(yàn)項(xiàng)目名稱定時(shí)器項(xiàng)目代碼十指導(dǎo)教師項(xiàng)目學(xué)分一、實(shí)驗(yàn)?zāi)康?.了解VHDL語(yǔ)言編程方法，學(xué)會(huì)熟練運(yùn)用quartus軟件2.了解定時(shí)器工作原理3.了解如何使用VHDL設(shè)計(jì)一個(gè)定時(shí)器二、內(nèi)容與設(shè)計(jì)思想1.定時(shí)器是計(jì)數(shù)器和顯示器的綜合應(yīng)用。基于VHDL語(yǔ)言，用FPGA實(shí)現(xiàn)，硬件簡(jiǎn)單，性能穩(wěn)定，可充分體現(xiàn)可編程邏輯器件在數(shù)字電路中的優(yōu)越性。2.要求;整體清零；最高可定時(shí)99min；預(yù)置數(shù)時(shí)以秒速度遞增至預(yù)定時(shí)間，以分速度遞減至零。三、使用環(huán)境winXP或win7Quartusii編程環(huán)境核心代碼及調(diào)試過(guò)程定時(shí)器設(shè)計(jì)AAA邏輯功能模塊，十進(jìn)制輸出libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityaaais port(clk,clr,set:instd_logic; alm:outstd_logic; q1,q0:outstd_logic_vector(3downto0) );endaaa;architectureaaa_arcofaaaisbegin process(clk) variablecnt1,cnt0:std_logic_vector(3downto0); variablecnt:integerrange0to59; begin ifclr='0'then alm<='0'; cnt:=0; cnt1:="0000"; cnt0:="0000"; elsifclk'eventandclk='1'then ifset='0'then cnt:=0; ifcnt<"1001"then cnt0:=cnt0+1; else cnt0:="0000"; ifcnt1<"1001"then cnt1:=cnt1+1; else cnt1:="0000"; endif; endif; else ifcnt<59then cnt:=cnt+1; else cnt:=0; ifcnt0>"0000"then cnt0:=cnt0-1; ifcnt1="0000"andcnt0="0000"then alm<='1'; endif; else cnt0:="1001"; ifcnt1>"0000"then cnt1:=cnt1-1; else cnt1:="1001"; endif; endif; endif; endif; endif; q0<=cnt0; q1<=cnt1; endprocess;endaaa_arc;CH模塊，對(duì)應(yīng)片選信號(hào)送出要顯示的相應(yīng)數(shù)據(jù)libraryieee;useieee.std_logic_1164.all;entitychis port(sel:instd_logic; a1,a0:instd_logic_vector(3downto0); q:outstd_logic_vector(3downto0) );endch;architecturech_arcofchisbegin process(sel,a0,a1) begin ifsel='0'then q<=a0; else q<=a1; endif; endprocess;endch_arc;DISP模塊libraryieee;useieee.std_logic_1164.all;entitydispis port(a:instd_logic_vector(3downto0); q:outstd_logic_vector(6downto0) );enddisp;architecturedisp_arcofdispisbegin process(a) begin caseais when"0000"=>q<="0111111"; when"0001"=>q<="0000110"; when"0010"=>q<="1011011"; when"0011"=>q<="1001111"; when"0100"=>q<="1100110"; when"0101"=>q<="1101101"; when"0110"=>q<="1111101"; when"0111"=>q<="0000111"; when"1